JP2023528051A - ダイの前面でのピラー接続及び裏面での受動デバイス集積のための方法 - Google Patents
ダイの前面でのピラー接続及び裏面での受動デバイス集積のための方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
- H01L2924/1421—RF devices
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
本出願は、2020年6月1日に米国特許商標庁に出願された米国特許出願第16/889,432号の優先権を主張するものであり、その開示は参照により本明細書に組み込まれる。
Claims (30)
- 第1の表面、第2の表面、前記第1の表面と前記第2の表面との間にあり、前記第1の表面に隣接する複数のトランジスタ・セルを備える半導体層構造、及び前記トランジスタ・セルに結合された端子を備える高周波(「RF」)トランジスタ増幅器ダイと、
前記ダイの前記第2の表面上にあり、前記端子のうちの少なくとも1つに電気的に接続された少なくとも1つの受動電子部品と、
を備える、集積回路デバイス。 - 前記端子が、前記トランジスタ・セルによって画定されるRFトランジスタ増幅器の入力端子、出力端子、及び/又は接地端子を含む、請求項1に記載の集積回路デバイス。
- 前記少なくとも1つの受動電子部品が、前記ダイの前記第2の表面上の、前記RFトランジスタ増幅器のための入力インピーダンス整合回路、出力インピーダンス整合回路、及び/又は高調波終端回路の少なくとも一部を画定する、請求項2に記載の集積回路デバイス。
- 前記少なくとも1つの受動電子部品が、前記ダイの前記第2の表面上のディスクリート・コンデンサ、インダクタ、及び/又は抵抗器を含む少なくとも1つの集積受動デバイス(IPD)である、請求項1から3までのいずれか一項に記載の集積回路デバイス。
- 前記ダイの前記第2の表面上に延在し、前記少なくとも1つの受動電子部品を前記端子のうちの前記少なくとも1つに電気的に接続する金属層、
をさらに備える、請求項1から3までのいずれか一項に記載の集積回路デバイス。 - 前記金属層が第1の金属層であり、
前記第2の表面の反対側の前記第1の金属層上に絶縁体層をさらに備え、
前記少なくとも1つの受動電子部品が、前記第1の金属層の反対側の前記絶縁体層上にあり、1つ又は複数のディスクリート・コンデンサ、インダクタ、及び/又は抵抗器を画定する第2の金属層のパターンを含む、
請求項5に記載の集積回路デバイス。 - 前記ダイの前記第2の表面及び前記半導体層構造内に延在して、前記ダイの前記第2の表面上の前記金属層を前記端子のうちの前記少なくとも1つに電気的に接続する少なくとも1つの導電性ビア、
をさらに備える、請求項5に記載の集積回路デバイス。 - 前記半導体層構造がIII族窒化物材料を含み、前記ダイが前記III族窒化物材料と前記第2の表面との間に炭化ケイ素基板を含む、請求項1から7までのいずれか一項に記載の集積回路デバイス。
- 前記ダイの前記第1の表面から突出し、前記端子のうちの1つ若しくは複数に電気的接続を提供する1つ又は複数の導電性ピラー構造、
をさらに備える、請求項1から3までのいずれか一項に記載の集積回路デバイス。 - 1つ又は複数の導電性接続部を含むパッケージ基板、
をさらに備え、
前記1つ又は複数の導電性ピラー構造が、前記ダイを前記ダイの前記第1の表面に隣接する前記パッケージ基板に取り付け、前記端子のうちの前記1つ若しくは複数を前記1つ又は複数の導電性接続部に電気的に接続する、
請求項9に記載の集積回路デバイス。 - 第1の表面、第2の表面、前記第1の表面と前記第2の表面との間にあり、前記第1の表面に隣接する複数のトランジスタ・セルを備える半導体層構造、及び前記トランジスタ・セルに結合された端子を備える高周波(「RF」)トランジスタ増幅器ダイと、
前記ダイの前記第1の表面から突出し、前記端子のうちの1つ若しくは複数に電気的に接続された1つ又は複数の導電性ピラー構造と、
前記ダイの前記第2の表面及び前記半導体層構造内に延在し、前記端子のうちの少なくとも1つに電気的である、少なくとも1つの導電性ビアと、
を備える、集積回路デバイス。 - 前記端子が、前記トランジスタ・セルによって画定されるRFトランジスタ増幅器の入力端子、出力端子、及び/又は接地端子を含む、請求項11に記載の集積回路デバイス。
- 前記1つ又は複数の導電性ピラー構造が前記入力端子及び/又は前記出力端子への電気的接続を提供し、前記少なくとも1つの導電性ビアが前記接地端子への電気的接続を提供する、請求項12に記載の集積回路デバイス。
- 前記ダイが前記半導体層構造と前記ダイの前記第2の表面との間に基板を含み、前記少なくとも1つの導電性ビアが前記基板を貫いて延在し、前記半導体層構造が、前記基板上に1つ又は複数のエピタキシャル層を含む、請求項11から13までのいずれか一項に記載の集積回路デバイス。
- 前記半導体層構造がIII族窒化物材料を含み、前記基板が炭化ケイ素基板を含む、請求項14に記載の集積回路デバイス。
- 1つ又は複数の導電性接続部を含むパッケージ基板、
をさらに備え、
前記1つ又は複数の導電性ピラー構造が、前記ダイを前記ダイの前記第1の表面に隣接する前記パッケージ基板に取り付け、前記端子のうちの前記1つ若しくは複数を前記1つ又は複数の導電性接続部に電気的に接続する、
請求項11から13までのいずれか一項に記載の集積回路デバイス。 - 少なくとも1つの導電性接続部を含むパッケージ基板をさらに備え、
前記ダイが前記ダイの前記第2の表面に隣接する前記パッケージ基板に取り付けられ、前記少なくとも1つの導電性ビアが前記端子のうちの前記少なくとも1つを前記少なくとも1つの導電性接続部に電気的に接続する、
請求項11から13までのいずれか一項に記載の集積回路デバイス。 - 前記ダイの前記第2の表面上に少なくとも1つの受動電子部品をさらに備え、前記少なくとも1つの受動電子部品が前記少なくとも1つの導電性ビアによって前記端子のうちの前記少なくとも1つに電気的に接続されている、
請求項11から13までのいずれか一項に記載の集積回路デバイス。 - 第1の表面、第2の表面、前記第1の表面と前記第2の表面との間にあり、前記第1の表面に隣接する複数のトランジスタ・セルを備える半導体層構造、前記半導体層構造と前記第2の表面との間の基板、及び前記トランジスタ・セルに結合された端子を備える高周波(「RF」)トランジスタ増幅器構造を形成するステップと、
前記第1の表面から突出する1つ又は複数の導電性ピラー構造を形成して、前記端子のうちの1つ又は複数への電気的接続を提供するステップと、
前記RFトランジスタ増幅器構造を個片化して、約50~約200ミクロン以上の厚さを有する前記基板の一部を含むRFトランジスタ増幅器ダイを画定するステップと、
を含む、集積回路デバイスを製造する方法。 - 前記第1の表面と前記第2の表面との間に延在する前記ダイの側壁が、前記第2の表面に隣接する第2の部分とは異なる表面特性を有する、前記第1の表面に隣接する第1の部分を含む、請求項19に記載の方法。
- 前記第1の表面から前記第2の表面に向かって前記半導体層構造を貫いて前記基板内に延在するトレンチを前記半導体層構造内に形成して、前記ダイの前記側壁の前記第1の部分を画定するステップ、
をさらに含む、請求項20に記載の方法。 - 前記トレンチを形成するステップが前記1つ又は複数の導電性ピラー構造を形成する前に行われる、請求項21に記載の方法。
- 個片化するステップが、前記基板の前記トレンチの底部をダイシング又はソーイングして、前記ダイの前記側壁の前記第2の部分を画定するステップを含む、請求項21又は22に記載の方法。
- 前記半導体層構造がIII族窒化物材料を含み、前記基板が炭化ケイ素を含む、請求項19から23までのいずれか一項に記載の方法。
- 第1の表面、第2の表面、前記第1の表面と前記第2の表面との間にあり、前記第1の表面に隣接する複数のトランジスタ・セルを備える半導体層構造、及び前記トランジスタ・セルに結合された端子を備える高周波(「RF」)トランジスタ増幅器構造を形成するステップと、
前記第1の表面から突出する1つ又は複数の導電性ピラー構造を形成して、前記端子のうちの1つ又は複数への電気的接続を提供するステップと、
前記第2の表面内に、且つ前記半導体層構造を貫いて延在する少なくとも1つの導電性ビアを形成して、前記端子のうちの少なくとも1つへの電気的接続を提供するステップと、
を含む、集積回路デバイスを製造する方法。 - 前記RFトランジスタ増幅器が前記半導体層構造と前記第2の表面との間に基板をさらに含み、前記少なくとも1つの導電性ビアを形成するステップが
前記第1の表面をウエハ・キャリアに取り付けるステップと、
前記第2の表面に対して薄化操作を行って、前記基板の厚さを低減するステップと、
前記薄化操作に応答して、前記第1の表面が前記ウエハ・キャリアに取り付けられた状態で、前記第2の表面内に延在する前記少なくとも1つの導電性ビアを形成するステップと、
を含む、請求項25に記載の方法。 - 前記1つ又は複数の導電性ピラー構造を形成するステップが前記第1の表面を前記ウエハ・キャリアに取り付ける前に実行される、請求項26に記載の方法。
- 前記ウエハ・キャリアが第1のウエハ・キャリアであり、前記1つ又は複数の導電性ピラー構造を形成するステップが、
前記第1の表面を前記第1のウエハ・キャリアから分離するステップと、
前記第2の表面を第2のウエハ・キャリアに取り付けるステップと、
前記第2の表面が前記第2のウエハ・キャリアに取り付けられた状態で、前記第1の表面上に前記1つ又は複数の導電性ピラー構造を形成するステップと、
を含む、請求項26に記載の方法。 - 前記第1の表面が前記ウエハ・キャリアに取り付けられた状態で、前記第2の表面上に少なくとも1つの受動電子部品を形成するステップをさらに含み、
前記少なくとも1つの受動電子部品が前記少なくとも1つの導電性ビアによって前記端子のうちの前記少なくとも1つに電気的に接続される、
請求項26から28までのいずれか一項に記載の方法。 - 前記少なくとも1つの受動電子部品を形成するステップが、
前記薄化操作に応答して前記第2の表面上に第1の金属層を形成するステップと、
前記第2の表面の反対側の前記第1の金属層上に絶縁体層を形成するステップと、
前記第1の金属層の反対側の前記絶縁体層上に第2の金属層を形成及びパターニングするステップであって、前記少なくとも1つの受動電子部品が、1つ又は複数のディスクリート・コンデンサ、インダクタ、及び/又は抵抗器を画定する前記第2の金属層のパターンを含む、ステップと、
を含む、請求項29に記載の方法。
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-
2020
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US20220208758A1 (en) | 2022-06-30 |
EP4158775A2 (en) | 2023-04-05 |
US11769768B2 (en) | 2023-09-26 |
WO2021247276A2 (en) | 2021-12-09 |
TW202211380A (zh) | 2022-03-16 |
US20210375856A1 (en) | 2021-12-02 |
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