WO2014185010A1 - 半導体素子およびその製造方法、半導体モジュールおよびその製造方法、並びに、半導体パッケージ - Google Patents

半導体素子およびその製造方法、半導体モジュールおよびその製造方法、並びに、半導体パッケージ Download PDF

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WO2014185010A1
WO2014185010A1 PCT/JP2014/002239 JP2014002239W WO2014185010A1 WO 2014185010 A1 WO2014185010 A1 WO 2014185010A1 JP 2014002239 W JP2014002239 W JP 2014002239W WO 2014185010 A1 WO2014185010 A1 WO 2014185010A1
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Prior art keywords
silicon carbide
semiconductor element
main surface
semiconductor
layer
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PCT/JP2014/002239
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English (en)
French (fr)
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康行 柳瀬
努 清澤
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パナソニックＩｐマネジメント株式会社
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Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Priority to US14/428,289 priority Critical patent/US9362366B2/en
Priority to JP2015516895A priority patent/JP5942212B2/ja
Publication of WO2014185010A1 publication Critical patent/WO2014185010A1/ja

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Definitions

  • the present disclosure relates to a semiconductor element having a silicon carbide substrate and a manufacturing method thereof.
  • Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material with a larger band gap than silicon (Si), and is applied to various semiconductor devices such as power elements, environmental elements, high-temperature operating elements, and high-frequency elements. Has been. Among these, application to power elements such as switching elements and rectifying elements has attracted attention. A power element using SiC has advantages such as a significant reduction in power loss compared to a Si power element.
  • Typical switching elements among power elements using SiC are metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-semiconductor field effect transistors (MESFETs).
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • MESFETs metal-semiconductor field effect transistors
  • a voltage applied to the gate electrode can switch between an on state in which a drain current of several A (amperes) or more flows and an off state in which the drain current becomes zero.
  • a high breakdown voltage of several hundred volts or more can be realized in the off state.
  • Schottky diodes and pn diodes have been reported as rectifying elements, and both are expected as rectifying elements that realize a large current and a high breakdown voltage.
  • These power devices often employ a structure in which current flows in the front and back direction of the substrate surface.
  • patterning using a photoresist is performed on the front surface side, but ohmic junctions are almost always formed on the entire back surface side.
  • a metal electrode layer for example, a laminated electrode made of Ti / Ni / Ag
  • an ohmic electrode layer formed on the substrate For example, when the wafer is separated into individual pieces by dicing, a large stress is applied to the interface between the soft metal layer and the hard semiconductor element at the junction between the back electrode and the back surface of the semiconductor element. This becomes a factor of peeling of the back electrode.
  • stress is applied to the interface having the most different difference in thermal expansion coefficient, which leads to peeling of the back electrode. In other words, if the metal electrode layer is triggered to peel, the peeling proceeds due to thermal stress during the manufacturing process, and in some cases, the metal electrode layer peels over the entire back surface of the semiconductor element.
  • Patent Documents 1 and 2 described above it has been studied to increase the reliability of the joint portion by increasing the thickness of the solder layer, but the back surface of the semiconductor element having the silicon carbide substrate as described above. No consideration is given to the bonding reliability between the electrode and the back surface of the semiconductor element, that is, the problem of peeling of the metal electrode layer on the back surface.
  • the present disclosure provides a semiconductor element that can suppress peeling of the metal electrode layer disposed on the back surface in a semiconductor element having a silicon carbide substrate.
  • a semiconductor element disclosed in this specification includes a silicon carbide substrate having a first main surface and a second main surface, a silicon carbide layer disposed on the first main surface of the silicon carbide substrate, and silicon carbide.
  • a notch is formed along a set of sides, the ohmic electrode layer and the metal electrode layer are arranged from the second main surface to the notch surface, and the notch is
  • the cross section of the silicon carbide substrate at the end portion of the silicon carbide substrate in the cutout portion has a carbonization in the portion where the cutout portion is not formed. Smaller than the thickness of the silicon substrate, or Greater than the thickness of the silicon carbide substrate in the bottom corner.
  • Sectional drawing which shows schematic structure of the semiconductor element which concerns on exemplary embodiment of this indication Sectional drawing which expands and shows schematic structure of the notch part of the semiconductor element which concerns on exemplary embodiment of this indication (A) And (b) is sectional drawing for showing the formation process of the semiconductor element in exemplary embodiment of this indication (A) And (b) is sectional drawing for showing the formation process of the semiconductor element in exemplary embodiment of this indication (A) And (b) is sectional drawing for showing the formation process of the semiconductor element in exemplary embodiment of this indication Sectional drawing for demonstrating another example of the dicing process of the semiconductor element in exemplary embodiment of this indication
  • the figure which shows the electron micrograph of the cross-sectional shape of the recessed part which has a subtrench (A) And (b) is a figure which shows the example of arrangement
  • (A) And (b) is a figure which shows schematic structure of the other modification of the semiconductor element in illustrative embodiment of this indication.
  • (A), (b) and (c) is a figure which shows schematic structure of the other modification of the semiconductor element in illustrative embodiment of this indication.
  • Sectional drawing which shows schematic structure of the semiconductor module using the semiconductor element which concerns on exemplary embodiment of this indication (A) And (b) is sectional drawing for showing the formation process of a semiconductor module (A) And (b) is sectional drawing for showing the formation process of a semiconductor module
  • the semiconductor element includes a silicon carbide substrate having a first main surface and a second main surface, and a silicon carbide layer disposed on the first main surface of the silicon carbide substrate. And an ohmic electrode layer disposed on the second main surface of the silicon carbide substrate, and a metal electrode layer disposed on the ohmic electrode layer.
  • a cutout portion is formed at least along a pair of opposing sides.
  • the ohmic electrode layer and the metal electrode layer are disposed from the second main surface to the notch surface.
  • the notch has a corner in the shape of a cross section orthogonal to the side.
  • the thickness of the silicon carbide substrate at the end of the silicon carbide substrate in the notch is smaller than the thickness of the silicon carbide substrate in the portion where the notch is not formed, and silicon carbide at the bottom of the corner It is larger than the thickness of the substrate.
  • the cutout portion having a corner portion in the cross-sectional shape is formed in the peripheral portion of the second main surface of the silicon carbide substrate. For this reason, even when the metal electrode layer is peeled from the end face of the element, the force vector in the peeling direction runs in different directions at the corners of the notch portions, so that the peeling can be suppressed.
  • the angle formed by the corner portion of the cutout portion is smaller than 90 degrees.
  • peeling of the metal electrode layer can be more effectively suppressed.
  • the notch is formed over the entire periphery of the second main surface of the silicon carbide substrate.
  • peeling of the metal electrode layer can be suppressed over the entire periphery of the second main surface.
  • the width of the notch in the cross section passing through the diagonal line of the second main surface of the silicon carbide substrate is the second main surface of the silicon carbide substrate. It is larger than the width of the notch in the cross section passing through the line connecting the midpoints of a pair of opposing sides.
  • the stress applied to the metal electrode layer is increased, and a notch portion having a large width is disposed on the diagonal line on the back surface of the semiconductor element, so that peeling of the metal electrode layer is effectively suppressed. can do.
  • a groove is further disposed on the second main surface of the silicon carbide substrate.
  • the groove portion is arranged at a position connecting the notch portions arranged along two adjacent sides on the second main surface of the silicon carbide substrate. Has been.
  • the bubbles can be removed through the groove.
  • a step of preparing a silicon carbide substrate having a silicon carbide layer formed on a first main surface, and a circuit element having a scribe line formed on the silicon carbide layer Forming a layer and forming a recess extending in the same direction as the scribe line by anisotropic etching on a portion corresponding to the scribe line in the second main surface of the silicon carbide substrate.
  • a step of forming an ohmic electrode layer on the second main surface where the recess is formed, a step of forming a metal electrode layer on the ohmic electrode layer, and the silicon carbide along the scribe line And a step of dividing the substrate into semiconductor elements.
  • the concave portion is formed such that both side surfaces and the bottom surface form corner portions, and a sub-trench is formed in the concave portion as the corner portion.
  • the semiconductor element of the first aspect can be easily manufactured.
  • a blade is inserted from the second main surface and dicing is performed.
  • the element area on the first main surface side can be increased, and the number of chips can be increased.
  • a semiconductor module includes a semiconductor element according to any one of the first to sixth aspects, a module substrate having a wiring layer disposed on a surface thereof, and a conductive connection layer disposed on at least a part of the wiring layer.
  • the wiring layer and the metal electrode layer on the second main surface of the semiconductor element are connected via the conductive connection layer.
  • the thickness of the conductive connection layer is greater at the position of the notch than at the center of the second main surface of the semiconductor element.
  • the reliability of the semiconductor module is further improved.
  • a method for manufacturing a semiconductor module includes a step of preparing a semiconductor element according to any one of the first to sixth aspects, a step of preparing a module substrate having a wiring layer, and the wiring layer on the module substrate. Forming a conductive connection layer; and connecting the metal electrode layer on the second main surface of the semiconductor element to the wiring layer of the module substrate via the conductive connection layer.
  • the semiconductor module of the ninth aspect can be easily manufactured.
  • a semiconductor package includes the semiconductor element according to any one of the first to sixth aspects, a lead frame, and a conductive connection layer disposed on at least a part of the lead frame.
  • the lead frame and the metal electrode layer on the second main surface of the semiconductor element are connected via each other.
  • the thickness of the conductive connection layer is greater at the position of the notch than at the center of the second main surface of the semiconductor element.
  • This aspect further improves the reliability of the semiconductor package.
  • FIG. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to an exemplary embodiment of the present disclosure.
  • a semiconductor element 10 in FIG. 1 includes a silicon carbide (SiC) substrate 11.
  • the silicon carbide substrate 11 has, for example, a main surface inclined by ⁇ degrees (0 ⁇ ⁇ ⁇ 10 degrees) from the 4H—SiC (0001) plane, the substrate surface (first main surface) is on the Si surface side, and the back surface ( The second main surface) is the C surface side.
  • an epitaxial layer 12 made of epitaxially grown n-type 4H—SiC is formed as a silicon carbide layer.
  • a circuit element layer 13 is formed on the epitaxial layer 12 using a semiconductor process.
  • a circuit is formed in the circuit element layer 13 and includes a source electrode and a gate electrode.
  • An ohmic electrode layer 14 is formed on the back surface of the silicon carbide substrate 11.
  • the ohmic electrode layer 14 includes, for example, titanium and is silicided on the side in contact with the silicon carbide substrate 11.
  • the thickness is about 150 nm, for example.
  • a metal electrode layer 15 is formed on the ohmic electrode layer 14.
  • the metal electrode layer 15 is shown as a single layer in FIG. 1, it may be a single layer or a multilayer.
  • a laminated electrode of Ti / Ni / Ag is selected.
  • the Ti side is in contact with the ohmic electrode layer 14.
  • the metal electrode layer 15 is disposed when die bonding (bonding by solder, conductive adhesive, metal diffusion, or the like) to a wiring layer of a semiconductor module or a lead frame such as TO-220.
  • a notch portion 20 is formed along the side of the peripheral portion of the chip surface.
  • the cross-sectional shape orthogonal to the side of the chip surface has a corner portion 21.
  • thickness X of silicon carbide substrate 11 at the end of silicon carbide substrate 11 in notch 20 is larger than thickness Z of silicon carbide substrate 11 in the portion where notch 20 is not formed. It is small and larger than the thickness Y of silicon carbide substrate 11 at the bottom of corner portion 21.
  • the angle formed by the corner portion 21 is smaller than 90 degrees and is an acute angle.
  • the ohmic electrode layer 14 and the metal electrode layer 15 are arranged from the back surface of the silicon carbide substrate 11 to the surface of the cutout portion 20.
  • FIG. 2 is an enlarged cross-sectional view showing a schematic configuration of the notch portion 20 of the semiconductor element according to the present embodiment.
  • the corner portion 21 may have a rounded shape.
  • the angle formed by the corner portion 21 is defined by the angle ⁇ formed by the tangent line 160 near the corner portion 21 of the bottom surface 150 of the notch portion 20 and the tangent line 162 near the corner portion 21 of the side surface 152 of the notch portion 20. Is done.
  • the notch portion 20 having the corner portion 21 in the cross-sectional shape is formed on the back surface along the side of the peripheral portion. For this reason, even when the metal electrode layer 15 is peeled from the end face of the semiconductor element 10, the direction of the force vector in the peeling direction is changed at the corner portion 21 in the notch portion 20, so that the peeling progresses. Stop. Accordingly, it is possible to suppress the metal electrode layer 15 from being peeled over the entire back surface of the semiconductor element 10.
  • a silicon carbide substrate 11 having an epitaxial layer 12 as a silicon carbide layer formed on the surface (first main surface) is prepared.
  • a buffer layer n + type semiconductor layer, here, a silicon carbide layer
  • concentration is about 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 ).
  • a circuit element layer 13 is formed on the epitaxial layer 12 using a semiconductor formation process.
  • a scribe line 13 a is formed so as to divide the circuit element layer 13. Detailed description is omitted here.
  • a recess (groove) whose cross-sectional shape is rectangular with respect to the portion corresponding to the scribe line 13a on the front surface side. ) 16 is formed.
  • the recess 16 has a sub-trench 18.
  • the sub-trench refers to a portion where the corner portion is dug deeper from the trench which is the main portion of the recess.
  • the concave portion 16 extends in the same direction as the scribe line 13a, and is formed so that the two side surfaces 152 and the bottom surface 150 form corner portions 21, respectively.
  • the recess 16 has a depth of 50 ⁇ m and a width of 150 ⁇ m.
  • a specific method for forming the recess 16 is, for example, as follows. After the SiO 2 layer is formed on the back surface and the front surface of the wafer using a plasma CVD apparatus, a resist is applied on the SiO 2 layer on the back surface side. Then, alignment is performed by transmitting a front-side alignment mark through a microscope from the back side, and a resist pattern corresponding to the scribe line 13a formed on the front side of the silicon carbide substrate 11 is formed by exposure and development. Using the resist mask, the SiO 2 layer is patterned by dry etching. Using the SiO 2 layer thus formed as a mask, the back surface of silicon carbide substrate 11 is dry-etched to form recess 16.
  • the groove shape having the sub-trench 18 is formed by performing dry etching under a condition in which Cl 2 and O 2 gas are mixed at a ratio of 2: 1. By changing the mixing ratio of these gases, it is possible to control the shape of the formed sub-trench 18.
  • FIG. 7 is a photograph showing an actual cross-sectional shape having a sub-trench. In FIG. 7, a sub-trench 18 is formed in the recess 16, and the sub-trench 18 becomes a corner 21 of the notch 20 after being separated into pieces.
  • an ohmic electrode layer 14 containing titanium is deposited on the back surface of the silicon carbide substrate 11, and a heat treatment at about 800 to 1100 ° C. is performed in a nitrogen atmosphere.
  • a heat treatment at about 800 to 1100 ° C. is performed in a nitrogen atmosphere.
  • the ohmic electrode layer 14 having a nitrided surface is formed.
  • the ohmic electrode layer 14 is also formed in the recess 16.
  • a silicide reaction occurs at the interface between the silicon carbide substrate 11 and titanium, and Ti silicide is formed at least at the interface. Since the heat treatment is performed in a nitrogen atmosphere, TiN is formed on the outermost layer on the back surface side.
  • the structure when viewed from the back side, the structure is TiN / Ti / Ti silicide / SiC after the heat treatment with respect to the structure of Ti / SiC before the heat treatment.
  • the film thickness of the unreacted layer between TiN and Ti silicide changes, and sometimes becomes TiN / Ti silicide / SiC.
  • the upper wiring is aluminum and the patterning is performed by phosphoric acid wet etching, the ohmic electrode layer 14 on the back surface side is hardly etched because TiN having a nitrided surface is formed.
  • patterning is performed by dry etching, it is preferable to form a metal such as Cu, Au, or Pt on the ohmic electrode layer 14 in order to prevent corrosion of the ohmic electrode layer 14.
  • a metal electrode layer 15 is formed on the ohmic electrode layer 14. Similarly to the ohmic electrode layer 14, the metal electrode layer 15 is also formed in the recess 16.
  • a Ti layer, a Ni layer, and an Ag layer are used as an example of the metal electrode layer 15.
  • the layer structure of the metal electrode layer 15 is appropriately selected depending on the package form of the semiconductor element 10. As other examples, a Ti / Ni / Au layer, a Cr / NiCr / Ni / Ag layer, and of course other combinations may be used.
  • the silicon carbide substrate 11 is separated into semiconductor elements 10 along the scribe lines 13a.
  • the dicing film 31 is attached to the circuit element layer 13 side, and the silicon carbide substrate 11 is diced by inserting a blade 32 from the back side using a dicer. That is, the blade 32 enters from the recess 16.
  • the blade 32 may be incident from the surface side of the silicon carbide substrate 11 and separated into pieces. In this case, the blade 32 enters from the scribe line 13a.
  • the shape of the dicing blade 32 is narrowed toward the tip. Therefore, as shown in FIG. 5B, when the blade 32 is incident from the back surface side of the silicon carbide substrate 11, the end surface of the semiconductor element 10 has a reverse bevel shape, and chipping on the front surface side is suppressed.
  • the inverted bevel shape means that the width of the semiconductor element 10 is narrowed from the front surface (first main surface) on which the circuit element layer 13 is disposed to the back surface (second main surface) of the semiconductor element 10. It means that it is inclined. For this reason, the scribe line 13a on the surface side of the silicon carbide substrate 11 can be thinned. As a result, it is possible to obtain an effect that the element area on the surface side can be increased or the number of chips can be increased.
  • the notch portion 20 having the corner portion 21 in the cross-sectional shape is formed in the peripheral portion of the back surface of the semiconductor element 10. For this reason, even when the metal electrode layer 15 is peeled off from the element end face at the interface between the metal electrode layer 15 and the ohmic electrode layer 14 due to thermal stress due to heat generation during the manufacturing process such as the dicing process or the element operation. Since the direction of the force vector in the peeling direction changes at the corner 21 of the notch 20, the peeling can be stopped. Therefore, it can suppress that the metal electrode layer 15 peels over the whole surface.
  • the notch 20 is formed over the entire periphery of the chip surface on the back surface of the silicon carbide substrate 11 of the semiconductor element 10.
  • the present invention is not limited to this.
  • notches 20a and 20b are formed along a pair of opposing sides, and the other pair of sides is cut. It is good also as a structure in which the notch part is not formed.
  • the dicing method may differ depending on the direction, such as using dicing in one direction and cleaving in the other direction. And about a direction using the method with low possibility of peeling of the metal electrode layer 15 like cleavage, a notch part shall not be provided. Thereby, the manufacturing process can be simplified.
  • the notch portion 20 is arranged with an equal width over the entire peripheral portion of the chip surface on the back surface of the silicon carbide substrate 11 of the semiconductor element 10. It was supposed to be. However, the present invention is not limited to this.
  • FIG. 9A is a plan view showing a schematic configuration of a modified example of the semiconductor element according to the present embodiment.
  • 9B is a cross-sectional view of the AA portion of the semiconductor element shown in FIG. 9A
  • FIG. 9C is a cross-sectional view of the BB portion of the semiconductor element shown in FIG. 9B.
  • AA portion corresponds to a diagonal line on the back surface of silicon carbide substrate 11
  • BB portion corresponds to a line connecting midpoints of a pair of opposing sides on the back surface of silicon carbide substrate 11.
  • configurations other than the silicon carbide substrate 11 among the semiconductor elements are omitted.
  • the width of the cutout portion 25 in the AA portion is larger than the width of the cutout portion 25 in the BB portion. That is, the width of notch 25 in the cross section passing through the diagonal line on the back surface of silicon carbide substrate 11 is the notch in the cross section passing through the line connecting the midpoints of a pair of opposing sides on the back surface of silicon carbide substrate 11.
  • the cutout portion 25 may be disposed so as to be larger than the width of the portion 25. In this way, the stress applied to the metal electrode layer is increased, and the notch 25 having a large width is arranged on the diagonal line on the back surface of the semiconductor element, so that the metal electrode layer can be effectively peeled off. Can be suppressed. Further, when the semiconductor element is mounted with a conductive material such as solder, the area where the thickness of the solder is thick can be increased, so that reliability during mounting can be increased.
  • FIG. 10A is a plan view showing a schematic configuration of another modified example of the semiconductor element according to this embodiment, and FIG. 10B is a cross-sectional view of the semiconductor element.
  • FIG. 11A is a plan view showing a schematic configuration of another modified example of the semiconductor element according to the present embodiment, and FIG. 11B is a cross-sectional view of the AA portion of the semiconductor element.
  • 11 (c) is a cross-sectional view of the BB portion of the semiconductor element.
  • AA portion corresponds to a diagonal line on the back surface of silicon carbide substrate 11
  • BB portion corresponds to a line connecting midpoints of a pair of opposing sides on the back surface of silicon carbide substrate 11. 10 and 11, the configuration of the semiconductor element other than the silicon carbide substrate 11 is omitted.
  • one groove portion 300 is arranged along the inner periphery of the notch portion 20 at a distance from the notch portion 20 on the back surface of the semiconductor element.
  • four grooves 400 are formed on the back surface of the semiconductor element so as to be orthogonal to the diagonal line on the back surface of the semiconductor element so as to connect the notches 20 arranged along two adjacent sides. Is arranged.
  • the groove portion 300 is used.
  • 400 also changes the direction of the force vector in the peeling direction even at the corners, so that peeling can be further suppressed. Furthermore, in the example shown in FIG. 11, since the groove part 400 is arranged so as to connect the notch parts 20 arranged along two adjacent sides, bubbles are generated when the semiconductor element is mounted with solder. Even in this case, the bubbles can be removed through the groove 400.
  • the sub-trench is provided at the bottom of the grooves 300 and 400 in the example shown in FIGS. 10 and 11, but the present invention is not limited to this.
  • the sub-trench may not be disposed at the bottom of the groove, and the bottom of the groove may be flat.
  • FIG. 12 is a cross-sectional view showing a schematic configuration of an example of a semiconductor module using the semiconductor element according to the above-described embodiment. Note that FIG. 12 illustrates the semiconductor element 10 and the outline of the periphery thereof, and illustration of a sealing resin layer, a case, and the like formed by a normal semiconductor module is omitted.
  • a semiconductor module 100 of FIG. 12 includes the semiconductor element 10 shown in the exemplary embodiment of the present disclosure and a module substrate 101 having wiring layers 102a, 102b, and 102c formed on the surface thereof.
  • the wiring layer 102a is a wire bonding pattern
  • the wiring layer 102b is an element mounting portion
  • the wiring layer 102c is a connection wiring layer for connecting the module substrate 101 and a base substrate (not shown).
  • a conductive connection layer 103 made of solder, a conductive adhesive, or the like is disposed on the wiring layer 102 b, and the metal electrode layer on the back surface of the wiring layer 102 b and the semiconductor element 10 through the conductive connection layer 103. 15 is connected.
  • the conductive connection layer 103 penetrates to the notch 20, and therefore, the thickness of the conductive connection layer 103 is thicker at the position of the notch 20 than the center of the back surface of the semiconductor element 10. Further, the wiring layer 102 a and an electrode (not shown) disposed on the circuit element layer 13 on the surface of the semiconductor element 10 are connected by the wire 104.
  • the peeling of the metal electrode layer 15 on the back surface of the semiconductor element 10 is suppressed as in the above-described embodiment.
  • the conductive connection layer 103 is thick in the cutout portion 20, the reliability of the semiconductor module 100 is improved. This is because the thickness of the conductive connection layer 103 at the outer periphery of the chip where the thermal stress is greatest can be increased, thereby suppressing the occurrence of cracks in the conductive connection layer 103 due to the thermal stress during operation. It is.
  • a copper foil 102 is attached to both surfaces of the insulating module substrate 101.
  • a direct bonding method in which the substrate and the copper plate are directly bonded can be cited.
  • the material of the module substrate 101 ceramics such as alumina, aluminum nitride, silicon nitride, or the like is selected.
  • the thickness of the module substrate 101 is, for example, 0.5 mm.
  • Various materials for the module substrate 101 are selected depending on the design value of the thermal resistance and breakdown voltage of the module.
  • pure copper foil etc. are used as a raw material of the copper foil 102, for example, is 0.2 mm thick.
  • the thickness of the copper foil 102 is determined by the design value of the current flowing through the semiconductor element 10, and the thickness increases as the amount of current increases.
  • a predetermined region is selectively removed by using a well-known photolithography method and etching method, and a wiring layer 102b functioning as an element mounting portion, a circuit (not shown) Then, a wiring layer 102a that functions as a pattern for wire bonding and a wiring layer 102c that functions as a wiring layer for connection to the base substrate are formed.
  • Ni plating or Ni / Au plating may be performed on the copper wiring by plating after patterning. By forming the plating film, the formation of an oxide film on the copper surface can be suppressed, and the bonding reliability of solder bonding can be improved.
  • a solder bump is formed by applying a conductive connection layer 103 such as solder and performing reflow.
  • the solder used here melts the bonding solder and moves the semiconductor element 10 even when heat treatment is performed when the wiring layer 102c disposed on the back surface of the module substrate is connected to a base substrate (not shown here).
  • a high melting point solder is selected so that it will not be damaged.
  • a high melting point solder material such as Au—Ge solder or Au—Sn solder is selected.
  • the semiconductor element 10 is mounted on the conductive connection layer 103, and reflow is performed to form a junction.
  • the solder since the solder has fluidity, the solder enters the notch 20 formed in the peripheral portion on the back surface of the semiconductor element 10, thereby increasing the thickness of the conductive connection layer 103 in the peripheral portion on the back surface of the semiconductor element 10. Become.
  • the wire 104 is formed by wire bonding from the surface of the semiconductor element 10 toward the wiring layer 102a on the module substrate 101. Thereby, the semiconductor module 100 as shown in FIG. 12 is completed.
  • the semiconductor module described above not only the effect of stopping the peeling of the metal electrode layer 15 described in the exemplary embodiment of the present disclosure, but also the notch 20 formed in the periphery of the back surface of the semiconductor element 10.
  • the reliability of the semiconductor module can be improved by the conductive connection layer 103 that is thickened.
  • FIG. 15 is a cross-sectional view showing a schematic configuration of an example of a semiconductor package using the semiconductor element according to the embodiment described above.
  • the semiconductor package 200 shown here has substantially the same configuration as the semiconductor module described above, except that the semiconductor element 10 is connected to the lead frame 201 via the conductive connection layer 203. That is, a conductive connection layer 203 made of solder, conductive adhesive, or the like is disposed on the lead frame 201, and the metal electrode on the back surface of the lead frame 201 and the semiconductor element 10 is interposed via the conductive connection layer 203. Layer 15 is connected.
  • the conductive connection layer 203 penetrates to the notch 20, and therefore, the thickness of the conductive connection layer 203 is thicker at the position of the notch 20 than the center of the back surface of the semiconductor element 10. Further, another lead frame 205 and the circuit element layer 13 on the surface of the semiconductor element 10 are connected by a wire 204.
  • the peeling of the metal electrode layer 15 on the back surface of the semiconductor element 10 is suppressed as in the above-described embodiment.
  • the conductive connection layer 203 is thick in the cutout portion 20, the reliability of the semiconductor package 200 is improved. This is because the thickness of the conductive connection layer 203 at the outer peripheral portion of the chip where the thermal stress is greatest can be increased, thereby suppressing the occurrence of cracks in the conductive connection layer 203 due to the thermal stress during operation. It is.
  • the semiconductor package described above not only the effect of stopping the peeling of the metal electrode layer 15 described in the exemplary embodiment of the present disclosure, but also the notch 20 formed in the peripheral portion of the back surface of the semiconductor element 10.
  • the reliability of the semiconductor package can be improved by the conductive connection layer 203 that is thickened.
  • the present disclosure is suitably used for various semiconductor devices that require high breakdown voltage characteristics and reliability, for example.
  • it is suitably used for a diode or a transistor using a vertical SiC substrate.

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Abstract

　炭化珪素基板（１１）の第２の主面上にオーミック電極層（１４）が配置され、オーミック電極層（１４）上に金属電極層（１５）が配置されている。炭化珪素基板（１１）の第２の主面の周辺部において、少なくとも対向する一組の辺に沿って、切り欠き部（２０）が形成されている。切り欠き部（２０）は、第２主面の辺に直交する断面の形状が角部（２１）を有している。この断面において、炭化珪素基板（１１）の厚みは、切り欠き部（２０）における基板端部では、切り欠き部（２０）が形成されていない部分よりも小さく、角部（２１）の底よりも大きい。

Description

半導体素子およびその製造方法、半導体モジュールおよびその製造方法、並びに、半導体パッケージ
　本開示は、炭化珪素基板を有する半導体素子およびその製造方法に関する。
　炭化珪素（シリコンカーバイド：ＳｉＣ）は、珪素（Ｓｉ）に比べてバンドギャップの大きな高硬度の半導体材料であり、パワー素子、耐環境素子、高温動作素子、高周波素子等の種々の半導体装置に応用されている。中でも、スイッチング素子や整流素子などのパワー素子への応用が注目されている。ＳｉＣを用いたパワー素子は、Ｓｉパワー素子よりも電力損失を大幅に低減できるなどの利点がある。
　ＳｉＣを用いたパワー素子のうち代表的なスイッチング素子は、金属－酸化物－半導体電界効果トランジスタ（ＭＯＳＦＥＴ）や金属－半導体電界効果トランジスタ（ＭＥＳＦＥＴ）である。このようなスイッチング素子では、ゲート電極に印加する電圧によって、数Ａ（アンペア）以上のドレイン電流が流れるオン状態と、ドレイン電流がゼロとなるオフ状態とをスイッチングすることができる。また、ＳｉＣによれば、オフ状態のとき、数百Ｖ以上の高耐圧を実現できる。また他にも整流素子として、ショットキーダイオードやｐｎダイオードが報告されており、いずれも大電流、高耐圧を実現する整流素子として期待されている。
　これらのパワーデバイスは、基板面の表裏方向に電流を流す構造が多く採用されている。この場合、表面側はフォトレジストを用いたパターニング加工が施されるが、裏面側はほぼ全面にオーミック接合を形成する場合がほとんどである。
　これらのパワー素子をモジュールにする場合には、裏面側の電極とモジュール基板の配線層との接続には、半田などの導電材料を介して、全面で接合が形成される。そのため、動作時には、パワー素子（Ｓｉ，ＳｉＣ，ＧａＮなど）と配線層材料（主に銅など）との熱膨張係数差に応じた熱応力が加わることによって、接合部分の信頼性が大きな問題となる。
　この接合部分の信頼性を向上させるために、個片化する前にチップの外周部に相当する部分の裏面に予めダイサーによるハーフカットによって凹みを形成しておき、個片化して実装する際にその空間に半田を充填させることによって、チップ外周部の半田層の厚みを厚くし、接合信頼性を向上させる方法が検討されている。（特許文献１、２を参照）
特開昭５６－４８１４２号公報 特開平６－１７７１７８号公報
　炭化珪素基板を有する半導体素子の場合、裏面に形成した金属電極層（例えばＴｉ／Ｎｉ／Ａｇによる積層電極）が、基板に形成したオーミック電極層から剥離しやすい、という問題がある。例えば、ウェハをダイシングによって個片化する際に、裏面電極と半導体素子裏面との接合部において、柔らかい金属層と硬い半導体素子間との界面に大きなストレスが加わる。これが、裏面電極の剥離の要因となる。また、半導体素子をモジュール化した際に、最も熱膨張係数差の異なる界面に応力が加わるため、これが裏面電極の剥離に繋がる。すなわち、金属電極層に剥離のきっかけがあれば、製造工程中の熱ストレスによって剥離が進行してしまい、場合によっては、金属電極層が半導体素子の裏面全体にわたって剥離してしまう。
　一方、上述した特許文献１，２では、半田層の厚みを厚くすることによって接合部の信頼性を高めることについては検討されているが、上のような、炭化珪素基板を有する半導体素子における裏面電極と半導体素子裏面との接合信頼性、すなわち裏面の金属電極層の剥離の問題に関しては、何ら検討されていない。
　そこで、本開示は、炭化珪素基板を有する半導体素子において、裏面に配置された金属電極層の剥離を抑制可能にする半導体素子を提供する。
　本明細書において開示される半導体素子は、第１の主面および第２の主面を有する炭化珪素基板と、炭化珪素基板の第１の主面上に配置された炭化珪素層と、炭化珪素基板の第２の主面上に配置されたオーミック電極層と、オーミック電極層上に配置された金属電極層とを備え、炭化珪素基板の第２の主面の周辺部において、少なくとも、対向する一組の辺に沿って、切り欠き部が形成されており、オーミック電極層および金属電極層は、第２の主面上から切り欠き部表面上にわたって配置されており、切り欠き部は、辺に直交する断面の形状が、角部を有しており、前記断面において、切り欠き部における炭化珪素基板の端部での炭化珪素基板の厚みは、切り欠き部が形成されていない部分における炭化珪素基板の厚みよりも小さく、かつ角部の底における炭化珪素基板の厚みよりも大きい。
　本明細書において開示される技術によると、炭化珪素基板を有する半導体素子において、裏面に配置された金属電極層の剥離を抑制することが可能となる。
本開示の例示的な実施形態に係る半導体素子の概略構成を示す断面図 本開示の例示的な実施形態に係る半導体素子の切り欠き部の概略構成を拡大して示す断面図 （ａ）および（ｂ）は本開示の例示的な実施形態における半導体素子の形成工程を示すための断面図 （ａ）および（ｂ）は本開示の例示的な実施形態における半導体素子の形成工程を示すための断面図 （ａ）および（ｂ）は本開示の例示的な実施形態における半導体素子の形成工程を示すための断面図 本開示の例示的な実施形態における半導体素子のダイシング工程の別の例を示すための断面図 サブトレンチを有する凹部の断面形状の電子顕微鏡写真を示す図 （ａ）および（ｂ）は切り欠き部の配置の例を示す図 （ａ），（ｂ）および（ｃ）は本開示の例示的な実施形態における半導体素子の一変形例の概略構成を示す図 （ａ）および（ｂ）は本開示の例示的な実施形態における半導体素子の他の変形例の概略構成を示す図 （ａ），（ｂ）および（ｃ）は本開示の例示的な実施形態における半導体素子の他の変形例の概略構成を示す図 本開示の例示的な実施形態に係る半導体素子を用いた半導体モジュールの概略構成を示す断面図 （ａ）および（ｂ）は半導体モジュールの形成工程を示すための断面図 （ａ）および（ｂ）は半導体モジュールの形成工程を示すための断面図 本開示の例示的な実施形態に係る半導体素子を用いた半導体パッケージの概略構成を示す断面図
　本開示の第１態様では、半導体素子は、第１の主面および第２の主面を有する炭化珪素基板と、前記炭化珪素基板の前記第１の主面上に配置された炭化珪素層と、前記炭化珪素基板の前記第２の主面上に配置されたオーミック電極層と、前記オーミック電極層上に配置された金属電極層とを備える。前記炭化珪素基板の前記第２の主面の周辺部において、少なくとも、対向する一組の辺に沿って、切り欠き部が形成されている。前記オーミック電極層および前記金属電極層は、前記第２の主面上から前記切り欠き部表面上にわたって配置されている。前記切り欠き部は、前記辺に直交する断面の形状が、角部を有している。前記断面において、切り欠き部における炭化珪素基板の端部での炭化珪素基板の厚みは、切り欠き部が形成されていない部分における炭化珪素基板の厚みよりも小さく、かつ角部の底における炭化珪素基板の厚みよりも大きい。
　この態様によると、炭化珪素基板の第２の主面の周辺部において、断面形状が角部を有している切り欠き部が形成されている。このため、素子端面から金属電極層の剥離が生じた場合であっても、切り欠き部の角部において剥離方向の力のベクトルが異なる向きに走るため、剥離を抑えることができる。
　第２態様では、第１態様の半導体素子において、前記切り欠き部が有する前記角部がなす角度は、９０度よりも小さい。
　この態様によると、金属電極層の剥離を、より効果的に抑えることができる。
　第３態様では、第１態様の半導体素子において、前記切り欠き部は、前記炭化珪素基板の前記第２の主面の周辺部全体にわたって、形成されている。
　この態様によると、第２の主面の周辺部全体にわたって、金属電極層の剥離を抑えることができる。
　第４態様では、第３態様の半導体素子において、前記炭化珪素基板の前記第２の主面の対角線を通る断面での前記切り欠き部の幅は、前記炭化珪素基板の前記第２の主面における対向する一組の辺の中点同士を結ぶ線を通る断面での切り欠き部の幅よりも大きい。
　この態様によると、金属電極層にかかる応力が大きくなる、半導体素子の裏面の対角線上において、太い幅を有する切り欠き部が配置されることになるため、金属電極層の剥離を効果的に抑制することができる。
　第５態様では、第３態様の半導体素子において、前記炭化珪素基板の前記第２の主面に、溝部がさらに配置されている。
　この態様によると、金属電極層とオーミック電極層との界面において素子端面から金属電極層の剥離が生じた場合であっても、切り欠き部の角部に加えて、溝部の角部においても剥離方向の力のベクトルの向きが変わるため、剥離をさらに抑制することができる。
　第６態様では、第５態様の半導体素子において、前記溝部は、前記炭化珪素基板の前記第２の主面において、隣接する２つの辺に沿って配置された前記切り欠き部をつなぐ位置に配置されている。
　この態様によると、半導体素子を半田で実装する際に気泡が生じた場合であっても、溝部を通して気泡を除去することができる。
　第７態様では、半導体素子の製造方法として、第１の主面上に炭化珪素層が形成された炭化珪素基板を準備する工程と、前記炭化珪素層上に、スクライブラインが形成された回路素子層を形成する工程と、前記炭化珪素基板の第２の主面のうち、前記スクライブラインに対応する部分に対して、異方性エッチングにより、前記スクライブラインと同一方向に延びる凹部を形成する工程と、前記凹部が形成された前記第２の主面上に、オーミック電極層を形成する工程と、前記オーミック電極層上に金属電極層を形成する工程と、前記スクライブラインに沿って前記炭化珪素基板を半導体素子に個片化する工程とを備える。前記凹部は、両側面と底面とがそれぞれ角部をなすように形成され、前記凹部に、前記角部として、サブトレンチが形成されている。
　この態様によると、第１態様の半導体素子を、容易に製造することができる。
　第８態様では、第７態様の半導体素子の製造方法において、前記個片化する工程において、前記第２の主面からブレードを入れて、ダイシングを行う。
　この態様によると、第１の主面側の素子面積を大きくでき、また、チップの取れ数を増やすことができる。
　第９態様では、半導体モジュールは、第１から第６態様のいずれかの半導体素子と、表面に配線層が配置されたモジュール基板と、前記配線層の少なくとも一部上に配置された導電接続層とを備え、前記導電接続層を介して、前記配線層と、前記半導体素子の前記第２の主面上における前記金属電極層とが、接続されている。
　この態様によると、信頼性の高い半導体モジュールが実現される。
　第１０態様では、第９態様の半導体モジュールにおいて、前記導電接続層の厚さは、前記半導体素子の前記第２の主面の中央部よりも、前記切り欠き部の位置の方が厚い。
　この態様によると、半導体モジュールの信頼性がさらに向上する。
　第１１態様では、半導体モジュールの製造方法は、第１から第６態様のいずれかの半導体素子を準備する工程と、配線層を有するモジュール基板を準備する工程と、前記モジュール基板の前記配線層上に、導電接続層を形成する工程と、前記導電接続層を介して、前記半導体素子の前記第２の主面上における前記金属電極層を、前記モジュール基板の前記配線層に接続する工程とを備えている。
　この態様によると、第９態様の半導体モジュールを、容易に製造することができる。
　第１２態様では、半導体パッケージは、第１から第６態様のいずれかの半導体素子と、リードフレームと、前記リードフレームの少なくとも一部上に配置された導電接続層とを備え、前記導電接続層を介して、前記リードフレームと、前記半導体素子の前記第２の主面上における前記金属電極層とが接続されている。
　この態様によると、信頼性の高い半導体パッケージが実現される。
　第１３態様では、第１２態様の半導体パッケージにおいて、前記導電接続層の厚さは、前記半導体素子の前記第２の主面の中央部よりも、前記切り欠き部の位置の方が厚い。
　この態様により、半導体パッケージの信頼性がさらに向上する。
　なお、上述した各要素を適宜組み合わせたものも、本件特許出願によって特許による保護を求める発明の範囲に含まれうる。
　以下、本開示の例示的な実施の形態について図面を参照して説明する。なお、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。
　図１は本開示の例示的な実施形態に係る半導体素子の概略構成を示す断面図である。図１の半導体素子１０は、炭化珪素（ＳｉＣ）基板１１を備えている。炭化珪素基板１１は例えば、４Ｈ－ＳｉＣ（０００１）面からθ度（０≦θ≦１０度）傾いた主面を有し、基板表面（第１の主面）がＳｉ面側で、裏面（第２の主面）がＣ面側である。炭化珪素基板１１の表面に、例えばエピタキシャル成長したｎ型４Ｈ－ＳｉＣであるエピタキシャル層１２が炭化珪素層として形成されている。エピタキシャル層１２の上に半導体プロセスを用いて回路素子層１３が形成されている。回路素子層１３には回路が形成されており、ソース電極及びゲート電極を備える。
　炭化珪素基板１１の裏面にはオーミック電極層１４が形成されている。オーミック電極層１４は、ここでは例えばチタンを含み、炭化珪素基板１１と接している側においてシリサイド化されている。厚さは例えば１５０ｎｍ程度である。オーミック電極層１４上には金属電極層１５が形成されている。金属電極層１５は、図１では１層で図示しているが、単層であっても多層であっても差し支えない。金属電極層１５の候補として、例えばＴｉ／Ｎｉ／Ａｇの積層電極が選択される。このとき、Ｔｉ側がオーミック電極層１４に接する構造となる。この金属電極層１５は、半導体モジュールの配線層やＴＯ－２２０等のリードフレームにダイボンディング(半田や導電性接着剤、金属拡散などによる接合)する際に配置される。
　そして、炭化珪素基板１１の裏面において、チップ表面の周辺部の辺に沿って、切り欠き部２０が形成されている。この切り欠き部２０では、チップ表面の辺に直交する断面の形状が、角部２１を有している。図１に示すように、切り欠き部２０における炭化珪素基板１１の端部での炭化珪素基板１１の厚みＸは、切り欠き部２０が形成されていない部分における炭化珪素基板１１の厚みＺよりも小さく、かつ角部２１の底における炭化珪素基板１１の厚みＹよりも大きい。また、角部２１がなす角度は９０度よりも小さく、鋭角になっている。オーミック電極層１４および金属電極層１５は、炭化珪素基板１１の裏面上から切り欠き部２０表面上にわたって配置されている。
　図２は、本実施形態に係る半導体素子の切り欠き部２０の概略構成を拡大して示す断面図である。図２に示すように、角部２１は丸みを帯びた形状であってもよい。このとき、角部２１がなす角度は、切り欠き部２０の底面１５０の角部２１近傍における接線１６０と、切り欠き部２０の側面１５２の角部２１近傍における接線１６２とのなす角度θにより定義される。
　このように、本実施形態に係る半導体素子１０は、裏面において、周辺部の辺に沿って、断面形状に角部２１を有する切り欠き部２０が形成されている。このため、半導体素子１０の端面から金属電極層１５の剥離が生じた場合であっても、切り欠き部２０における角部２１において、剥離方向の力のベクトルの向きが変わるため、剥離の進行が止まる。したがって、金属電極層１５が半導体素子１０の裏面全面にわたって剥離してしまうことを抑制することができる。
　以下、半導体素子１０の製造方法について、図３から図６を用いて説明する。
　まず、図３（ａ）に示すように、表面（第１の主面）に炭化珪素層としてのエピタキシャル層１２を形成した炭化珪素基板１１を準備する。このとき、その界面にバッファー層（ｎ+型の半導体層、ここでは炭化珪素層）を約０．５から４μｍ程度（濃度は１ｘ１０１６から１ｘ１０１９ｃｍ－３程度）形成しておいてもよい。次に図３（ｂ）に示すように、エピタキシャル層１２の上に半導体形成プロセスを用いて回路素子層１３を形成する。また、回路素子層１３を区切るようにスクライブライン１３ａを形成する。ここでは詳細な説明は省略する。
　次に、図４（ａ）に示すように、炭化珪素基板１１の裏面（第２の主面）において、表面側のスクライブライン１３ａに対応した部分に対して、断面形状が矩形の凹部（溝）１６を形成する。凹部１６はサブトレンチ１８を有する。なお、本開示において、サブトレンチとは、凹部の主たる部分であるトレンチから、角部がさらに深く掘り下げられた部分のことをいう。凹部１６はスクライブライン１３ａと同一方向に延びており、２つの側面１５２と底面１５０とがそれぞれ角部２１をなすように、形成される。この凹部１６は例えば、深さ５０μｍ、幅１５０μｍである。
　凹部１６の具体的な形成方法は、例えば次のとおりである。ウェハ裏面及び表面に、プラズマＣＶＤ装置を用いてＳｉＯ２層を形成した後に、裏面側のＳｉＯ２層上にレジストを塗布する。そして、裏面側から顕微鏡で表面側のアライメント用マークを透過させてアライメントをとり、炭化珪素基板１１の表面側に形成されたスクライブライン１３ａに対応したレジストパターンを露光・現像により形成する。そのレジストマスクを利用して、ＳｉＯ２層をドライエッチングによりパターニングする。このようにして形成されたＳｉＯ２層をマスクとして、炭化珪素基板１１の裏面をドライエッチングすることによって、凹部１６を形成する。例えば、Ｃｌ２とＯ２ガスを２：１の比率で混合した条件でドライエッチングを行うことによって、サブトレンチ１８を持つ溝形状が形成される。これらのガスの混合比率を変えることによって、形成されるサブトレンチ１８の形状を制御することが可能となる。図７はサブトレンチを持つ実際の断面形状を示す写真である。図７において、凹部１６には、サブトレンチ１８が形成されており、このサブトレンチ１８が、個片化後に、切り欠き部２０の角部２１となる。
　次に、炭化珪素基板１１の裏面にチタンを含むオーミック電極層１４を堆積し、８００から１１００℃程度の熱処理を窒素雰囲気中で実施する。これにより、図４（ｂ）に示したように、表面が窒化されたオーミック電極層１４が形成される。オーミック電極層１４は凹部１６にも形成される。このとき、炭化珪素基板１１とチタンとの界面ではシリサイド反応がおこり、少なくとも界面でＴｉシリサイドが形成される。また窒素雰囲気で熱処理しているので、裏面側の最表層はＴｉＮが形成される。例えば裏面側から見れば、熱処理前がＴｉ／ＳｉＣという構造に対して、熱処理後はＴｉＮ／Ｔｉ／Ｔｉシリサイド／ＳｉＣとなる。膜厚や熱処理温度、時間により、ＴｉＮとＴｉシリサイドの間の未反応層の膜厚は変化し、ＴｉＮ／Ｔｉシリサイド／ＳｉＣとなる場合もある。
　この後、回路素子層１３を有する表面側に上部配線となる金属として、例えばアルミニウムを堆積し、パターニングしてソース電極とゲート電極を形成する。なお、後述の図５（ａ），（ｂ）では、これらの図示を省略している。上部配線がアルミニウムであり、そのパターニングを燐酸系のウェットエッチングで行った場合には、裏面側のオーミック電極層１４はその表面が窒化されたＴｉＮが形成されているため、ほとんどエッチングされない。なお、パターニングをドライエッチングで行う場合には、オーミック電極層１４の腐食防止のため、Ｃｕ、Ａｕ、Ｐｔなどの金属をオーミック電極層１４上に形成しておくことが好ましい。
　次に、図５（ａ）に示すように、オーミック電極層１４上に金属電極層１５を形成する。金属電極層１５もオーミック電極層１４と同様に、凹部１６にも形成される。金属電極層１５の例として、Ｔｉ層、Ｎｉ層、Ａｇ層が用いられるが、金属電極層１５の層構造は、半導体素子１０のパッケージ形態により適宜選択される。他の例としては、Ｔｉ／Ｎｉ／Ａｕ層や、Ｃｒ／ＮｉＣｒ／Ｎｉ／Ａｇ層、もちろんその他の組み合わせでも差し支えない。
　最後に、スクライブライン１３ａに沿って炭化珪素基板１１を半導体素子１０に個片化する。図５（ｂ）の例では、回路素子層１３側にダイシング用フィルム３１を貼り付け、ダイサーを用いて、裏面側からブレード３２を入れて炭化珪素基板１１をダイシングしている。すなわち、凹部１６からブレード３２が入射される。なお、図６に示すように、炭化珪素基板１１の表面側からブレード３２を入射して、個片化してもよい。この場合は、スクライブライン１３ａからブレード３２が入射される。
　ここで、ダイシング用のブレード３２は、その形状が先端に向かって細くなっている。このため、図５（ｂ）のように、炭化珪素基板１１の裏面側からブレード３２を入射した場合には、半導体素子１０の端面が逆べベル形状になるとともに、表面側のチッピングが抑えられる。ここで、逆ベベル形状とは、半導体素子１０の端面が、回路素子層１３が配置された表面（第１の主面）から裏面（第２の主面）にかけて半導体素子１０の幅が狭まるように、傾斜していることを意味している。このため、炭化珪素基板１１の表面側のスクライブライン１３ａを細くすることができる。この結果、表面側の素子面積を大きくできる、あるいは、チップの取れ数を増やせるという効果が得られる。
　以上説明したように本実施形態によると、半導体素子１０の裏面の周辺部に、断面形状が角部２１を有している切り欠き部２０が形成されている。このため、ダイシング工程等の製造工程や素子動作中の発熱による熱応力により、金属電極層１５とオーミック電極層１４との界面において素子端面から金属電極層１５の剥離が生じた場合であっても、切り欠き部２０の角部２１において剥離方向の力のベクトルの向きが変わるため、剥離を止めることができる。したがって、金属電極層１５が全面に渡って剥離してしまうことを抑制することができる。
　なお、本実施形態では、図８（ａ）に示すように、半導体素子１０の炭化珪素基板１１の裏面において、切り欠き部２０は、チップ表面の周辺部全体にわたって形成されているものとした。ただし、これに限られるものではなく、例えば図８（ｂ）に示すように、対向する一組の辺に沿って切り欠き部２０ａ，２０ｂが形成されており、もう一組の辺には切り欠き部が形成されていない構成としてもよい。例えば、半導体素子の個片化工程において、一方向はダイシングを用い、他方向は劈開を用いるというように、個片化手法が方向によって異なる場合がある。そして、劈開のように金属電極層１５の剥離の可能性が低い手法を用いる方向に関しては、切り欠き部を設けないものとする。これにより、製造工程の簡素化が可能となる。
　また、本実施形態では、図８（ａ）に示すように、半導体素子１０の炭化珪素基板１１の裏面において、切り欠き部２０は、チップ表面の周辺部全体にわたって、等しい幅で配置されているものとした。ただし、これに限られるものではない。
　図９（ａ）は本実施形態に係る半導体素子の一変形例の概略構成を示す平面図である。図９（ｂ）は図９（ａ）に示す半導体素子のＡ－Ａ部分の断面図であり、図９（ｃ）は図９（ｂ）に示す半導体素子のＢ－Ｂ部分の断面図である。Ａ－Ａ部分は炭化珪素基板１１の裏面における対角線に相当し、Ｂ－Ｂ部分は炭化珪素基板１１の裏面における対向する一組の辺の中点同士を結ぶ線に相当する。図９では、半導体素子のうち炭化珪素基板１１以外の構成は省略して示している。
　図９（ｂ）及び（ｃ）に示すように、Ａ－Ａ部分における切り欠き部２５の幅は、Ｂ－Ｂ部分における切り欠き部２５の幅よりも大きい。すなわち、炭化珪素基板１１の裏面の対角線を通る断面での切り欠き部２５の幅は、炭化珪素基板１１の裏面における対向する一組の辺の中点同士を結ぶ線を通る断面での切り欠き部２５の幅よりも大きくなるように、切り欠き部２５が配置されていてもよい。このようにすると、金属電極層にかかる応力が大きくなる、半導体素子の裏面の対角線上において、太い幅を有する切り欠き部２５が配置されることになるため、金属電極層の剥離を効果的に抑制することができる。また、半導体素子を半田等の導電性材料で実装する際に、半田の厚みが厚い領域を増やすことができるため、実装時の信頼性を高くすることができる。
　また、半導体素子の炭化珪素基板の裏面において、切り欠き部の内側に、溝部が配置されていてもよい。図１０（ａ）は、本実施形態に係る半導体素子の他の変形例の概略構成を示す平面図であり、図１０（ｂ）は同半導体素子の断面図である。図１１（ａ）は、本実施形態に係る半導体素子の他の変形例の概略構成を示す平面図であり、図１１（ｂ）は同半導体素子のＡ－Ａ部分の断面図であり、図１１（ｃ）は同半導体素子のＢ－Ｂ部分の断面図である。Ａ－Ａ部分は炭化珪素基板１１の裏面における対角線に相当し、Ｂ－Ｂ部分は炭化珪素基板１１の裏面における対向する一組の辺の中点同士を結ぶ線に相当する。図１０及び図１１では、半導体素子のうち炭化珪素基板１１以外の構成は省略して示している。
　図１０に示す例では、半導体素子の裏面において、切り欠き部２０から間隔を空けて、切り欠き部２０の内周に沿って、１本の溝部３００が配置されている。図１１に示す例では、半導体素子の裏面において、隣接する２つの辺に沿って配置された切り欠き部２０をつなぐように、半導体素子の裏面の対角線と直交するように、４本の溝部４００が配置されている。図１０及び図１１に示す例では、金属電極層とオーミック電極層との界面において素子端面から金属電極層の剥離が生じた場合であっても、切り欠き部の角部に加えて、溝部３００、４００の角部においても剥離方向の力のベクトルの向きが変わるため、剥離をさらに抑制することができる。さらに、図１１に示す例では、隣接する２つの辺に沿って配置された切り欠き部２０をつなぐように溝部４００が配置されているため、半導体素子を半田で実装する際に気泡が生じた場合であっても、溝部４００を通して気泡を除去することができる。
　なお、図１０及び図１１に示す例では、溝部３００、４００の底部にサブトレンチがある例について示したが、これに限定されない。溝部の底部にサブトレンチが配置されておらず、溝部の底部が平坦であってもよい。
　（半導体モジュールの例）
　図１２は上述した実施形態に係る半導体素子を用いた半導体モジュールの例の概略構成を示す断面図である。なお、図１２では、半導体素子１０とその周囲の概略について示しており、通常の半導体モジュールで形成される封止樹脂層やケース等は図示を省略している。
　図１２の半導体モジュール１００は、本開示の例示的な実施形態で示した半導体素子１０と、表面に配線層１０２ａ，１０２ｂ，１０２ｃが形成されたモジュール基板１０１とを備えている。配線層１０２ａはワイヤボンディング用のパターン、配線層１０２ｂは素子搭載部、配線層１０２ｃは、モジュール基板１０１とベース基板（図示せず）とを接続するための接続用配線層である。そして、配線層１０２ｂ上に半田や導電性接着剤などにより構成される導電接続層１０３が配置されており、この導電接続層１０３を介して、配線層１０２ｂと半導体素子１０の裏面における金属電極層１５とが接続されている。導電接続層１０３は切り欠き部２０まで入り込んでおり、このため導電接続層１０３の厚さは、半導体素子１０の裏面の中央部よりも切り欠き部２０の位置の方が厚くなっている。また、ワイヤ１０４によって、配線層１０２ａと、半導体素子１０の表面における回路素子層１３上に配置された電極（図示せず）とが接続されている。
　図１２の構成によると、上述した実施形態と同様に、半導体素子１０の裏面における金属電極層１５の剥離が抑制される。また、切り欠き部２０において導電接続層１０３が厚くなっていることによって、半導体モジュール１００の信頼性が向上する。これは、最も熱応力が大きくなるチップ外周部における導電接続層１０３の厚みを厚くすることができることにより、動作時の熱応力に起因した導電接続層１０３におけるクラックの発生を抑制することができるためである。
　以下、半導体モジュール１００の製造方法について、図１３および図１４を用いて説明する。
　まず、図１３（ａ）に示すように、絶縁性のモジュール基板１０１の両面に、例えば銅箔１０２を貼り付ける。モジュール基板１０１に銅箔１０２を貼り付ける方法としては、例えば基板と銅板とを直接接合する直接接合法が挙げられる。モジュール基板１０１の材料としてはアルミナ、窒化アルミニウム、窒化シリコンなどのセラミックス等が選択される。モジュール基板１０１の厚さは、例えば０．５ｍｍである。モジュール基板１０１の材料はモジュールの熱抵抗、耐圧の設計値などにより各種選択される。また、銅箔１０２の素材としては純銅箔などが使用され、例えば０．２ｍｍ厚である。銅箔１０２の厚さは、半導体素子１０に流れる電流の設計値によって決定され、電流量が多くなるほど厚みが大きくなる。
　次に、図１３（ｂ）に示すように、周知のフォトリソグラフィ法およびエッチング法を用いて、所定領域を選択的に除去し、素子搭載部として機能する配線層１０２ｂ、回路（図示せず）、ワイヤボンディング用のパターンとして機能する配線層１０２ａ、ベース基板との接続用配線層として機能する配線層１０２ｃを形成する。なお、図１３（ｂ）には図示していないが、パターニング後にめっきなどにより、銅配線上にＮｉめっきやＮｉ／Ａｕめっきなどを施してもよい。めっき膜を形成することによって、銅表面への酸化膜の形成を抑制することができ、はんだ接合の接合信頼性を向上させることができる。
　次に、図１４（ａ）に示すように、半田などの導電接続層１０３を塗布し、リフローすることで半田バンプを形成する。ここで用いられる半田は、モジュール基板の裏面に配置された配線層１０２ｃをベース基板（ここでは図示しない）に接続する際に熱処理を実施しても接合用の半田が溶けて半導体素子１０が動いてしまわないように、高融点の半田が選択される。例えば、Ａｕ－Ｇｅ半田やＡｕ－Ｓｎ半田などの高融点半田材料が選択される。また、導電接続層１０３の材料として導電性接着剤などが選択された場合には、塗布後にリフローは行わず、塗布後にそのまま図１４（ｂ）に示す半導体素子搭載の工程を行う。
　次に、図１４（ｂ）に示すように、半導体素子１０を導電接続層１０３上に搭載し、リフローを行うことで接合を形成する。このとき、半田は流動性を持つため、半導体素子１０裏面の周辺部に形成した切り欠き部２０にまで半田が入り込み、これにより、半導体素子１０裏面の周辺部の導電接続層１０３の厚みが厚くなる。
　最後に、半導体素子１０表面から、モジュール基板１０１上の配線層１０２ａに向かってワイヤボンディングによりワイヤ１０４を形成する。これにより、図１２に示すような半導体モジュール１００が完成する。
　以上説明した半導体モジュールによると、本開示の例示的な実施形態で説明した金属電極層１５の剥離の進行を止める効果だけでなく、半導体素子１０の裏面周辺部に形成された切り欠き部２０に入り込み厚くなった導電接続層１０３によって、半導体モジュールの信頼性を向上させることができる。
　（半導体パッケージの例）
　図１５は上述した実施形態に係る半導体素子を用いた半導体パッケージの例の概略構成を示す断面図である。ここで示す半導体パッケージ２００は、先に説明した半導体モジュールとほぼ同様の構成となるが、リードフレーム２０１に、導電接続層２０３を介して半導体素子１０が接続されている点が異なる。すなわち、リードフレーム２０１上に、半田や導電性接着剤などにより構成される導電接続層２０３が配置されており、この導電接続層２０３を介して、リードフレーム２０１と半導体素子１０の裏面における金属電極層１５とが接続されている。導電接続層２０３は切り欠き部２０まで入り込んでおり、このため導電接続層２０３の厚さは、半導体素子１０の裏面の中央部よりも切り欠き部２０の位置の方が厚くなっている。また、ワイヤ２０４によって、別のリードフレーム２０５と、半導体素子１０の表面における回路素子層１３とが接続されている。
　図１５の構成によると、上述した実施形態と同様に、半導体素子１０の裏面における金属電極層１５の剥離が抑制される。また、切り欠き部２０において導電接続層２０３が厚くなっていることによって、半導体パッケージ２００の信頼性が向上する。これは、最も熱応力が大きくなるチップ外周部における導電接続層２０３の厚みを厚くすることができることにより、動作時の熱応力に起因した導電接続層２０３におけるクラックの発生を抑制することができるためである。
　以上説明した半導体パッケージによると、本開示の例示的な実施形態で説明した金属電極層１５の剥離の進行を止める効果だけでなく、半導体素子１０の裏面周辺部に形成された切り欠き部２０に入り込み厚くなった導電接続層２０３によって、半導体パッケージの信頼性を向上させることができる。
　本開示は、上述の各実施の形態に限定されるものではなく、当業者の知識に基づいて各種の設計変更等の変形を加えることも可能であり、そのような変形が加えられた実施の形態も本開示の範囲に含まれうるものである。
　本開示は、例えば高い耐圧特性や信頼性が求められる種々の半導体装置に好適に用いられる。特に、縦型のＳｉＣ基板を用いたダイオードやトランジスタなどに好適に用いられる。
１０　半導体素子
１１　炭化珪素基板
１２　エピタキシャル層（炭化珪素層）
１３　回路素子層
１３ａ　スクライブライン
１４　オーミック電極層
１５　金属電極層
１６　凹部
１８　サブトレンチ
２０，２０ａ，２０ｂ，２５　切り欠き部
２１　角部
３１　ダイシング用フィルム
３２　ブレード
１００　半導体モジュール
１０１　モジュール基板
１０２　銅箔
１０２ａ，１０２ｂ，１０２ｃ　配線層
１０３，２０３　導電接続層
１０４，２０４　ワイヤ
１５０　底面
１５２　側面
１６０，１６２　接線
２００　半導体パッケージ
２０１，２０５　リードフレーム
３００，４００　溝部

Claims (13)

  1. 　第１の主面および第２の主面を有する炭化珪素基板と、
    　前記炭化珪素基板の前記第１の主面上に配置された炭化珪素層と、
    　前記炭化珪素基板の前記第２の主面上に配置されたオーミック電極層と、
    　前記オーミック電極層上に配置された金属電極層とを備え、
    　前記炭化珪素基板の前記第２の主面の周辺部において、少なくとも、対向する一組の辺に沿って、切り欠き部が形成されており、
    　前記オーミック電極層および前記金属電極層は、前記第２の主面上から前記切り欠き部表面上にわたって配置されており、
    　前記切り欠き部は、前記辺に直交する断面の形状が、角部を有しており、
    　前記断面において、
    　前記切り欠き部における前記炭化珪素基板の端部での前記炭化珪素基板の厚みは、前記切り欠き部が形成されていない部分における前記炭化珪素基板の厚みよりも小さく、かつ前記角部の底における前記炭化珪素基板の厚みよりも大きい半導体素子。
  2. 　請求項１記載の半導体素子において、
    　前記切り欠き部が有する前記角部がなす角度は、９０度よりも小さい半導体素子。
  3. 　請求項１記載の半導体素子において、
    　前記切り欠き部は、前記炭化珪素基板の前記第２の主面の周辺部全体にわたって、形成されている半導体素子。
  4. 　請求項３記載の半導体素子において、
    　前記炭化珪素基板の前記第２の主面の対角線を通る断面での前記切り欠き部の幅は、前記炭化珪素基板の前記第２の主面における対向する一組の辺の中点同士を結ぶ線を通る断面での前記切り欠き部の幅よりも大きい半導体素子。
  5. 　請求項３記載の半導体素子において、
    　前記炭化珪素基板の前記第２の主面に、溝部がさらに配置されている半導体素子。
  6. 　請求項５記載の半導体素子において、
    　前記溝部は、前記炭化珪素基板の前記第２の主面において、隣接する２つの辺に沿って配置された前記切り欠き部をつなぐ位置に配置されている半導体素子。
  7. 　第１の主面上に炭化珪素層が形成された炭化珪素基板を準備する工程と、
    　前記炭化珪素層上に、スクライブラインが形成された回路素子層を形成する工程と、
    　前記炭化珪素基板の第２の主面のうち、前記スクライブラインに対応する部分に対して、異方性エッチングにより、前記スクライブラインと同一方向に延びる凹部を形成する工程と、
    　前記凹部が形成された前記第２の主面上に、オーミック電極層を形成する工程と、
    　前記オーミック電極層上に金属電極層を形成する工程と、
    　前記スクライブラインに沿って前記炭化珪素基板を半導体素子に個片化する工程とを備え、
    　前記凹部は、両側面と底面とがそれぞれ角部をなすように形成され、
    　前記凹部に、前記角部として、サブトレンチが形成されている、半導体素子の製造方法。
  8. 　請求項７記載の半導体素子の製造方法において、
    　前記個片化する工程において、前記第２の主面からブレードを入れて、ダイシングを行う、半導体素子の製造方法。
  9. 　請求項１から６のうちいずれか１項に記載の半導体素子と、
    　表面に配線層が配置されたモジュール基板と、
    　前記配線層の少なくとも一部上に配置された導電接続層とを備え、
    　前記導電接続層を介して、前記配線層と、前記半導体素子の前記第２の主面上における前記金属電極層とが、接続されている半導体モジュール。
  10. 　請求項９記載の半導体モジュールにおいて、
    　前記導電接続層の厚さは、前記半導体素子の前記第２の主面の中央部よりも、前記切り欠き部の位置の方が厚い半導体モジュール。
  11. 　請求項１から６のうちいずれか１項に記載の半導体素子を準備する工程と、
    　配線層を有するモジュール基板を準備する工程と、
    　前記モジュール基板の前記配線層上に、導電接続層を形成する工程と、
    　前記導電接続層を介して、前記半導体素子の前記第２の主面上における前記金属電極層を、前記モジュール基板の前記配線層に接続する工程とを備える、半導体モジュールの製造方法。
  12. 　請求項１から６のうちいずれか１項に記載の半導体素子と、
    　リードフレームと、
    　前記リードフレームの少なくとも一部上に配置された導電接続層とを備え、
    　前記導電接続層を介して、前記リードフレームと、前記半導体素子の前記第２の主面上における前記金属電極層とが接続されている半導体パッケージ。
  13. 　請求項１２記載の半導体パッケージにおいて、
    　前記導電接続層の厚さは、前記半導体素子の前記第２の主面の中央部よりも、前記切り欠き部の位置の方が厚い半導体パッケージ。
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CN105931989A (zh) * 2015-02-26 2016-09-07 瑞萨电子株式会社 制造半导体器件的方法以及半导体器件
JP2019207984A (ja) * 2018-05-30 2019-12-05 住友電工デバイス・イノベーション株式会社 半導体装置およびその製造方法
JP7095844B2 (ja) 2018-05-30 2022-07-05 住友電工デバイス・イノベーション株式会社 半導体装置およびその製造方法

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