WO2014171056A1 - 薄膜半導体装置、有機el表示装置、及びそれらの製造方法 - Google Patents
薄膜半導体装置、有機el表示装置、及びそれらの製造方法 Download PDFInfo
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- WO2014171056A1 WO2014171056A1 PCT/JP2014/001303 JP2014001303W WO2014171056A1 WO 2014171056 A1 WO2014171056 A1 WO 2014171056A1 JP 2014001303 W JP2014001303 W JP 2014001303W WO 2014171056 A1 WO2014171056 A1 WO 2014171056A1
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- Prior art keywords
- film
- aluminum oxide
- semiconductor device
- protective layer
- thin film
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Definitions
- the technology disclosed herein relates to a thin film semiconductor device including an oxide semiconductor layer, an organic EL (Electro-Luminescence) display device including the thin film semiconductor device, and a method for manufacturing the same.
- Display devices such as liquid crystal display devices or organic EL display devices are widely used.
- a thin film semiconductor device called a thin film transistor (TFT: Thin Film Transistor) is used in an active matrix drive type display device.
- the TFT includes a gate electrode, a source electrode, a drain electrode, a semiconductor layer, a gate insulating film, and the like.
- As the semiconductor layer of the TFT amorphous silicon or the like is used.
- the semiconductor layer has a channel region that is a region in which the movement of carriers is controlled by the voltage of the gate electrode.
- TFTs active matrix drive type display devices are required to have high performance TFTs in order to be used as TFTs that are electrically connected to organic EL elements in response to high definition and high frame rates of screens.
- a TFT using an oxide semiconductor such as zinc oxide (ZnO), indium gallium oxide (InGaO), and indium gallium zinc oxide (also abbreviated as InGaZnO or IGZO) as a TFT semiconductor layer.
- ZnO zinc oxide
- InGaO indium gallium oxide
- IGZO indium gallium zinc oxide
- Non-Patent Document 1 “degradation of the film characteristics of the oxide semiconductor layer” means that the resistance of the oxide semiconductor layer is reduced. As a result, the threshold voltage of the TFT using the oxide semiconductor fluctuates, the oxide semiconductor layer becomes conductive, and further, the reliability deteriorates.
- the term “degradation of reliability” as used herein means that the TFT does not operate as a transistor, and that the threshold voltage shifts and cannot be stably driven as a transistor in the medium to long term. Note that as a state of hydrogen entering the oxide semiconductor layer, a state of gas, atom, radical, or ion can be considered.
- Patent Document 2 As a hydrogen protective film for protecting the oxide semiconductor layer from hydrogen, a method of forming a hydrogen protective film made of aluminum oxide (AlOx) or the like has been proposed (Patent Document 2).
- the “thin film semiconductor device” is a device in which a semiconductor layer is formed by a thin film formation method. Examples of the thin film forming method include a plasma CVD (Chemical Vapor Deposition) method, a sputtering method, and the like.
- the aluminum oxide film is used as a part of an interlayer insulating film of a TFT or a part of a channel protective layer.
- the aluminum oxide film in order to form a wiring in the TFT, it is necessary to process the aluminum oxide film to provide a through hole.
- the better the aluminum oxide film the more difficult it is to perform etching by dry etching or wet etching, and there is a problem that workability is low.
- the present invention has been made in view of such a problem, and an object of the present invention is to provide a thin film semiconductor device with improved workability while suppressing a reduction in resistance of the oxide semiconductor layer due to hydrogen intrusion into the oxide semiconductor layer.
- an aluminum oxide film suitable as a protective film for an oxide semiconductor is clarified.
- the thin film semiconductor device and the thin film semiconductor device having improved workability while suppressing a reduction in resistance of the oxide semiconductor layer due to hydrogen intrusion into the oxide semiconductor layer are provided.
- the object is to provide a method of manufacturing an organic EL display device.
- a thin film semiconductor device includes a substrate, a film containing aluminum oxide, and an oxide semiconductor layer provided between the substrate and the film containing aluminum oxide.
- the film containing aluminum oxide is provided with at least one through-hole embedded with an extraction electrode electrically connected to the oxide semiconductor layer, and the film density of the film containing aluminum oxide is 2.80 g / cm 3 or more 3.25 g / cm 3 or less, and wherein the.
- the film density comprises a film containing 2.80 g / cm 3 or more 3.25 g / cm 3 or less of aluminum oxide.
- Embodiment of this invention 3 is a cross-sectional view schematically showing a lead electrode forming step in the method for manufacturing a thin film semiconductor device according to FIG. It is a figure which shows the relationship between the wet etching rate which normalized the aluminum oxide film, and the film density of an aluminum oxide film. It is a figure which shows the relationship between the sheet resistance value of an oxide semiconductor layer, and the film density of an aluminum oxide film. It is a figure which shows the XRR measurement result and analysis result of aluminum oxide which concern on Embodiment 1 of this invention.
- a thin film semiconductor device includes a film containing aluminum oxide, and an oxide semiconductor layer provided between the substrate and the film containing aluminum oxide, and the film containing the aluminum oxide Includes at least one through hole in which an extraction electrode electrically connected to the oxide semiconductor layer is embedded, and is made of aluminum oxide.
- the film density of the film containing aluminum oxide is 2.80 g / It is characterized by being not less than cm 3 and not more than 3.25 g / cm 3 .
- the film density of the film including the aluminum oxide may be 2.85 g / cm 3 or more 2.95 g / cm 3 or less.
- 1.5 ⁇ x ⁇ 2.0 may be satisfied in aluminum oxide AlOx contained in the film containing aluminum oxide in the thin film semiconductor device.
- the aluminum oxide constituting the film containing aluminum oxide may have an amorphous structure.
- the refractive index of the film containing aluminum oxide may be 1.58 or more and 1.66 or less.
- the film thickness of the film containing aluminum oxide may be 3 nm or more and 30 nm or less.
- the film containing aluminum oxide may have a single layer structure.
- An organic EL display device includes a lower electrode electrically connected to the extraction electrode, a light emitting layer containing an organic light emitting material, and a light emitting layer above the film containing aluminum oxide in the thin film semiconductor device.
- An organic EL element including an upper electrode is provided.
- a method for manufacturing a thin film semiconductor device includes a step of preparing a substrate, a step of forming an oxide semiconductor layer above the substrate, and aluminum oxide above the oxide semiconductor layer.
- a step of forming a film; a step of forming at least one through-hole in the film containing aluminum oxide; and a through-hole provided in the film containing aluminum oxide, electrically connected to the oxide semiconductor layer it is the includes a step of embedding an extraction electrode, a film density of a film containing the aluminum oxide is less than 2.80 g / cm 3 or more 3.25 g / cm 3, it is characterized.
- An organic EL display device manufacturing method includes a step of preparing a substrate, a step of forming an oxide semiconductor layer over the substrate, and aluminum oxide over the oxide semiconductor layer.
- a step of forming a film including the step of forming at least one through-hole in the film including the aluminum oxide, and a through-hole provided in the film including the aluminum oxide and electrically connecting the oxide semiconductor layer.
- FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film semiconductor device 10 according to the first embodiment of the present invention.
- the thin film semiconductor device 10 includes a substrate 1, a gate electrode 2, a gate insulating film 3, an oxide semiconductor layer 4, a channel protective layer 5, a source electrode 6s, a drain electrode 6d, a protective layer 7, and a lead-out. And an electrode 8.
- the thin film semiconductor device 10 is a bottom gate type TFT in which a gate electrode 2 is provided below a channel region.
- the thin film semiconductor device 10 is a channel protection type in which a channel protection layer is formed on a semiconductor layer among bottom gate type TFTs. Since the thin film semiconductor device 10 is a channel protection type, a semiconductor layer including a channel region can be thinly formed. Therefore, in the thin film semiconductor device 10, the parasitic resistance value due to the semiconductor layer can be reduced, and the on-characteristic can be improved.
- the substrate 1 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass.
- a silicon nitride film (SiN x ), silicon oxide (SiO y ) or an undercoat layer made of a silicon oxynitride film (SiO y N x ) or the like may be formed.
- the thickness of the undercoat layer is, for example, about 100 nm to 2000 nm.
- the gate electrode 2 is formed on the substrate 1.
- the gate electrode 2 can have a single layer structure or a multilayer structure using a conductive material and an alloy thereof, for example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium. (Ti), chromium (Cr), molybdenum tungsten (MoW), or the like.
- the gate electrode 2 may be made of a transparent conductive film such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO).
- the film thickness of the gate electrode 2 can be, for example, about 20 nm to 500 nm.
- the gate insulating film 3 is formed on the gate electrode 2.
- the gate insulating film 3 is formed on the entire surface of the substrate 1 so as to cover the gate electrode 2.
- the gate insulating film 3 includes, for example, silicon oxide (SiO y ), silicon nitride (SiN x ), silicon oxynitride film (SiO y N x ), aluminum oxide (AlO z ), tantalum oxide (TaO w ), hafnium oxide ( A single-layer structure using HfO x ) or a laminated structure thereof can be used.
- the gate insulating film 3 can have a two-layer structure of a silicon oxide film and a silicon nitride film, for example.
- the gate insulating film 3 preferably contains silicon oxide. This will be described below. In order to maintain good threshold voltage characteristics in the TFT, it is preferable to make the interface state between the oxide semiconductor layer 4 and the gate insulating film 3 good. Since silicon oxide is an oxide in the same manner as the oxide semiconductor layer 4, the use of a gate insulating film containing silicon oxide can improve the interface state between the oxide semiconductor layer 4 and the gate insulating film 3. it can.
- the film thickness of the gate insulating film 3 can be set to, for example, 50 nm to 300 nm.
- the oxide semiconductor layer 4 is a semiconductor film formed over the gate insulating film 3 and has a channel region.
- the oxide semiconductor layer 4 is made of, for example, an oxide semiconductor containing at least one of indium (In), gallium (Ga), and zinc (Zn). Examples of such an oxide semiconductor include amorphous indium gallium zinc oxide (IGZO, InGaZnO).
- the film thickness of the oxide semiconductor layer 4 can be about 20 nm to 200 nm, for example.
- the channel protective layer 5 is a protective film that protects the channel region of the oxide semiconductor layer 4, and is formed on the entire surface so as to cover the oxide semiconductor layer 4.
- the channel protective layer 5 is a channel etching stopper (CES) layer provided for the purpose of preventing the channel region of the oxide semiconductor layer 4 from being etched during the etching process when forming the source electrode 6s and the drain electrode 6d. Function. If etching damage enters the oxide semiconductor layer, an oxygen deficient layer is formed on the surface of the oxide semiconductor layer. Since the oxygen-deficient layer has a very high carrier concentration, the oxide semiconductor layer with etching damage is made conductive. In such a state, the TFT does not operate as a transistor. Therefore, in a TFT using an oxide semiconductor, it is effective to have a structure in which etching damage does not occur in the channel region of the oxide semiconductor layer.
- CES channel etching stopper
- the channel protective layer 5 for example, a single layer structure using silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride, or a stacked structure thereof is used.
- the film thickness of the channel protective layer 5 can be set to, for example, 50 nm to 500 nm.
- the lower limit of the thickness of the channel protective layer 5 is determined by suppressing the influence of the margin due to channel etching and the fixed charges in the channel protective layer 5.
- the upper limit of the film thickness maintenance of the channel protective layer 5 is decided from suppressing the reliability fall of the manufacturing process accompanying the increase in a level
- the channel protective layer 5 may be an organic material layer mainly containing an organic material containing silicon, oxygen, and carbon.
- Source electrode 6s, drain electrode 6d The source electrode 6s and the drain electrode 6d are formed above the channel region of the oxide semiconductor layer 4 with the channel protective layer 5 interposed therebetween.
- the source electrode 6s and the drain electrode 6d are electrically connected to the oxide semiconductor layer 4 by being opposed to each other with a gap therebetween. That is, when a voltage is applied to the gate electrode 2, carriers move from the source electrode 6 s and the drain electrode 6 d to the oxide semiconductor layer 4.
- the source electrode 6s and the drain electrode 6d each have a single layer structure or a multilayer structure using a conductive material, an alloy, or the like, for example, aluminum, molybdenum, tungsten, copper, titanium, manganese (Mn). And a material such as chromium.
- the source electrode 6s and the drain electrode 6d are formed with a three-layer structure of Mo / Cu / CuMn.
- the film thickness of the source electrode 6s and the drain electrode 6d can be, for example, about 100 nm to 500 nm.
- the protective layer 7 is formed on the source electrode 6s and the drain electrode 6d.
- the protective layer 7 is formed on the entire surface so as to cover the source electrode 6s and the drain electrode 6d.
- the specific structure of the protective layer 7 has a three-layer structure of a first protective layer 7a, a second protective layer 7b, and a third protective layer 7c.
- the first protective layer 7a is preferably a film having good adhesion to the source electrode 6s and the drain electrode 6d and having a low hydrogen content in the film. Therefore, the first protective layer 7a is made of, for example, a silicon oxide film.
- the second protective layer 7b is preferably a film having a barrier property against the penetration of hydrogen into the oxide semiconductor layer 4. Therefore, the second protective layer 7b is constituted by, for example, an aluminum oxide film (a film containing aluminum oxide).
- the third protective layer 7c is preferably a film that has a barrier property such as moisture and can secure processability for forming a through hole for embedding the extraction electrode 8. Therefore, the third protective layer 7c can be constituted by, for example, a single layer structure using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a laminated structure thereof.
- the total film thickness of the protective layer 7 can be, for example, 200 nm to 1000 nm.
- extraction electrode 8 The extraction electrode 8 is embedded in a contact hole provided in the protective layer 7.
- the extraction electrode 8 is electrically connected to the source electrode 6s and the drain electrode 6d when the lower portion 8b contacts the source electrode 6s and the drain electrode 6d.
- the oxide semiconductor layer 4 is electrically connected to the extraction electrode 8.
- the thin film semiconductor device 10 includes an extraction electrode (not shown) that is electrically connected to the gate electrode 2.
- the gate electrode 2 is formed on the substrate 1. Specifically, after preparing a glass substrate as the substrate 1, the gate electrode 2 is formed on the substrate 1. Hereinafter, the step of forming the gate electrode 2 will be described in detail.
- a gate metal film in which a Mo film and a Cu film are sequentially deposited on the substrate 1 is formed by sputtering. Furthermore, the gate electrode 2 can be formed by etching the gate metal film using a wet etching method using a resist formed by a photolithography method as a mask. The wet etching of the Mo film or the Cu film can be performed using, for example, a chemical solution in which a hydrogen peroxide solution (H 2 O 2 ) and an organic acid are mixed.
- H 2 O 2 hydrogen peroxide solution
- an undercoat layer made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like may be formed on the substrate 1 by plasma CVD (Chemical Vapor Deposition) or the like.
- a gate insulating film 3 is formed so as to cover the substrate 1 on which the gate electrode 2 is formed.
- the gate insulating film 3 in which silicon nitride and silicon oxide are sequentially deposited so as to cover the gate electrode 2 is formed by plasma CVD or the like.
- Silicon nitride can be formed, for example, by introducing silane gas (SiH 4 ), ammonia gas (NH 3 ), and nitrogen gas (N 2 ).
- silicon oxide can be formed by introducing silane gas (SiH 4 ) and nitrous oxide gas (N 2 O). (Formation process of oxide semiconductor layer 4 and channel protective layer 5) As shown in FIG.
- the oxide semiconductor layer 4 is formed on the gate insulating film 3.
- the oxide semiconductor layer 4 is composed of, for example, an IGZO film.
- the IGZO film can be formed by a sputtering method or the like.
- the TFT characteristics are improved by heat-treating the amorphous IGZO film at about 200 ° C. to 500 ° C. in the air atmosphere.
- the oxide semiconductor layer 4 can be formed by patterning the amorphous IGZO film using a photolithography method and a wet etching method. The wet etching of the IGZO film can be performed using, for example, a chemical solution in which phosphoric acid (HPO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH) and water are mixed.
- a channel protective layer material 5 ′ is deposited so as to cover the oxide semiconductor layer 4.
- the channel protective layer material 5 ′ is composed of, for example, a silicon oxide film. Specifically, for example, a silicon oxide film is formed by plasma CVD or the like so as to cover the oxide semiconductor layer 4.
- Step of forming source electrode 6s and drain electrode 6d As shown in FIG. 3A, a source electrode 6s and a drain electrode 6d are formed on the channel protective layer 5.
- the channel protective layer material 5 ′ is etched using a dry etching method using a resist formed using a photolithography method as a mask, so that the source region and the drain region on the oxide semiconductor layer 4 are etched. Contact holes are respectively formed on the regions functioning as.
- a reactive ion etching (RIE) apparatus is used for the dry etching of the channel protective layer material 5 ′ formed of the silicon oxide film.
- the etching gas for example, carbon tetrafluoride (CF 4 ) and oxygen gas (O 2 ) are used.
- the apparatus parameters such as gas flow rate, pressure, applied power, and frequency are appropriately set depending on the substrate size, the set etching film thickness, and the like.
- the source electrode 6s and the drain electrode 6d are formed on the channel protective layer 5 in which the contact holes are formed.
- a source / drain metal film in which a Mo film, a Cu film, and a CuMn film are sequentially deposited is formed on the channel protective layer 5 in which the contact holes are formed by a sputtering method.
- the source electrode 6s and the drain electrode 6d can be formed by etching the source / drain metal film using the wet etching method with the resist formed using the photolithography method as a mask.
- the wet etching of the Mo film, the Cu film, and the CuMn film can be performed using, for example, a chemical solution in which a hydrogen peroxide solution (H 2 O 2 ) and an organic acid are mixed.
- a protective layer material 7 ′ is deposited so as to cover the substrate 1 on which the source electrode 6s and the drain electrode 6d are formed.
- a silicon oxide film, an aluminum oxide film, and a silicon nitride film are sequentially deposited.
- the silicon oxide film that is the first protective layer material 7a ′ is formed by, for example, plasma CVD or the like.
- the film thickness of the first protective layer material 7a ′ is, for example, about 50 nm to 500 nm.
- the aluminum oxide that is the second protective layer material 7b ′ is deposited by, for example, a sputtering method.
- a reactive sputtering apparatus is used to form the second protective layer material 7b ′ composed of an aluminum oxide film.
- Aluminum is used for the target, and argon gas (Ar) and O 2 are used for the process gas.
- the apparatus parameters such as the gas flow rate, pressure, applied power, and frequency are appropriately set depending on the substrate size, the set film thickness, and the like.
- Aluminum oxide can also be used as a target. In this case, argon gas is used as the process gas.
- the film thickness of the second protective layer material 7b ′ is, for example, about 2 nm to 50 nm.
- the silicon nitride film that is the third protective layer material 7c ′ is formed by plasma CVD or the like, for example.
- the film thickness of the third protective layer material 7c ′ is, for example, about 50 nm to 700 nm.
- the total film thickness of the protective layer material 7 ′ is preferably about 300 nm to 700 nm in consideration of a step and the like while suppressing a short circuit between the wirings. (Contact hole formation process to protective layer 7) As shown in FIG. 3C, a resist 9 is disposed on the protective layer material 7 '.
- the resist 9 is formed by, for example, laminating a resist material on the protective layer material 7 ′ and then exposing using a photolithography method.
- a resist material a negative resist material, a positive resist material, or the like can be used.
- the resist 9 functions as a mask in dry etching and wet etching performed in the following steps.
- a protective layer 7 provided with contact holes is formed. From the contact hole of the protective layer 7, a part of the source electrode 6s and the drain electrode 6d is exposed. Specifically, first, the third protective layer material 7c ′ is etched using a dry etching method. For example, a reactive ion etching (RIE) apparatus is used for dry etching of the silicon nitride film constituting the third protective layer material 7c ′. As the etching gas, for example, sulfur hexafluoride gas (SF 6 ) and oxygen gas (O 2 ) are used. Next, the second protective layer material 7b ′ is etched using a wet etching method.
- RIE reactive ion etching
- wet etching of the aluminum oxide film constituting the second protective layer material 7b ′ is performed using a chemical solution in which phosphoric acid (HPO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH) and water are mixed. Can do.
- the first protective layer material 7a ′ is etched using a dry etching method.
- a reactive ion etching (RIE) apparatus is used for dry etching of the silicon oxide film constituting the first protective layer material 7a ′.
- RIE reactive ion etching
- As the etching gas for example, carbon tetrafluoride (CF 4 ) and oxygen gas are used.
- the apparatus parameters such as gas flow rate, pressure, applied power, and frequency are appropriately set depending on the substrate size, the set etching film thickness, and the like.
- extraction electrode 8 forming step Finally, as shown in FIG. 4B, the extraction electrode 8 is formed on the protective layer 7. Specifically, a lead metal film in which a Mo film and a Cu film are sequentially deposited is formed on the protective layer 7 in which the contact hole is formed by a sputtering method.
- the extraction electrode 8 can be formed by etching the extraction metal film using a wet etching method using a resist formed by photolithography as a mask.
- the wet etching of the Mo film and the Cu film can be performed using, for example, a chemical solution in which a hydrogen peroxide solution (H 2 O 2 ) and an organic acid are mixed.
- the thin film semiconductor device 10 including the substrate 1, the second protective layer 7b that is a hydrogen protective film, and the oxide semiconductor layer 4 provided between the substrate 1 and the second protective layer 7b. can be manufactured.
- the protective layer 7 has a three-layer structure is shown as the thin film semiconductor device 10
- the number of stacked layers may be changed as long as the second protective layer is included.
- it can also be configured by a two-layer structure of a first protective layer and a second protective layer, a four-layer structure including a second protective layer composed of two layers, or the like.
- an aluminum oxide film is used as the second protective layer 7b.
- the physical properties of an aluminum oxide film for realizing a thin film semiconductor device capable of improving workability while suppressing resistance reduction of the oxide semiconductor layer due to hydrogen intrusion into the oxide semiconductor layer will be described. To do.
- FIG. 5 is a diagram showing the relationship between the normalized wet etching rate of the aluminum oxide film and the film density of the aluminum oxide film.
- each data shown in FIG. 5 is for each of a plurality of samples formed by various film forming methods (RF sputtering method, DC sputtering method, EB vapor deposition method, etc.).
- RF sputtering method DC sputtering method
- EB vapor deposition method etc.
- the film density of the aluminum oxide film is considered to change depending on the film formation conditions.
- the tendency of the change in the film density of the aluminum oxide film depending on the film forming conditions is considered to vary depending on the film forming method.
- the vertical axis in the figure shows the wet etching rate normalized by the wet etching rate of the reference sample, and the horizontal axis shows the film density (Film Density) calculated from the X-ray reflectivity measurement (XRR) results. ing.
- the wet etching rate of the aluminum oxide film depends on the film density. In the range where the film density is 3.55 g / cm 3 or more, the wet etching rate is extremely small. Therefore, a preferable range of the film density of the aluminum oxide film is a range of 3.25 g / cm 3 or less, which is a range of the film density until the wet etching rate rapidly decreases.
- the reason why the vertical axis is normalized by the wet etching rate of the reference sample is that the wet etching rate itself changes depending on the chemical concentration and the type of chemical. It is because it is difficult to make it. If the wet etching rate of the aluminum oxide film depends on the film density, the same effect can be obtained by adopting the film density described with the data by the above method.
- the wet etching rate when the reference sample is etched by the above-described wet etching process is about 1 nm / min to 50 nm / min.
- FIG. 6 is a diagram showing the relationship between the sheet resistance value of the oxide semiconductor layer 4 and the film density of the aluminum oxide film that is the second protective layer 7b.
- an IGZO film is used as the oxide semiconductor layer 4.
- the vertical axis represents the sheet resistance value of the IGZO film
- the horizontal axis represents the film density of the aluminum oxide film.
- the sheet resistance value of the IGZO film is used as an index indicating the hydrogen barrier property of the aluminum oxide film. If the aluminum oxide film has no hydrogen barrier property, the resistance of the IGZO film is reduced as described above. That is, the sheet resistance value of the IGZO film is lowered.
- the sheet resistance value of the IGZO film is measured by, for example, forming a metal electrode pattern on the IGZO film, forming a silicon oxide film and an aluminum oxide film, and then forming a protective film containing hydrogen on the sheet resistance value. Measured and performed. Note that a silicon nitride film formed by a plasma CVD method is used as the protective film containing hydrogen.
- the sheet resistance value of the IGZO film rapidly decreases when the film density of the aluminum oxide film as the second protective layer 7b is 2.80 g / cm 3 or less. That is, it can be seen that the hydrogen barrier property with respect to the IGZO film can be secured in the range where the film density of the aluminum oxide film is 2.80 g / cm 3 or more.
- the range of the film density for securing the workability and hydrogen barrier property of the second protective layer 7b on the aluminum oxide film is 2.80 g / cm 3 or more and 3.25 g / It can be seen that it is cm 3 or less.
- the error of the film density by X-ray reflectivity measurement (XRR) is about 0.01 g / cm 3 . Therefore, the minimum value of the film density in consideration of error is 2.79 g / cm 3 obtained by subtracting the 0.01 g / cm 3 from 2.80 g / cm 3.
- the maximum value of the film density considering the error is 3.26 g / cm 3 obtained by adding 0.01 g / cm 3 to 3.25 g / cm 3 . Thereby, the range of the film density considering the error is 2.79 g / cm 3 or more and 3.26 g / cm 3 or less.
- FIG. 7 is a diagram showing XRR (X-ray reflectivity method) measurement results and analysis results of the aluminum oxide film that is the second protective layer 7b in the thin film semiconductor device 10 manufactured by the above-described manufacturing method.
- the film density of aluminum oxide can be obtained by comparing the XRR measurement result with the simulation result using the film density, film thickness and surface roughness as parameters and optimizing the simulation parameters.
- the film density of the aluminum oxide film can be determined to be 2.856 g / cm 3 . This value is included below 2.80 g / cm 3 or more 3.25 g / cm 3 is preferred the range of film density of the aluminum oxide film. (The optimum range of the film density of the second protective layer 7b)
- the optimum range of the film density of the second protective layer 7b By the way, when the thin film semiconductor device 10 is mass-produced, an error may occur in the film forming conditions in the step of forming the second protective layer 7b. As a result of examining this, it has been found that the magnitude of the change in the film density of the second protective layer 7b with respect to the error in the film forming conditions varies depending on the target value of the film density of the aluminum oxide film as the second protective layer 7b. .
- the optimum range of the film density of the second protective layer 7b in the thin film semiconductor device 10 is defined as “a range in which the magnitude of the change in the film density of the second protective layer 7b is small with respect to an error in the film formation conditions” .
- the optimum range of the film density of the second protective layer 7b will be specifically described in detail.
- FIG. 8 is a diagram showing the variation of the film density of the aluminum oxide film as the second protective layer 7b depending on the number of film formation.
- the vertical axis indicates the film density of the aluminum oxide film
- the horizontal axis indicates the number of times of film formation.
- the plot indicated by the triangle corresponds to the case where the target value of the aluminum oxide film density is 2.75 g / cm 3, and the plot indicated by the square is the target value of 2.90 g / cm 3 of the aluminum oxide film density. Corresponds to the case.
- the target value of the film density of the aluminum film is 2.75 g / cm 3
- the first film formation, the second film formation, the third film formation, the fourth film formation Then, the film densities were 2.73 g / cm 3 , 2.80 g / cm 3 , 2.71 g / cm 3 , and 2.75 g / cm 3 , respectively.
- variation in film density of the aluminum film in the four times of the deposition was 0.09 g / cm 3.
- the target value of the film density of the aluminum film is 2.90 g / cm 3
- the variation in the film density of the aluminum film in the four film formations is from the maximum value 2.90 g / cm 3 to the minimum value 2. pulling the .87g / cm 3, it was 0.03g / cm 3.
- the target value of the film density and 2.90 g / cm 3 compared with the case where the target value of the film density of the aluminum oxide film was 2.75 g / cm 3 also, the film density of the aluminum oxide film, Variations due to the number of depositions are small.
- the optimum range of the film density of the aluminum oxide film will be considered.
- FIG. 9 is a diagram showing the relationship between the film density of the aluminum oxide film according to Embodiment 1 of the present invention and the normalized oxygen flow rate ratio during the formation of the aluminum oxide film.
- the vertical axis indicates the film density of the aluminum oxide film
- the horizontal axis indicates the normalized oxygen flow rate ratio.
- the oxygen flow rate ratio indicates the ratio of the oxygen flow rate to the total gas flow rate (the sum of the argon gas flow rate and the oxygen gas flow rate).
- the normalized oxygen flow ratio on the horizontal axis indicates the ratio of the center condition to the oxygen flow ratio.
- the reason why the standardized oxygen flow ratio is used is to generalize different oxygen flow ratios depending on the film forming method and apparatus conditions.
- the actual oxygen flow ratio is about 5% to 80%.
- the oxygen flow rate ratio affects the film density of the aluminum oxide film.
- the film density of the aluminum oxide film tends to increase.
- Be oxygen flow ratio varies between from 0.85 to 1.16 film density of the aluminum oxide film becomes 2.85 g / cm 3 or more 2.95 g / cm 3 or less.
- FIG. 10 is a diagram showing the relationship between the film density of the aluminum oxide film and the normalized pressure when forming the aluminum oxide film.
- the vertical axis represents the film density of the aluminum oxide film
- the horizontal axis represents the normalized pressure.
- the normalized pressure on the horizontal axis represents the ratio of the center condition to the pressure. Similar to the above-described oxygen flow ratio, the pressure also varies depending on the film forming method and apparatus conditions. Therefore, standardized pressure is used for generalization. The actual pressure is about 0.2 Pa to 2.0 Pa.
- the pressure when forming the aluminum oxide film affects the film density of the aluminum oxide film. Be varied between a pressure of 0.90 to 1.10, the film density of the aluminum oxide film becomes 2.85 g / cm 3 or more 2.95 g / cm 3 or less.
- the optimum range of film density of the aluminum oxide film it is preferable to the range of 2.85 g / cm 3 or more 2.95 g / cm 3.
- the error of the film density by XRR is about 0.01 g / cm 3 . Therefore, the optimum range of the film density is 2.84 g / cm 3 or more and 2.96 g / cm 3 or less in consideration of the maximum error.
- FIG. 11 is a diagram showing the relationship between the refractive index of the aluminum oxide film and the film density of the aluminum oxide film.
- each data shown in the figure is a measured value of the refractive index in the same sample as that shown in FIG.
- the vertical axis in FIG. 11 indicates the refractive index of the aluminum oxide film at a wavelength of 633 nm
- the horizontal axis indicates the film density of the aluminum oxide film.
- FIG. 12 is a diagram showing the relationship between the sheet resistance value of the IGZO film that is the oxide semiconductor layer 4 in the thin film semiconductor device 10 and the film thickness of the aluminum oxide film.
- measurement of the sheet resistance value of the IGZO film is, for example, a sample in which a metal electrode pattern is formed on the IGZO film, a SiO protective film and an aluminum oxide film having a different thickness are formed, and then a protective film containing hydrogen is formed.
- the sheet resistance value was measured.
- shaft in the same figure has shown the sheet resistance value of the IGZO film
- the sheet resistance value of the IGZO film rapidly decreases when the thickness of the aluminum oxide film is less than 3 nm.
- the film thickness of the aluminum oxide film is 3 nm or more, the film resistance dependency of the sheet resistance value of IGZO is almost eliminated, and the barrier property of the IGZO film can be secured.
- the thickness of the aluminum oxide film is preferably 30 nm or less. This is because it is difficult to achieve a desired film density when the aluminum oxide film has a thickness of 30 nm or more. For example, when forming a film by sputtering, the film density increases as the film thickness increases. For this reason, it becomes difficult to realize desired processing performance.
- FIG. 13 is a diagram showing the relationship between the normalized wet etching rate of the aluminum oxide film according to the present embodiment and the film formation conditions of the aluminum oxide film.
- the wet etching rate of the aluminum oxide film is a value normalized with the reference sample, as in FIG.
- the vertical axis in FIG. 13 indicates the normalized wet etching rate of the aluminum oxide film
- the horizontal axis indicates the film forming conditions of the aluminum oxide film.
- “as-depo” indicates a sample which is not annealed immediately after film formation, and 500 ° C., 600 ° C., 700 ° C. and 800 ° C. indicate samples after annealing at respective temperatures. Note that annealing at 500 ° C., 600 ° C., 700 ° C., and 800 ° C. is performed for 20 minutes each.
- the wet etching rate of the aluminum oxide film is 1.0 when not annealed.
- the annealing temperature increases to 500 ° C., 600 ° C., 700 ° C., and 800 ° C.
- the wet etching rate of the aluminum oxide film decreases to 0.5, 0.45, 0.3, and 0.12, respectively.
- the amorphous structure changes to the crystal structure. This will be discussed below.
- FIG. 14 is a diagram showing the X-ray diffraction measurement (XRD) results of the sample after annealing at 800 ° C. shown in FIG. 13 (Comparative Example) and the sample before annealing (Example 1) by a dotted line and a solid line, respectively. It is.
- the vertical axis in FIG. 14 indicates the normalized strength, and the horizontal axis indicates the angle.
- diffraction peaks corresponding to (311), (400), and (440) of aluminum oxide are observed. That is, it can be seen that the annealing process at 800 ° C. causes the aluminum oxide to crystallize.
- Embodiment 1 of the present invention there are no diffraction peaks corresponding to (311), (400), and (440) of aluminum oxide. That is, the aluminum oxide film before annealing has an amorphous structure.
- the amorphous structure here refers to an amorphous structure in which no crystalline diffraction peak is observed in XRD. Even when the annealing temperature is 500 ° C. to 700 ° C., it is considered that at least a part of the aluminum oxide film is crystallized as in the case where the annealing temperature is 800 ° C.
- the aluminum oxide film that is the second protective layer 7b in the thin film semiconductor device 10 preferably has an amorphous structure from the viewpoint of workability.
- the reason why the workability of the amorphous aluminum oxide film is good is considered that the chemical liquid used in wet etching is more likely to enter the amorphous aluminum oxide film than the crystalline aluminum oxide film. (Discussion)
- the range of film density to ensure the workability and hydrogen barrier aluminum oxide film is 2.80 g / cm 3 or more 3.25 g / cm 3 or less.
- the film density of the aluminum oxide film is not more than 2.80 g / cm 3 or more 3.25 g / cm 3, the property may differ aluminum oxide film by a variety of factors. This will be discussed below. (Consideration of refractive index of aluminum oxide film)
- the film density of the aluminum oxide film is simply a physical quantity defined by the mass per unit volume. It does not reflect. Even aluminum oxide films having the same film density are considered to have a crystalline structure and an amorphous structure. It is known that the refractive index of a crystalline aluminum oxide film is different from that of an amorphous aluminum oxide film.
- the workability of the amorphous aluminum oxide film is different from the workability of the crystalline aluminum oxide film. Therefore, even if an aluminum oxide film has the same film density, if the refractive index is different, the crystal structure or the amorphous structure is different, and the workability may be different accordingly.
- an aluminum oxide film having good workability may not be specified only by the film density.
- an aluminum oxide film with good workability can be specified by using the film density and the refractive index in combination.
- composition of aluminum oxide film In order to examine the composition of AlOx contained in the aluminum oxide film according to the first embodiment, spectrum measurement was performed by XPS (X-ray fluorescence analysis) while etching the aluminum oxide film with Ar gas. The film thickness of the aluminum oxide film is 35 nm. As a result of the analysis, spectra of AlOx at depths of 0 nm, 9 nm, 19 nm, and 28.8 nm were obtained.
- FIG. 15 is a graph showing the relationship between the depth in the film thickness direction of AlOx contained in the aluminum oxide film and the composition.
- the horizontal axis of the graph indicates the depth in the film thickness direction
- the vertical axis of the graph indicates the atomic ratio between O and Al.
- the atomic ratios of aluminum at depths of 0 nm, 9 nm, 19 nm, and 28.8 nm are 32.92 atm%, 34.86 atm%, 35.02 atm%, and 35.05 atm%, respectively.
- aluminum takes a ratio of 32.92 atm% or more and 35.05 atm% or less.
- the atomic ratios of oxygen at depths of 0 nm, 9 nm, 19 nm, and 28.8 nm are 58.96 atm%, 64.62 atm%, 64.50 atm%, and 64.81 atm%, respectively. Therefore, it can be said that oxygen takes a ratio of 58.96 atm% or more and 64.81 atm% or less.
- X in AlOx is 1.79 obtained by dividing 58.96 by 32.92, 1.85 obtained by dividing 64.62 by 34.86, and 64.50 divided by 35.02. There is 1.85 obtained by dividing 1.84 and 64.81 obtained by 35.05. These x are all larger than 1.5 and smaller than 2.0. Furthermore, if we look at these x in more detail, it is larger than 1.8 and smaller than 1.9.
- x is larger than 1.5 is considered that the aluminum oxide film according to the first embodiment has an amorphous structure as described above.
- X in AlOx (Al 2 O 3 ) contained in the aluminum oxide film having a crystal structure is 1.5. Since the aluminum oxide film according to Embodiment 1 has an amorphous structure, it is considered that more oxygen atoms that are not bonded to any atom are included than the aluminum oxide film having a crystal structure.
- x is smaller than 2.0 is that it is considered that up to 2.0 can actually exist as x in AlOx contained in the aluminum oxide film.
- the atomic ratio of aluminum and oxygen in the film also changes.
- an aluminum oxide film having a multilayer structure composed of a plurality of layers having different film densities it can be considered that there are places where the atomic ratio of aluminum and oxygen changes greatly when viewed in the film thickness direction.
- the atomic ratio between aluminum and oxygen in the aluminum oxide film of this embodiment is substantially constant when viewed in the film thickness direction. From this, it can be said that the aluminum oxide film has a single layer structure. (Layer structure of aluminum oxide film)
- FIG. 1 Layer structure of aluminum oxide film
- FIG. 16 is a cross-sectional TEM (Transmission Electron Microscope) image of the protective layer having a three-layer structure including the aluminum oxide film according to the first embodiment.
- a silicon oxide film 7a first protective layer
- an aluminum oxide film 7b second protective layer
- a silicon oxide film 7c third protective layer
- This figure is an image of the vicinity of an aluminum oxide film having a thickness of 30 nm.
- the aluminum oxide film 7b appears at a constant density with almost no difference in density at any location.
- the film density of the aluminum oxide film is small, it appears thin in the TEM image, and when the film density of the aluminum oxide film is large, it appears dark in the TEM image.
- the film density in the thickness direction of the aluminum oxide film 7b is constant throughout the film, and the aluminum oxide film 7b has a single layer structure.
- the aluminum oxide film both a single-layer structure composed of only one layer having the same film density and a multilayer structure composed of a plurality of layers having different film densities can be produced.
- the aluminum oxide film constituting the second protective layer 7b has a single layer structure. Therefore, the aluminum oxide film constituting the second protective layer 7b has uniform workability and hydrogen barrier properties in the film thickness direction as compared with the multilayered aluminum oxide film. Therefore, good workability can be secured in the film thickness direction in the aluminum oxide film constituting the second protective layer 7b.
- the wet etching can be performed with the same chemical solution from the surface to the bottom of the aluminum oxide film.
- the aluminum oxide film which comprises the 2nd protective layer 7b favorable hydrogen barrier property can be ensured in the film thickness direction. Therefore, entry of hydrogen into the oxide semiconductor layer can be suppressed.
- the aluminum oxide film has a crystal structure, a pattern appears at the same magnification as that in FIG. However, the pattern does not appear in the aluminum oxide film 7b. Therefore, the aluminum oxide film 7b is considered to have an amorphous structure.
- the thin film semiconductor device according to the first embodiment of the present invention was actually created and its effect was verified. First, the structure of the thin film semiconductor device will be described using the symbols in FIG.
- the substrate 1 was an alkali-free glass substrate.
- the gate electrode 2 is formed above the substrate 1.
- the Mo film functions as an adhesion layer with the substrate 1.
- the film thicknesses of the Cu film and the Mo film were 300 nm and 20 nm, respectively.
- the gate insulating film 3 is formed on the gate electrode 2 and is formed on the entire surface of the substrate 1 so as to cover the gate electrode 2. Since the oxide semiconductor layer 4 is used, a silicon oxide film is used for the gate insulating film 3 in contact with the oxide semiconductor layer 4.
- the oxide semiconductor layer 4 was made of amorphous indium gallium zinc oxide (IGZO).
- IGZO amorphous indium gallium zinc oxide
- the film thickness of the IGZO film was 60 nm.
- the channel protective layer 5 was made of silicon oxide.
- the film thickness of the channel protective layer 5 was 200 nm.
- the source electrode 6s and the drain electrode 6d used a three-layer structure of Mo / Cu / CuMn.
- the protective layer 7 is formed on the source electrode 6s and the drain electrode 6d, and is formed on the entire surface so as to cover the source electrode 6s and the drain electrode 6d.
- the protective layer has a three-layer structure of a first protective layer 7a, a second protective layer 7b, and a third protective layer 7c.
- the first protective layer 7a is composed of a silicon oxide film.
- the second protective layer 7b is composed of an aluminum oxide film.
- As the aluminum oxide film a film having a film density of 2.90 g / cm 3 and a refractive index of 1.60 was used. Film density of the aluminum oxide film, since less 2.80 g / cm 3 or more 3.25 g / cm 3, can provide a thin film semiconductor device 10 having improved processability.
- the film thickness of the aluminum oxide film was 30 nm.
- a silicon nitride film was used for the third protective layer 7c.
- the (total) film thickness of the protective layer 7 can be 600 nm.
- FIG. 17 shows the transfer characteristics of the TFT in the thin film semiconductor device 10 having the above configuration by a solid line.
- a TFT in which an aluminum oxide film is not formed as a protective film is indicated by a dotted line.
- the vertical axis indicates the drain current
- the horizontal axis indicates the gate voltage.
- the drain current is not sufficiently reduced even when the gate voltage is reduced, and deterioration of the on / off characteristics of the transistor is observed.
- the oxide semiconductor layer is considered to be a conductor in the range of the gate voltage measured this time.
- Example 1 an aluminum oxide film is formed as a protective film
- the resistance of the IGZO film which is the oxide semiconductor layer 4 due to the penetration of hydrogen, is suppressed.
- FIG. 18 is a cross-sectional view schematically showing the configuration of the thin film semiconductor device 20.
- the second embodiment is different from the first embodiment in that a protective layer 11b intended for a hydrogen barrier is included in the channel protective layer 11.
- the protective layer 11 b is formed of the same aluminum oxide film as the second protective layer 7 b in the thin film semiconductor device 10.
- symbol is attached
- the thin film semiconductor device 20 includes a channel protective layer 11 and a protective layer 12.
- the thin film semiconductor device 20 is a bottom gate type TFT.
- channel protective layer 11 and the protective layer 12 which are the differences between the thin film semiconductor device 20 and the thin film semiconductor device 10 will be described in detail.
- the channel protective layer 11 is a protective film that protects the channel region of the oxide semiconductor layer 4 and is formed on the entire surface so as to cover the oxide semiconductor layer 4.
- the channel protective layer 11 has a three-layer structure including a first channel protective layer 11a, a second channel protective layer 11b, and a third channel protective layer 11c.
- the first channel protective layer 11a is preferably a film that has good adhesion to the oxide semiconductor layer 4 and does not affect the film quality of the oxide semiconductor layer 4 (low hydrogen content and high oxygen content). Therefore, the first channel protective layer 11a is formed of, for example, a silicon oxide film.
- the second channel protective layer 11b is preferably a film having a hydrogen barrier property to the oxide semiconductor layer 4.
- the second channel protective layer 11b is made of, for example, an aluminum oxide film.
- the aluminum oxide used as the second channel protective layer 11b preferably has the above film density.
- the third channel protective layer 11c is preferably a film having good adhesion with the source electrode 6s and the drain electrode 6d. Therefore, the third channel protective layer 11c can be formed of, for example, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.
- the total film thickness of the channel protective layer 11 can be set to, for example, 50 nm to 300 nm.
- the protective layer 12 is formed on the source electrode 6s and the drain electrode 6d.
- the thin film semiconductor device 20 is formed on the entire surface so as to cover the source electrode 6s and the drain electrode 6d.
- the protective layer 12 is preferably a film having good adhesion to the source electrode 6s and the drain electrode 6d and having a barrier property such as moisture. Therefore, the protective layer 12 can be configured by, for example, a single layer structure using a silicon nitride film, a silicon oxide film, and a silicon oxynitride film, or a stacked structure thereof.
- the total film thickness of the protective layer 12 can be, for example, 200 nm to 1000 nm.
- FIGS. 19A to 21C are cross-sectional views schematically showing the configuration of each process in the method for manufacturing the thin film semiconductor device 20.
- a glass substrate is prepared as the substrate 1 as in FIGS. 2A to 2C, and the gate electrode 2 is formed on the substrate 1.
- a gate insulating film 3 is formed so as to cover the gate electrode 2 (FIG. 19B), and an oxide semiconductor layer 4 such as an IGZO film is formed on the gate insulating film 3. (FIG. 19 (c)).
- a channel protective layer material 11 ′ is formed so as to cover the substrate 1 on which the oxide semiconductor layer 4 is formed.
- the channel protective layer material 11 ′ has a three-layer structure in which a silicon oxide film, an aluminum oxide film, and a silicon oxide film are sequentially deposited.
- the silicon oxide film that is the first channel protective layer material 11a ′ is formed by, for example, plasma CVD or the like.
- the film thickness of the silicon oxide film is, for example, about 50 nm to 200 nm.
- the aluminum oxide film that is the second channel protective layer material 11b ′ is deposited by, for example, a sputtering method. For example, a reactive sputtering apparatus is used for forming the aluminum oxide film.
- the film thickness of the aluminum oxide film is, for example, about 3 nm to 50 nm.
- the silicon oxide film that is the third channel protective layer material 11c ′ is formed by, for example, plasma CVD or the like.
- the film thickness of the silicon oxide film is, for example, about 50 nm to 200 nm.
- the total thickness of the channel protective layer 11 is preferably about 100 nm to 400 nm in consideration of a short circuit between wirings or a step.
- a resist 19 having an opening above the oxide semiconductor layer 4 is laminated on the channel protective layer material 11 ′.
- the resist 19 is formed in the same manner as the resist 9 shown in FIG. 3C in the manufacturing process of the thin film semiconductor device 10.
- a channel protective layer 11 having contact holes provided above the oxide semiconductor layer 4 is formed. Specifically, similarly to the manufacturing process shown in FIG. 4A, each layer of the channel protective layer 11 is etched using a dry etching method or a wet etching method to form a contact hole.
- the source electrode 6s and the drain electrode 6d are formed on the channel protective layer 11 as in FIG. 20C.
- a protective layer material 12 ′ is deposited so as to cover the source electrode 6s and the drain electrode 6d.
- a silicon nitride film is formed by plasma CVD or the like so as to cover the source electrode 6s and the drain electrode 6d.
- the film thickness of the source electrode 6s and the drain electrode 6d is, for example, about 50 nm to 500 nm.
- the extraction electrode 8 is formed on the protective layer 12 as in FIG. 3B.
- the film density is a 2.80 g / cm 3 or more 3.25 g / cm 3 or less is an aluminum oxide film, as the second channel protective layer 11b
- the channel protective layer 11 is included. Therefore, workability can be improved while suppressing the entry of hydrogen into the oxide semiconductor layer 4. Furthermore, in the thin film semiconductor device 20, since an appropriate etching rate can be ensured by using the second channel protective layer 11b, a mass-productive manufacturing method can be realized.
- FIG. 22 is a cross-sectional view schematically showing the configuration of the thin film semiconductor device 30.
- symbol is attached
- the thin film semiconductor device 30 is a channel etching type TFT.
- the channel etching type thin film semiconductor device 30 does not require a channel protective layer, so that the manufacturing process can be simplified.
- FIG. 23 is a cross-sectional view schematically showing the configuration of the thin film semiconductor device 40.
- the same aluminum oxide film as shown in the first embodiment is used as the second protective layer 7 b in the protective layer 7.
- the thin film semiconductor device 40 is different from the thin film semiconductor device 10 of FIG.
- symbol is attached
- the gate electrode 2 is formed on the upper side of the oxide semiconductor layer 44. Thereby, most of the channel region is covered with the gate electrode 2.
- the thin film semiconductor device 40 is a top gate type TFT. Since the thin film semiconductor device 40 has a top gate structure, most of the channel region is covered with the gate electrode 2, so that a change in the resistance value of the oxide semiconductor layer 44 can be suppressed.
- Embodiment 5 a display device according to Embodiment 5 of the present invention will be described.
- the present embodiment is an example in which the thin film semiconductor device 10 according to the first embodiment is applied to a display device.
- an application example to an organic EL display device will be described.
- FIG. 24 is a diagram illustrating the appearance of an organic EL display device 50 using the thin film semiconductor device 10.
- FIG. 25 is a schematic cross-sectional view of the organic EL display device 50.
- the organic EL display device 50 has a plurality of pixels, but only one pixel is shown in FIG.
- the organic EL display device 50 is an active matrix drive type, and the thin film semiconductor device 10 is used as a drive transistor.
- the organic EL display device 50 includes a thin film semiconductor device 10, an insulating layer 51, a lower electrode 52, a partition layer 53, an organic EL layer 54, an upper electrode 55 (transparent electrode), and a passivation layer 56. .
- a contact hole 51a is provided in the insulating layer 51, and the lower part of the lower electrode 52 is buried in the contact hole 51a.
- the lower electrode 52 is electrically connected to the source electrode 6s through the extraction electrode 8.
- the partition layer 53 is provided with an opening 53a, and the organic EL layer 54 is embedded in the opening 53a.
- the organic EL layer 54 includes a light emitting layer containing an organic light emitting material.
- the organic EL layer 54 may further include an electron transport layer, a hole transport layer, and the like.
- the upper electrode 55 is formed over all the pixels so as to cover the organic EL layer 54.
- the passivation layer 56 is formed over all the pixels so as to cover the upper electrode 55.
- Each layer from the insulating layer 51 to the passivation layer 56 is collectively referred to as an organic EL element 57.
- FIG. 2 is a diagram showing a circuit configuration of one pixel of an organic EL display device using the thin film semiconductor device 10 according to the first embodiment.
- the thin film semiconductor device 10 is referred to as a drive transistor 61.
- the anode and cathode of the organic EL element 57 correspond to the lower electrode 52 and the upper electrode 55 in FIG. 25, respectively.
- One pixel includes an organic EL element 57, a drive transistor 61, a switching transistor 62, and a capacitor 63.
- the drive transistor 61 is a transistor that drives the organic EL element 57
- the switching transistor 62 is a transistor for selecting a pixel.
- the gate electrode 61G is connected to the drain electrode 62D of the switching transistor 62, the source electrode 61S is connected to the anode of the organic EL element 57, and the drain electrode 61D is connected to the power supply line 69.
- the gate electrode 62G is connected to the selection line 67
- the source electrode 62S is connected to the signal line 68
- the drain electrode 62D is connected to the capacitor 63 and the gate electrode 61G of the driving transistor 61.
- the video signal voltage supplied via the signal line 68 is applied to the capacitor 63.
- the video signal voltage applied to the capacitor 63 is held throughout one frame period. Due to the held video signal voltage, the conductance of the drive transistor 61 changes in an analog manner, and a drive current corresponding to the video signal voltage flows from the anode to the cathode of the organic EL element 57 and the organic EL element 57 emits light. . Thereby, an image can be displayed on the organic EL display device 50.
- the organic EL display device 50 according to Embodiment 5 has been described above, but the display device is not limited to this.
- the thin film semiconductor device 10 may be used not only as a driving transistor but also as a switching transistor.
- the fifth embodiment can be used as a display device including another display element using an active matrix substrate such as a liquid crystal display element.
- Such a display device can be used for a television set, a personal computer, a mobile phone, or the like.
- the present invention can be applied to any electronic device having a display device.
- ⁇ Modification As described above, the thin film semiconductor device and the manufacturing method thereof according to the present invention have been described based on the embodiments, but the present invention is not limited to the above embodiments.
- a glass substrate is used as the substrate.
- the present invention is not limited to this.
- a plastic substrate or the like may be used.
- a hydrogen protective film may be provided between the substrate and the oxide semiconductor layer.
- a hydrogen protective film is provided between the substrate and the oxide semiconductor layer in order to prevent hydrogen from entering the oxide semiconductor layer. What is necessary is just to provide.
- a thin film semiconductor device In the above embodiments and the like, a thin film transistor has been described as an example of a thin film semiconductor device.
- the present invention is not limited to this, and the thin film semiconductor device of the present invention is a thin film semiconductor device in which an oxide semiconductor layer is provided between a substrate and a film containing aluminum oxide, and a through hole is provided in the film containing aluminum oxide. Good.
- the present invention can be applied to a thin film solar cell in which an oxide semiconductor layer is sandwiched between two electrodes.
- the thin film semiconductor device according to the present invention can be widely used in various electric devices having a display device such as a television set, a personal computer, a mobile phone, or other thin film semiconductor devices.
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Abstract
Description
本発明の一態様に係る薄膜半導体装置は、酸化アルミニウムを含む膜と、前記基板と前記酸化アルミニウムを含む膜との間に設けられた酸化物半導体層と、を備え、前記酸化アルミニウムを含む膜には、前記酸化物半導体層と電気的に接続される引き出し電極が埋め込まれた貫通孔が少なくとも1つ設けられ、酸化アルミニウムで構成され、前記酸化アルミニウムを含む膜の膜密度は2.80g/cm3以上3.25g/cm3以下である、ことを特徴とする。
<<実施の形態1>>
まず、本発明の実施の形態1に係る薄膜半導体装置10及び薄膜半導体装置10の製造方法について、図1~図3を用いて説明する。なお、ここでは、薄膜半導体装置10としてTFTを例に挙げて説明する。
<薄膜半導体装置10の構成>
図1は、本発明の実施の形態1に係る薄膜半導体装置10の構成を模式的に示した断面図である。
以下、本実施の形態に係る薄膜半導体装置10の各構成要素について詳述する。
<薄膜半導体装置10の各構成要素>
(基板1)
基板1は、例えば、石英ガラス、無アルカリガラス、高耐熱性ガラス等のガラス材料で構成されるガラス基板である。なお、ガラス基板の中に含まれるナトリウムやリン等の不純物が酸化物半導体層4に侵入することを防止するために、基板1上にシリコン窒化膜(SiNx)、酸化シリコン(SiOy)又はシリコン酸窒化膜(SiOyNx)等からなるアンダーコート層を形成してもよい。アンダーコート層の膜厚は、例えば、100nm~2000nm程度とする。
(ゲート電極2)
ゲート電極2は、基板1上に形成される。ゲート電極2は、導電性材料及びその合金等を用いた単層構造又は多層構造とすることができ、例えば、モリブデン(Mo)、アルミニウム(Al)、銅(Cu)、タングステン(W)、チタン(Ti)、クロム(Cr)、及びモリブデンタングステン(MoW)等により構成することができる。また、ゲート電極2は、酸化インジウム錫(ITO)、アルミニウムドープ酸化亜鉛(AZO)及びガリウムドープ酸化亜鉛(GZO)等の透明導電膜から構成されてもよい。ゲート電極2の膜厚は、例えば、20nm~500nm程度とすることができる。
(ゲート絶縁膜3)
ゲート絶縁膜3は、ゲート電極2上に形成される。薄膜半導体装置10では、ゲート絶縁膜3は、ゲート電極2を覆うように基板1上の全面に形成される。ゲート絶縁膜3は、例えば、酸化シリコン(SiOy)、窒化シリコン(SiNx)、シリコン酸窒化膜(SiOyNx)、酸化アルミニウム(AlOz)、酸化タンタル(TaOw)、酸化ハフニウム(HfOx)を用いた単層構造又はこれらの積層構造等により構成することができる。積層構造により構成する場合、ゲート絶縁膜3は、例えば、酸化シリコン膜と窒化シリコン膜との二層構造とすることができる。
(酸化物半導体層4)
酸化物半導体層4は、ゲート絶縁膜3上に形成される半導体膜であって、チャネル領域を有する。酸化物半導体層4は、例えば、インジウム(In)、ガリウム(Ga)、及び亜鉛(Zn)のうち少なくとも1種を含む酸化物半導体によって構成される。このような酸化物半導体としては、例えば、アモルファス酸化インジウムガリウム亜鉛(IGZO、InGaZnO)が挙げられる。酸化物半導体層4の膜厚は、例えば、20nm~200nm程度とすることができる。
(チャネル保護層5)
チャネル保護層5は、酸化物半導体層4のチャネル領域を保護する保護膜であって、酸化物半導体層4を覆うように全面に形成される。チャネル保護層5は、ソース電極6s及びドレイン電極6dを形成するときのエッチング処理時に、酸化物半導体層4のチャネル領域がエッチングされることを防止する目的で設けられるチャネルエッチングストッパ(CES)層として機能する。仮に酸化物半導体層にエッチングダメージが入ると、酸化物半導体層の表面に酸素欠損した層が形成される。この酸素欠損した層のキャリア濃度が非常に高いため、エッチングダメージが入った酸化物半導体層は導電化される。このような状態のままでは、TFTはトランジスタとして動作しない。そのため、酸化物半導体を用いたTFTにおいては、酸化物半導体層のチャネル領域にエッチングダメージの入らない構造にすることが有効となる。
(ソース電極6s、ドレイン電極6d)
ソース電極6s及びドレイン電極6dは、それぞれ酸化物半導体層4のチャネル領域の上方にチャネル保護層5を介して形成される。また、ソース電極6s及びドレイン電極6dは、間隔をあけて対向配置されることにより、酸化物半導体層4と電気的に接続されている。すなわち、ゲート電極2に電圧が印加されると、ソース電極6s及びドレイン電極6dから酸化物半導体層4にキャリアが移動する。
(保護層7)
保護層7は、ソース電極6s及びドレイン電極6d上に形成される。薄膜半導体装置10では、保護層7は、ソース電極6s及びドレイン電極6dを覆うように全面に形成される。保護層7の具体的な構成は、第一保護層7a、第二保護層7b、及び第三保護層7cの三層構造としている。第一保護層7aは、ソース電極6s及びドレイン電極6dとの密着性がよく、膜中に水素の含有量が少ない膜が好ましい。そのため、第一保護層7aは、例えば、酸化シリコン膜により構成される。第二保護層7bは、酸化物半導体層4への水素の侵入に対してバリア性を有する膜が好ましい。そのため、第二保護層7bは、例えば、酸化アルミニウム膜(酸化アルミニウムを含む膜)により構成される。第二保護層7bとして用いる酸化アルミニウム膜として、好ましい物性については、後述する。第三保護層7cは、水分等のバリア性を有し、引き出し電極8を埋め込むための貫通孔を形成する加工性を確保できる膜が好ましい。そのため、第三保護層7cは、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜を用いた単層構造又はこれらの積層構造等によって構成することができる。保護層7の合計膜厚は、例えば、200nm~1000nmとすることができる。
(引き出し電極8)
引き出し電極8は、保護層7に設けられたコンタクトホールに埋め込まれている。また、引き出し電極8は、下部8bがソース電極6s及びドレイン電極6dに接触することにより、ソース電極6s及びドレイン電極6dと電気的に接続される。これにより、酸化物半導体層4は、引き出し電極8と電気的に接続されることとなる。なお、図面には現れていないが、薄膜半導体装置10は、ゲート電極2と電気的に接続される引き出し電極(不図示)を備える。
<薄膜半導体装置10の製造方法>
以下、薄膜半導体装置10の製造方法について、図2、図3を用いて説明する。図2(a)~図3(c)は、本発明の実施の形態1に係る薄膜半導体装置10の製造方法における各工程の構成を模式的に示した断面図である。
(基板1、ゲート電極2、及びゲート絶縁膜3の形成工程)
まず、図2(a)に示すように、基板1上にゲート電極2を形成する。具体的には、基板1としてガラス基板を準備した後、基板1上にゲート電極2を形成する。以下、ゲート電極2の形成工程について、詳しく述べる。
(酸化物半導体層4及びチャネル保護層5の形成工程)
図2(c)に示すように、ゲート絶縁膜3上に、酸化物半導体層4を形成する。酸化物半導体層4は、例えば、IGZO膜により構成される。具体的には、IGZO膜は、スパッタリング法等によって成膜することができる。例えば、組成比In:Ga:Zn=1:1:1のターゲット材を用いて、酸素雰囲気でスパッタリングすることによって、アモルファスIGZO膜が成膜される。更に、大気雰囲気で、アモルファスIGZO膜を200℃~500℃程度の熱処理をすることによって、TFT特性が改善する。フォトリソグラフィー法及びウェットエッチング法を用いてアモルファスIGZO膜をパターニングすることにより、酸化物半導体層4を形成することができる。IGZO膜のウェットエッチングは、例えば、リン酸(HPO4)、硝酸(HNO3)、酢酸(CH3COOH)及び水を混合した薬液を用いて行うことができる。
(ソース電極6s及びドレイン電極6dの形成工程)
図3(a)に示すように、チャネル保護層5上に、ソース電極6s及びドレイン電極6dを形成する。
(保護層7の形成工程)
図3(b)に示すように、ソース電極6s及びドレイン電極6dが形成された基板1上を覆って保護層材料7´を堆積する。例えば、保護層材料7´は、酸化シリコン膜、酸化アルミニウム膜、窒化シリコン膜が順に堆積されている。具体的には、第一保護層材料7a´である酸化シリコン膜は、例えば、プラズマCVD等によって成膜する。第一保護層材料7a´の膜厚は、例えば、50nm~500nm程度である。第二保護層材料7b´である酸化アルミニウムは、例えば、スパッタリング法により堆積する。酸化アルミニウム膜により構成される第二保護層材料7b´の成膜には、例えば、反応性スパッタリング装置が用いられる。ターゲットにはアルミニウムが用いられ、プロセスガスにはアルゴンガス(Ar)とO2等が用いられる。ガス流量、圧力、印加電力及び周波数等の装置パラメーターは、基板サイズ、設定膜厚等によって適宜設定される。なお、酸化アルミニウムをターゲットとして用いることもできる。この場合、プロセスガスにはアルゴンガスが用いられる。第二保護層材料7b´の膜厚は、例えば、2nm~50nm程度である。第三保護層材料7c´である窒化シリコン膜は、例えば、プラズマCVD等によって成膜する。第三保護層材料7c´の膜厚は、例えば、50nm~700nm程度である。保護層材料7´の全体膜厚は、配線間におけるショートを抑制し、段差等を考慮して、300nm~700nm程度が好ましい。
(保護層7へのコンタクトホール形成工程)
図3(c)に示すように、保護層材料7´上にレジスト9を配置する。レジスト9におけるソース電極6s及びドレイン電極6dの一部を覆う部分には、開口が設けられている。レジスト9は、例えば、レジスト材料を保護層材料7´上に積層した後、フォトリソグラフィー法を用いて露光することにより形成される。レジスト材料としては、ネガ型レジスト材料やポジ型レジスト材料等を用いることができる。レジスト9は、以下の工程で行うドライエッチング及びウェットエッチングの際のマスクとして機能する。
(引き出し電極8形成工程)
最後に、図4(b)に示すように、保護層7上に、引き出し電極8を形成する。具体的には、コンタクトホールの形成された保護層7上に、Mo膜、Cu膜が順に堆積された引き出し金属膜をスパッタリング法によって成膜する。フォトリソグラフィー法を用いて形成したレジストをマスクとして、ウェットエッチング法を用いて引き出し金属膜をエッチングすることにより、引き出し電極8を形成することができる。Mo膜、Cu膜のウェットエッチングは、例えば、過酸化水素水(H2O2)、及び有機酸を混合した薬液を用いて行うことができる。
<薄膜半導体装置10の第二保護層7bの詳細構成>
以下、薄膜半導体装置10の第二保護層7bの構成について、図5~図16を用いて説明する。
(第二保護層7bの膜密度の好適範囲)
まず、薄膜半導体装置10における第二保護層7bの膜密度の好適範囲について検討する。
(第二保護層7bの膜密度の測定)
図7は、上述した製造方法で製造した薄膜半導体装置10における、第二保護層7bである酸化アルミニウム膜のXRR(X線反射率法)測定結果及び解析結果を示す図である。XRR測定結果と、膜密度、膜厚及び表面ラフネスをパラメーターとしたシミュレーション結果とを比較し、シミュレーションパラメーターを最適化することで、酸化アルミニウムの膜密度を求めることができる。
(第二保護層7bの膜密度の最適範囲)
ところで、薄膜半導体装置10を量産する場合、第二保護層7bを形成する工程で、成膜条件に誤差が出てしまう場合がある。これについて検討した結果、成膜条件の誤差に対する、第二保護層7bの膜密度の変化の大きさは、第二保護層7bである酸化アルミニウム膜の膜密度の目標値により異なることが分かった。これにより、薄膜半導体装置10における第二保護層7bの膜密度の最適範囲を、「成膜条件の誤差に対する、第二保護層7bの膜密度の変化の大きさが小さくなる範囲」として定めた。以下、具体的に第二保護層7bの膜密度の最適範囲について詳述する。
(酸化アルミニウム膜の屈折率)
図11は、酸化アルミニウム膜の屈折率と、酸化アルミニウム膜の膜密度との関係を示す図である。ここで、同図に示す各データは、図5で示されたものと同じサンプルにおける屈折率の測定値である。また、図11における縦軸は波長633nmにおける酸化アルミニウム膜の屈折率を示しており、横軸は酸化アルミニウム膜の膜密度を示している。
(酸化アルミニウム膜の膜厚)
図12は、薄膜半導体装置10における酸化物半導体層4であるIGZO膜のシート抵抗値と、酸化アルミニウム膜の膜厚との関係を示す図である。ここで、IGZO膜のシート抵抗値測定は、例えば、IGZO膜上に金属電極パターンを形成し、更にSiO保護膜及び異なる厚みの酸化アルミニウム膜を形成後、水素を含む保護膜を成膜したサンプルの、シート抵抗値を測定することで行った。また、同図における縦軸はIGZO膜のシート抵抗値を示しており、横軸は酸化アルミニウム膜の膜厚を示している。
(酸化アルミニウム膜の構造)
図13は、本実施の形態に係る酸化アルミニウム膜の規格化したウェットエッチングレートと、酸化アルミニウム膜の成膜条件との関係を示す図である。ここで、酸化アルミニウム膜のウェットエッチングレートは、図5と同様に、基準サンプルで規格化した値である。また、図13における縦軸は酸化アルミニウム膜の規格化ウェットエッチングレートを示しており、横軸は酸化アルミニウム膜の成膜条件を示している。as-depoは、成膜直後でアニールしていないサンプルを示し、500℃、600℃、700℃、800℃は、それぞれの温度でアニールした後のサンプルを示す。なお、500℃、600℃、700℃、800℃のアニールは、アニール処理をそれぞれ20分間ずつ行なっている。
(考察)
上述のように、酸化アルミニウム膜に加工性及び水素バリア性を確保するための膜密度の範囲は、2.80g/cm3以上3.25g/cm3以下である。一方、酸化アルミニウム膜の膜密度が2.80g/cm3以上3.25g/cm3以下であっても、種々の要素により酸化アルミニウム膜の性質が異なる可能性がある。以下、これについて考察する。
(酸化アルミニウム膜の屈折率についての考察)
酸化アルミニウム膜の膜密度は、単に単位体積当たりの質量で定義される物理量なので、AlOxの原子の緻密性や組成比xを反映しているとは言えるものの、原則、結晶構造かアモルファス構造かを反映するものではない。同じ膜密度の酸化アルミニウム膜であっても、結晶構造のものと、アモルファス構造のものとがあると考えられる。そして、結晶構造の酸化アルミニウム膜の屈折率と、アモルファス構造の酸化アルミニウム膜の屈折率とは異なることが知られている。また、X線回折測定の説明でも上述したように、アモルファス構造の酸化アルミニウム膜の加工性は、結晶構造の酸化アルミニウム膜の加工性と異なるという結果が得られている。従って、同じ膜密度の酸化アルミニウム膜であっても屈折率が異なれば、結晶構造であるかアモルファス構造であるかが異なり、それに伴い加工性が異なる可能性がある。
(酸化アルミニウム膜の組成)
本実施の形態1に係る酸化アルミニウム膜に含まれるAlOxの組成について検討するために、酸化アルミニウム膜をArガスでエッチングしつつ、XPS(X線蛍光分析法)でスペクトル測定を行った。なお、酸化アルミニウム膜の膜厚は35nmである。当該解析の結果、深さ0nm、9nm、19nm、28.8nmでのAlOxのスペクトルを得た。各スペクトルから半定量解析を行うことで、OとAlとの相対強度を得て、酸化アルミニウム膜に含まれるOの原子数比と、酸化アルミニウム膜に含まれるAlの原子数比とを求めた。図15は、当該酸化アルミニウム膜に含まれるAlOxの膜厚方向の深さと組成との関係を示すグラフである。グラフの横軸が膜厚方向の深さを示し、グラフの縦軸がOとAlとの原子数比を示す。深さ0nm、9nm、19nm、28.8nmでのアルミニウムの原子数比は、それぞれ32.92atm%、34.86atm%、35.02atm%、35.05atm%である。そのため、アルミニウムは、32.92atm%以上35.05atm%以下の比率を取るといえる。また、深さ0nm、9nm、19nm、28.8nmでの酸素の原子数比は、それぞれ58.96atm%、64.62atm%、64.50atm%、64.81atm%である。そのため、酸素は58.96atm%以上64.81atm%以下の比率を取るといえる。
(酸化アルミニウム膜の層構造)
図16は、本実施の形態1に係る酸化アルミニウム膜を含む三層構造の保護層の断面TEM(Transmission Electron Microscope)画像である。同図には、酸化シリコン膜7a(第1保護層)と、酸化アルミニウム膜7b(第2保護層)と、酸化シリコン膜7c(第3保護層)と、が現れている。なお、同図は、厚さ30nmの酸化アルミニウム膜の近傍を撮像したものである。酸化アルミニウム膜7bは、厚み方向に視ると、どの箇所においても濃淡の差がほぼ無く一定の濃さで現れている。一般的に、酸化アルミニウム膜の膜密度が小さいとTEM画像では薄く現れ、酸化アルミニウム膜の膜密度が大きいとTEM画像では濃く現れる。そのため、酸化アルミニウム膜7bの厚み方向の膜密度は膜全体で一定であり、酸化アルミニウム膜7bは単層構造である。ところで、酸化アルミニウム膜には、膜密度が等しい一層のみからなる単層構造のものと、膜密度が異なる複数の層からなる多層構造のどちらも作製可能である。第二保護層7bを構成する酸化アルミニウム膜は、単層構造である。そのため、第二保護層7bを構成する酸化アルミニウム膜は、多層構造の酸化アルミニウム膜と比べて、膜厚方向における加工性や水素バリア性が均一である。従って、第二保護層7bを構成する酸化アルミニウム膜では、膜厚方向において良好な加工性を確保できる。そのため、当該酸化アルミニウム膜に貫通孔を設けるためにウェットエッチングを行う際、当該酸化アルミニウム膜の表面から底面まで同一の薬液でウェットエッチングを行うことができる。また、第二保護層7bを構成する酸化アルミニウム膜では、膜厚方向において良好な水素バリア性を確保できる。そのため、酸化物半導体層に水素が入り込むことを抑制できる。
<薄膜半導体装置の実証>
本発明の実施の形態1に係る薄膜半導体装置を実際に作成し、その効果について実証した。まず、図1の記号を用いて、薄膜半導体装置の構成について説明する。
<<実施の形態2>>
次に、本発明の実施の形態2に係る薄膜半導体装置20及び薄膜半導体装置20の製造方法について説明する。
<薄膜半導体装置20の構成>
図18は、薄膜半導体装置20の構成を模式的に示した断面図である。実施の形態2は、実施の形態1に対して、水素のバリアを目的とした保護層11bがチャネル保護層11の中に含まれている点が異なる。また、保護層11bは、薄膜半導体装置10における第二保護層7bと同じ酸化アルミニウム膜で構成される。なお、同図において、図1に示す構成要素と同じ構成要素については同じ符号を付している。
<薄膜半導体装置20の製造方法>
次に、本発明の実施の形態2に係る薄膜半導体装置20の製造方法について、図19(a)~図21(c)を用いて説明する。図19(a)~図21(c)は、薄膜半導体装置20の製造方法における各工程の構成を模式的に示した断面図である。
<効果>
薄膜半導体装置20は、薄膜半導体装置10における第二保護層7bと同じく、膜密度が2.80g/cm3以上3.25g/cm3以下である酸化アルミニウム膜を、第二チャネル保護層11bとしてチャネル保護層11に含んだ構成である。そのため、酸化物半導体層4への水素の侵入を抑制しつつ、加工性を向上させることができる。更に、薄膜半導体装置20では、第二チャネル保護層11bを用いることで、適切なエッチングレートを確保することができるため、量産性のある製造方法を実現することができる。
<<実施の形態3>>
次に、本発明の実施の形態3に係る薄膜半導体装置30について説明する。
<薄膜半導体装置30の構成>
実施の形態3は、保護層7における第二保護層7bとして実施の形態1で示したものと同じ酸化アルミニウム膜を用いている。一方、薄膜半導体装置30は、図1の薄膜半導体装置10に対して、チャネルエッチング型TFTである点が異なる。図22は、薄膜半導体装置30の構成を模式的に示した断面図である。なお、同図において、図1に示す構成要素と同じ構成要素については同じ符号を付している。
<<実施の形態4>>
本発明の実施の形態4に係る薄膜半導体装置40の構成について説明する。
<薄膜半導体装置40の構成>
図23は、薄膜半導体装置40の構成を模式的に示した断面図である。実施の形態4は、保護層7における第二保護層7bとして、実施の形態1で示したものと同じ酸化アルミニウム膜を用いている。一方、薄膜半導体装置40は、図1の薄膜半導体装置10に対して、トップゲート型TFTである点が異なる。なお、同図において、図1に示す構成要素と同じ構成要素については同じ符号を付している。
<<実施の形態5>>
次に、本発明の実施の形態5に係る表示装置について説明する。本実施の形態は、上記の実施の形態1に係る薄膜半導体装置10を表示装置に適用した例である。なお、本実施の形態では、有機EL表示装置への適用例について説明する。
<<変形例>>
以上、本発明に係る薄膜半導体装置及びその製造方法等について、実施の形態に基づいて説明したが、本発明は、上記の実施の形態に限定されるものではない。例えば、各実施の形態に対して当業者が思いつく各種変形を施して得られる形態や、本発明の趣旨を逸脱しない範囲で各実施の形態における構成要素及び機能を任意に組み合わせることで実現される形態も本発明に含まれる。
<基板>
上記実施の形態等では、基板としてガラス基板を用いた。しかしながら、これに限らず、例えば、プラスティック基板等を用いてもよい。また、基板が水素を通す材料で構成される場合には、基板と酸化物半導体層との間に水素保護膜を設ければよい。
<薄膜半導体装置>
上記実施の形態等では、薄膜半導体装置の例として、薄膜トランジスタを挙げて説明した。しかしながら、これに限らず、本発明の薄膜半導体装置は、基板と酸化アルミニウムを含む膜との間に酸化半導体層が設けられ、酸化アルミニウムを含む膜に貫通孔が設けられる薄膜半導体装置であればよい。例えば、2つの電極に酸化物半導体層が挟まれた薄膜太陽電池等にも、本発明を利用することができる。
2 ゲート電極
3 ゲート絶縁膜
4 酸化物半導体層
5、11 チャネル保護層
6s ソース電極
6d ドレイン電極
7、12 保護層
7a 第一保護層
7b 第二保護層
7c 第三保護層
8 引き出し電極
10、20、30、40 薄膜半導体装置
11a 第一チャネル保護層
11b 第二チャネル保護層
11c 第三チャネル保護層
50 有機EL表示装置
51 絶縁層
52 下部電極
53 隔壁層
54 有機EL層
55 上部電極
56 パッシベーション層
61 駆動トランジスタ
62 スイッチングトランジスタ
64 コンデンサ
67 信号線
68 選択線
69 電源線
Claims (11)
- 基板と、
酸化アルミニウムを含む膜と、
前記基板と前記酸化アルミニウムを含む膜との間に設けられた酸化物半導体層と、
を備え、
前記酸化アルミニウムを含む膜には、前記酸化物半導体層と電気的に接続される引き出し電極が埋め込まれた貫通孔が少なくとも1つ設けられ、
前記酸化アルミニウムを含む膜の膜密度は2.80g/cm3以上3.25g/cm3以下である、
薄膜半導体装置。 - 前記酸化アルミニウムを含む膜の膜密度は2.85g/cm3以上2.95g/cm3以下である、
請求項1に記載の薄膜半導体装置。 - 前記酸化アルミニウムを含む膜に含まれる酸化アルミニウムAlOxにおいて、
1.5<x<2.0である、
請求項1に記載の薄膜半導体装置。 - 前記酸化アルミニウムを含む膜に含まれる酸化アルミニウムAlOxにおいて、
1.79≦x≦1.85である、
請求項3に記載の薄膜半導体装置。 - 前記酸化アルミニウムを含む膜を構成する酸化アルミニウムは、アモルファス構造である、
請求項1に記載の薄膜半導体装置。 - 前記酸化アルミニウムを含む膜の屈折率は、1.58以上1.66以下である、
請求項1に記載の薄膜半導体装置。 - 前記酸化アルミニウムを含む膜の膜厚は、3nm以上30nm以下である、
請求項1に記載の薄膜半導体装置。 - 前記酸化アルミニウムを含む膜は、単層構造である、
請求項1に記載の薄膜半導体装置。 - 請求項1に記載の薄膜半導体装置における前記酸化アルミニウムを含む膜の上方に、前記引き出し電極と電気的に接続された下部電極、有機発光材料を含む発光層、及び上部電極を含む有機EL素子が設けられている、
有機EL表示装置。 - 基板を準備する工程と、
前記基板の上方に酸化物半導体層を形成する工程と、
前記酸化物半導体層の上方に、酸化アルミニウムを含む膜を形成する工程と、
前記酸化アルミニウムを含む膜に、少なくとも1つの貫通孔を形成する工程と、
前記酸化アルミニウムを含む膜に設けられた貫通孔に、前記酸化物半導体層と電気的に接続される引き出し電極を埋め込む工程と、
を含み、
前記酸化アルミニウムを含む膜の膜密度は2.80g/cm3以上3.25g/cm3以下である、
薄膜半導体装置の製造方法。 - 基板を準備する工程と、
前記基板の上方に酸化物半導体層を形成する工程と、
前記酸化物半導体層の上方に、酸化アルミニウムを含む膜を形成する工程と、
前記酸化アルミニウムを含む膜に、少なくとも1つの貫通孔ホールを形成する工程と、
前記酸化アルミニウムを含む膜に設けられた貫通孔に、前記酸化物半導体層と電気的に接続される引き出し電極を埋め込む工程と、
前記酸化アルミニウムを含む膜の上方に、前記引き出し電極と電気的に接続された下部電極、有機発光材料を含む発光層、及び上部電極を含む有機EL素子を形成する工程と、
を含み、
前記酸化アルミニウムを含む膜の膜密度は2.80g/cm3以上3.25g/cm3以下である、
有機EL表示装置の製造方法。
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Also Published As
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US9431468B2 (en) | 2016-08-30 |
JP6142331B2 (ja) | 2017-06-07 |
JPWO2014171056A1 (ja) | 2017-02-16 |
US20150194475A1 (en) | 2015-07-09 |
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