JP6331052B2 - 薄膜トランジスタ、薄膜トランジスタの製造方法及び有機el表示装置 - Google Patents
薄膜トランジスタ、薄膜トランジスタの製造方法及び有機el表示装置 Download PDFInfo
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- JP6331052B2 JP6331052B2 JP2016529053A JP2016529053A JP6331052B2 JP 6331052 B2 JP6331052 B2 JP 6331052B2 JP 2016529053 A JP2016529053 A JP 2016529053A JP 2016529053 A JP2016529053 A JP 2016529053A JP 6331052 B2 JP6331052 B2 JP 6331052B2
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- oxide semiconductor
- semiconductor layer
- thin film
- film transistor
- fluorine
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H01L21/02612—Formation types
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- Condensed Matter Physics & Semiconductors (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
以下、本発明の一実施の形態について、図面を用いて説明する。なお、以下に説明する実施の形態は、いずれも本発明の好ましい一具体例を示すものである。したがって、以下の実施の形態で示される、数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、工程(ステップ)、工程の順序等は、一例であって本発明を限定する主旨ではない。よって、以下の実施の形態における構成要素のうち、本発明の最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。
まず、本発明の実施の形態に係る薄膜トランジスタ1について、図1を用いて説明する。図1は、本発明の実施の形態に係る薄膜トランジスタの構成を示す断面図である。なお、図1には2つの薄膜トランジスタ1が図示されており、2つの薄膜トランジスタ1は同じ構造である。
次に、本実施の形態に係る薄膜トランジスタ1の製造方法について、図2A〜図2Gを用いて説明する。図2A〜図2Gは、本発明の実施の形態に係る薄膜トランジスタの製造方法における各工程の断面図である。
次に、本実施の形態に係る薄膜トランジスタ1の作用効果について、本発明に至った経緯も含めて説明する。
次に、上記の実施の形態に係る薄膜トランジスタ1を表示装置に適用した例について、図9及び図10を用いて説明する。なお、本実施の形態では、有機EL表示装置への適用例について説明する。
以上、薄膜トランジスタ及びその製造方法について、実施の形態に基づいて説明したが、本発明は、上記実施の形態に限定されるものではない。
10 基板
20 アンダーコート層
30、G1、G2 ゲート電極
40 ゲート絶縁層
50 酸化物半導体層
51 第1領域
52 第2領域
50S、S1、S2 ソース領域
50D、D1、D2 ドレイン領域
60 保護層
70S ソース電極
70D ドレイン電極
100 有機EL表示装置
110 TFT基板
120 画素
130 有機EL素子
131 陽極
132 EL層
133 陰極
140 ゲート配線
150 ソース配線
160 電源配線
SwTr スイッチングトランジスタ
DrTr 駆動トランジスタ
C キャパシタ
Claims (20)
- ゲート電極と、
ソース電極及びドレイン電極と、
チャネル層として用いられる酸化物半導体層と、
前記ゲート電極と前記酸化物半導体層との間に配置されたゲート絶縁層とを備え、
前記酸化物半導体層を構成する金属元素には少なくともインジウム及び亜鉛が含まれており、
前記酸化物半導体層の内部領域であって前記ゲート絶縁層と近接する領域にはフッ素が含有されており、
前記酸化物半導体層のフッ素含有濃度は、1×10 22 atm/cm 3 以上である
薄膜トランジスタ。 - 前記酸化物半導体層におけるフッ素が含有されている領域の膜厚は、少なくとも5nm以上である
請求項1に記載の薄膜トランジスタ。 - 前記酸化物半導体層におけるフッ素が含有されている領域の膜厚は、少なくとも20nm以上である
請求項1に記載の薄膜トランジスタ。 - 前記酸化物半導体層のフッ素含有濃度は、少なくとも前記酸化物半導体層の水素含有濃度よりも高い
請求項1〜3のいずれか1項に記載の薄膜トランジスタ。 - 前記酸化物半導体層を構成する金属元素には、さらに、ガリウム及び亜鉛の少なくとも一方又は両方が含まれている
請求項1〜4のいずれか1項に記載の薄膜トランジスタ。 - 前記ゲート電極、前記ゲート絶縁層及び前記酸化物半導体層は、この順で基板上に積層されており、
前記ソース電極及び前記ドレイン電極は、前記酸化物半導体層の上方に形成されている
請求項1〜5のいずれか1項に記載の薄膜トランジスタ。 - さらに、前記酸化物半導体層上に形成されたチャネル保護層を備える
請求項6に記載の薄膜トランジスタ。 - 前記酸化物半導体層、前記ゲート絶縁層及び前記ゲート電極は、この順で基板上に積層されており、
前記ソース電極は、前記ゲート絶縁層に形成されたコンタクトホールを介して前記酸化物半導体層のソース領域に接続されており、
前記ドレイン電極は、前記ゲート絶縁層に形成されたコンタクトホールを介して前記酸化物半導体層のドレイン領域に接続されている
請求項1〜5のいずれか1項に記載の薄膜トランジスタ。 - ゲート電極を形成する工程と、
ソース電極及びドレイン電極を形成する工程と、
チャネル層として用いられる酸化物半導体層を形成する工程と、
前記ゲート電極と前記酸化物半導体層との間に位置するようにゲート絶縁層を形成する工程とを含み、
前記酸化物半導体層を構成する金属元素には少なくともインジウム及び亜鉛が含まれており、
前記酸化物半導体層を形成する工程では、フッ素を導入しながら前記酸化物半導体層を形成し、
前記酸化物半導体層のフッ素含有濃度は、1×10 22 atm/cm 3 以上である
薄膜トランジスタの製造方法。 - 前記酸化物半導体層を形成する工程では、前記フッ素が前記酸化物半導体層の内部領域であって前記ゲート絶縁層と近接する領域に含有するように、前記酸化物半導体層を形成する
請求項9に記載の薄膜トランジスタの製造方法。 - ゲート電極を形成する工程と、
ソース電極及びドレイン電極を形成する工程と、
チャネル層として用いられる酸化物半導体層を形成する工程と、
前記ゲート電極と前記酸化物半導体層との間に位置するようにゲート絶縁層を形成する工程とを含み、
前記酸化物半導体層を構成する金属元素には少なくともインジウムが含まれており、
前記酸化物半導体層を形成する工程では、フッ素を含むターゲット材を用いたスパッタによって前記酸化物半導体層を形成する
薄膜トランジスタの製造方法。 - 前記酸化物半導体層を形成する工程では、フッ素を含むガスを用いて前記酸化物半導体層を形成する
請求項9又は10に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層におけるフッ素が含有されている領域の膜厚は、少なくとも5nm以上である
請求項9〜12のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層におけるフッ素が含有されている領域の膜厚は、少なくとも20nm以上である
請求項9〜12のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層のフッ素含有濃度は、少なくとも前記酸化物半導体層の水素含有濃度よりも高い
請求項10〜14のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層を構成する金属元素には、さらに、ガリウム及び亜鉛の少なくとも一方又は両方が含まれている
請求項10〜15のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記ゲート電極を形成する工程と、前記ゲート絶縁層を形成する工程と、前記酸化物半導体層を形成する工程と、前記ソース電極及び前記ドレイン電極を形成する工程とは、この順で行われる
請求項9〜16のいずれか1項に記載の薄膜トランジスタの製造方法。 - さらに、前記酸化物半導体層上にチャネル保護層を形成する工程を含む
請求項16に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層を形成する工程と、前記ゲート絶縁層を形成する工程と、前記ゲート電極を形成する工程と、前記ソース電極及び前記ドレイン電極を形成する工程とは、この順で行われる
請求項9〜16のいずれか1項に記載の薄膜トランジスタの製造方法。 - 請求項1〜8のいずれか1項に記載の薄膜トランジスタを備える有機EL表示装置であって、
マトリクス状に配置された複数の画素と、
前記複数の画素の各々に対応して形成された有機EL素子とを備え、
前記薄膜トランジスタは、前記有機EL素子を駆動する駆動トランジスタである
有機EL表示装置。
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