JP6263721B2 - 薄膜トランジスタ、薄膜トランジスタの製造方法及び有機el表示装置 - Google Patents
薄膜トランジスタ、薄膜トランジスタの製造方法及び有機el表示装置 Download PDFInfo
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- JP6263721B2 JP6263721B2 JP2016529054A JP2016529054A JP6263721B2 JP 6263721 B2 JP6263721 B2 JP 6263721B2 JP 2016529054 A JP2016529054 A JP 2016529054A JP 2016529054 A JP2016529054 A JP 2016529054A JP 6263721 B2 JP6263721 B2 JP 6263721B2
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- oxide semiconductor
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- fluorine
- thin film
- film transistor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Description
以下、本発明の一実施の形態について、図面を用いて説明する。なお、以下に説明する実施の形態は、いずれも本発明の好ましい一具体例を示すものである。したがって、以下の実施の形態で示される、数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、工程(ステップ)、工程の順序等は、一例であって本発明を限定する主旨ではない。よって、以下の実施の形態における構成要素のうち、本発明の最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。
まず、本発明の実施の形態に係る薄膜トランジスタ1について、図1を用いて説明する。図1は、本発明の実施の形態に係る薄膜トランジスタの構成を示す断面図である。なお、図1には2つの薄膜トランジスタ1が図示されており、2つの薄膜トランジスタ1は同じ構造である。
次に、本実施の形態に係る薄膜トランジスタ1の製造方法について、図2A〜図2Gを用いて説明する。図2A〜図2Gは、本発明の実施の形態に係る薄膜トランジスタの製造方法における各工程の断面図である。
次に、本実施の形態に係る薄膜トランジスタ1の作用効果について、本発明に至った経緯も含めて説明する。
次に、上記の実施の形態に係る薄膜トランジスタ1を表示装置に適用した例について、図11及び図12を用いて説明する。なお、本実施の形態では、有機EL表示装置への適用例について説明する。
以上、薄膜トランジスタ及びその製造方法について、実施の形態に基づいて説明したが、本発明は、上記実施の形態に限定されるものではない。
10 基板
20 アンダーコート層
30、G1、G2 ゲート電極
40 ゲート絶縁層
50 酸化物半導体層
51 第1領域
52 第2領域
50S、S1、S2 ソース領域
50D、D1、D2 ドレイン領域
60 保護層
70S ソース電極
70D ドレイン電極
100 有機EL表示装置
110 TFT基板
120 画素
130 有機EL素子
131 陽極
132 EL層
133 陰極
140 ゲート配線
150 ソース配線
160 電源配線
SwTr スイッチングトランジスタ
DrTr 駆動トランジスタ
C キャパシタ
Claims (17)
- ゲート電極と、
前記ゲート電極の上方に配置されたゲート絶縁層と、
前記ゲート絶縁層の上方に配置された酸化物半導体層と、
前記酸化物半導体層と電気的に接続されたソース電極及びドレイン電極とを備え、
前記酸化物半導体層を構成する金属元素には少なくともインジウムが含まれており、
前記酸化物半導体層の内部領域であって前記ゲート絶縁層と近接する領域にはフッ素が含有されており、
前記酸化物半導体層における前記ゲート絶縁層と近接する領域のフッ素濃度は、前記酸化物半導体層における前記ソース電極又はドレイン電極とのコンタクト領域のフッ素濃度よりも高い
薄膜トランジスタ。 - 前記酸化物半導体層における前記フッ素が含有されている領域において、前記ゲート絶縁層側の領域のフッ素濃度は、前記ゲート絶縁層とは反対側の領域のフッ素濃度よりも大きい
請求項1に記載の薄膜トランジスタ。 - 前記酸化物半導体層における前記フッ素が含有されている領域のフッ素濃度は、前記ゲート絶縁層に近づく方向に向けて漸次増加している
請求項2に記載の薄膜トランジスタ。 - 前記酸化物半導体層における前記フッ素が含有されている領域の膜厚は、少なくとも5nm以上である
請求項1〜3のいずれか1項に記載の薄膜トランジスタ。 - 前記酸化物半導体層における前記フッ素が含有されている領域の膜厚は、少なくとも20nm以上である
請求項1〜3のいずれか1項に記載の薄膜トランジスタ。 - 前記酸化物半導体層のフッ素含有濃度は、少なくとも前記酸化物半導体層の水素含有濃度よりも高い
請求項1〜5のいずれか1項に記載の薄膜トランジスタ。 - 前記酸化物半導体層を構成する金属元素には、さらに、ガリウム及び亜鉛の少なくとも一方又は両方が含まれている
請求項1〜6のいずれか1項に記載の薄膜トランジスタ。 - さらに、前記酸化物半導体層上に形成された保護層を備える
請求項1〜7のいずれか1項に記載の薄膜トランジスタ。 - ゲート電極を形成する工程と、
前記ゲート電極の上方にゲート絶縁層を形成する工程と、
前記ゲート絶縁層の上方にフッ素を含有する酸化物半導体層を形成する工程と、
前記酸化物半導体層と電気的に接続されるように前記酸化物半導体層の上方にソース電極及びドレイン電極を形成する工程とを含み、
前記酸化物半導体層を構成する金属元素には少なくともインジウムが含まれており、
前記酸化物半導体層の内部領域であって前記ゲート絶縁層と近接する領域にはフッ素が含有されており、
前記酸化物半導体層における前記ゲート絶縁層と近接する領域のフッ素濃度は、前記酸化物半導体層における前記ソース電極又はドレイン電極とのコンタクト領域のフッ素濃度よりも高い
薄膜トランジスタの製造方法。 - 前記酸化物半導体層における前記フッ素が含有されている領域において、前記ゲート絶縁層側の領域のフッ素濃度は、前記ゲート絶縁層とは反対側の領域のフッ素濃度よりも大きい
請求項9に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層における前記フッ素が含有されている領域のフッ素濃度は、前記ゲート絶縁層に近づく方向に向けて漸次増加している
請求項10に記載の薄膜トランジスタの製造方法。 - フッ素を含むガスを用いて前記酸化物半導体層にフッ素を導入する
請求項9〜11のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層における前記フッ素が含有されている領域の膜厚は、少なくとも5nm以上である
請求項9〜12のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層における前記フッ素が含有されている領域の膜厚は、少なくとも20nm以上である
請求項9〜12のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層のフッ素含有濃度は、少なくとも前記酸化物半導体層の水素含有濃度よりも高い
請求項9〜14のいずれか1項に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層を構成する金属元素には、さらに、ガリウム及び亜鉛の少なくとも一方又は両方が含まれている
請求項9〜15のいずれか1項に記載の薄膜トランジスタの製造方法。 - 請求項1〜8のいずれか1項に記載の薄膜トランジスタを備える有機EL表示装置であって、
マトリクス状に配置された複数の画素と、
前記複数の画素の各々に対応して形成された有機EL素子とを備え、
前記薄膜トランジスタは、前記有機EL素子を駆動する駆動トランジスタである
有機EL表示装置。
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