WO2014166168A1 - 薄膜晶体管、阵列基板、制备方法以及显示装置 - Google Patents

薄膜晶体管、阵列基板、制备方法以及显示装置 Download PDF

Info

Publication number
WO2014166168A1
WO2014166168A1 PCT/CN2013/077730 CN2013077730W WO2014166168A1 WO 2014166168 A1 WO2014166168 A1 WO 2014166168A1 CN 2013077730 W CN2013077730 W CN 2013077730W WO 2014166168 A1 WO2014166168 A1 WO 2014166168A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
drain
gate
forming
composite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/077730
Other languages
English (en)
French (fr)
Inventor
孟庆超
罗强强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/378,491 priority Critical patent/US10326024B2/en
Publication of WO2014166168A1 publication Critical patent/WO2014166168A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor and an array substrate thereof, a method for preparing the same, and a display device including the array substrate. Background technique
  • flat panel display devices have replaced cumbersome CRT (Cathode Ray Tube) display devices in people's daily lives.
  • CRT Cathode Ray Tube
  • LCD Liquid Crystal Display
  • OLED Organic
  • Light-Emitting Diode Organic Light Emitting Diode
  • LCD display device and active matrix driven OLED (Active Matrix) during imaging
  • AMOLED Organic Light Emission Display
  • TFT thin film transistor
  • the thin film transistor includes a substrate 1 and a gate layer 2, a gate insulating layer 4, an active layer, and a corresponding isolation layer (ie, composite layer 5), a source layer 6, and a drain formed on the substrate 1.
  • a source (Source) and a drain (Drain) in a thin film transistor are usually disposed in the same layer, for example, a drain layer 6 and a source layer 3 with gaps or trenches interposed therebetween.
  • the source/drain film layer is formed by a film forming step, and then the source/drain film layer is exposed, developed, and etched to form a source/drain with a gap or a trench therebetween. Thereby forming mutually separated source and drain electrodes in the same layer.
  • the array substrate includes the above-mentioned thin film transistor (TFT) and the passivation layer 7, and the pixel electrode layer 8, wherein the passivation layer 7 is disposed above the TFT, and the passivation layer 7 is further provided with a via hole.
  • the pixel electrode layer 8 is disposed above the passivation layer 7, and the drain layer 3 of the TFT and the pixel electrode layer 8 are connected through the via 9.
  • the channel (the conductive region confined between the source and the drain is called the channel) often appears to be not completely etched, so that the source and drain are out.
  • the phenomenon of bridge now causes poor pixel spots (Pixel) and lowers the product quality level (for example, the product quality level is reduced from P to S). Therefore, how to ensure complete blocking between the source and the drain in the thin film transistor, improving product quality has become a problem to be solved in the industry. Summary of the invention
  • An object of the present invention is to provide a thin film transistor, an array substrate, a preparation method, and a display device.
  • the thin film transistor and the corresponding array substrate can be completely blocked between the source and the drain, thereby ensuring a source and a drain. There is no bridging phenomenon and the product quality of the display device is improved.
  • a thin film transistor includes a substrate and a gate layer, a source layer, and a drain layer disposed on the substrate, wherein the source layer and the drain layer are disposed at The different layers are disposed and the drain layer is disposed in the same layer as the gate layer.
  • a gap is formed between the drain layer and the gate layer; the source layer is disposed above the gate layer, and between the source layer and the gate layer a gate insulating layer disposed above the gate layer and below the composite layer, the composite layer covering the gap from the gate insulating layer and partially extending to the Above the drain layer.
  • the gate layer, the source layer, and the drain layer are each formed of at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, and copper, the gate layer, the source
  • the thickness of the pole and drain layers ranges from 2000 to 1000 ⁇ .
  • the composite layer includes an active layer and an ohmic contact layer disposed over the active layer, the active layer being formed of an amorphous silicon material, the active layer having a thickness ranging from 200 to
  • the ohmic contact layer is formed of an amorphous silicon material doped with phosphorus, and the ohmic contact layer has a thickness ranging from 200 to 3000 ⁇ .
  • the composite layer includes an active layer and an etch barrier layer disposed over the active layer, the active layer using indium gallium oxide, indium oxide, indium tin oxide, indium gallium oxide Forming at least one material in the tin, the active layer having a thickness ranging from 100 to 2000 A; and the etching barrier layer adopting at least two of silicon oxide, silicon nitride, tantalum oxide, and aluminum oxide The material is formed, and the etching barrier layer has a thickness ranging from 500 to 4000 ⁇ .
  • the gate insulating layer is a single layer, a double layer or a plurality of layers, and at least one of silicon oxide, silicon nitride, germanium oxide, silicon oxynitride, and aluminum oxide is used.
  • the material is formed, and the thickness of the gate insulating layer ranges from 2000 to 6000 A.
  • an array substrate comprising the above-described thin film transistor.
  • the array substrate further includes a passivation layer disposed above the source layer and the drain layer, and the passivation layer is disposed adjacent to a region of the drain layer
  • the via layer is formed of at least two materials of silicon oxide, silicon nitride, tantalum oxide, and aluminum oxide, and the passivation layer has a thickness ranging from 1000 to 4000 ⁇ .
  • the array substrate further includes a pixel electrode layer disposed above the passivation layer, the drain layer and the pixel electrode layer being connected by via holes, the pixel electrode layer
  • the material is formed by at least one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide.
  • the thickness of the pixel electrode layer ranges from 300 to 150 ⁇ .
  • a display device comprising the above array substrate.
  • a method of fabricating a thin film transistor includes forming the source layer and the drain layer on different layers and forming a gate layer and a drain layer on a same layer. A step of.
  • the step of forming the source layer and the drain layer on different layers and forming the gate layer and the drain layer on the same layer includes:
  • the pattern of the gate layer and the drain layer is simultaneously formed by one patterning process, and the pattern of the source layer is formed by another patterning process.
  • a method of fabricating a thin film transistor includes: forming a pattern of a gate layer and a drain layer on a substrate, wherein the gate layer and the drain layer have a gap or a trench Slot
  • a pattern of the source layer is formed on the composite layer corresponding to the region of the gate layer.
  • the pattern of the gate layer and the drain layer is formed on the substrate, and the step of having a gap or a trench between the gate layer and the drain layer comprises: forming an electrode metal film on the substrate A pattern including a gate layer and a drain layer is formed by one patterning process.
  • the step of forming a pattern of a gate insulating layer on the gate layer includes: forming a gate insulating layer film, forming a pattern of a gate insulating layer on the gate layer by one patterning process .
  • the forming a composite layer on the gate insulating layer and a portion of the drain layer comprises: forming a composite layer film, the composite layer film comprising an active layer film and an ohmic contact layer film disposed over the active layer film, by a patterning process in the gate insulating layer A pattern of the composite layer is formed on a portion of the drain layer.
  • the step of forming a pattern of a composite layer on the gate insulating layer and a portion of the drain layer includes: forming a composite layer film, the composite layer film including an active layer film, and being disposed in the An etch barrier film over the active layer forms a pattern of a composite layer on the gate insulating layer and a portion of the drain layer by a patterning process.
  • the step of forming a pattern of the source layer on the composite layer corresponding to the region of the gate layer comprises: forming an electrode metal film corresponding to the composite layer by a patterning process The region of the gate layer forms a source layer pattern.
  • a method of fabricating an array substrate comprising the above-described method of fabricating a thin film transistor.
  • a via hole is formed in the passivation layer, and a pattern including a pixel electrode layer is formed over the passivation layer, and the drain layer is connected to the pixel electrode layer through a via.
  • the step of forming a pattern of the passivation layer on the source layer, a portion of the composite layer not covered by the source layer, and a portion of the drain layer not covered by the composite layer includes: Forming a passivation layer film, forming a passivation layer on the source layer, a portion of the composite layer not covered by the source layer, and a portion of the drain layer not covered by the composite layer by a patterning process The pattern of the hole.
  • the via is formed in the passivation layer, and a pattern of the pixel electrode layer is formed over the passivation layer, and the step of connecting the drain layer and the pixel electrode layer through the via includes Forming a transparent conductive film on the substrate on which step S5) is completed, and forming a pattern of the pixel electrode layer over the passivation layer by one patterning process, the drain layer and the pixel electrode layer being connected through via holes.
  • 1A is a cross-sectional view of a thin film transistor in the prior art
  • 1B is a cross-sectional view of an array substrate in the prior art
  • Embodiment 2 is a cross-sectional view of an array substrate in Embodiment 1 of the present invention.
  • 3A and 3a are a cross-sectional view and a plan view, respectively, of an array substrate on which a gate layer and a drain layer are formed;
  • FIGS. 3B and 3b are respectively a cross-sectional view and a plan view of an array substrate on which a gate insulating layer is formed; and FIGS. 3C-3E are cross-sectional views of an array substrate on which a source layer is formed;
  • 3e is a schematic plan view of an array substrate forming a source layer
  • FIGS. 3F and 3f are respectively a cross-sectional view and a plan view of an array substrate forming a composite layer
  • FIGS. 3G and 3g are respectively a cross-sectional view and a plan view of an array substrate forming a passivation layer and via holes
  • FIGS. 3H and 3h are respectively forming a pixel electrode layer.
  • FIG. 4 is a plan view of an array substrate having a plurality of TFT arrays.
  • the present embodiment provides a thin film transistor including a substrate and a gate layer, a source layer, and a drain layer disposed on the substrate, wherein the source layer and the drain layer are disposed on different layers, and The drain layer is disposed in the same layer as the gate layer.
  • An array substrate is also provided, including the thin film transistor described above.
  • the drain layer 3 is disposed in the same layer as the gate layer 2 a gap or a trench is formed between the drain layer 3 and the gate layer 2 on the substrate 1;
  • the source layer 6 is disposed above the gate layer 2
  • the source A gate insulating layer 4 and a composite layer 5 are disposed between the layer 6 and the gate layer 2
  • the gate insulating layer 4 is disposed above the gate layer 2 and below the composite layer 5, the composite layer 5 covering the gap or trench from the gate insulating layer 4 and partially extending over the drain layer 3.
  • the gate layer 2, the source layer 6 and the drain layer 3 may each be formed of at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium and copper, and the gate layer 2
  • the thickness of the source layer 6 and the drain layer 3 ranges from 2000 to 1000 ⁇ .
  • the composite layer 5 includes an active layer and an etch barrier layer disposed above the active layer, wherein the active layer is indium gallium oxide, indium oxide, indium tin oxide, and oxidation.
  • the active layer is indium gallium oxide, indium oxide, indium tin oxide, and oxidation.
  • the etch barrier layer has a thickness ranging from 500 to 4000 ⁇ .
  • the gate insulating layer 4 may be a single layer, a double layer or a plurality of layers, and may be formed of at least one of silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride, and aluminum oxide.
  • the thickness of the gate insulating layer 4 ranges from 2000 to 6000 A.
  • the array substrate in this embodiment includes the TFT described above, and further includes a passivation layer 7 and a pixel electrode layer 8.
  • the passivation layer 7 is disposed above the source layer 6 and the drain layer 3,
  • the passivation layer 7 is provided with a via hole 9 corresponding to the region of the drain layer 3, and the passivation layer 7 may be formed of at least two materials of silicon oxide, silicon nitride, germanium oxide, and aluminum oxide.
  • the passivation layer 7 has a thickness ranging from 1000 to 4000 ⁇ .
  • the pixel electrode layer 8 is disposed above the passivation layer 7, and the drain layer 3 and the pixel electrode layer 8 are connected through a via 9.
  • the pixel electrode layer 8 may be indium gallium oxide or indium oxide. Forming at least one of indium tin oxide and indium gallium tin oxide, the pixel electrode layer 8 having a thickness ranging from 300 to 1500 ⁇ .
  • the method for preparing the thin film transistor includes the steps of forming the gate layer 2 and the drain layer 3 on the same layer; and the method for preparing the array substrate, except for the steps of the method for preparing the thin film transistor.
  • the method further includes the steps of forming the passivation layer 7, the via hole 9, and connecting the drain layer 3 and the pixel electrode layer 8 through the via hole 9.
  • the thin film transistor is fabricated by using two patterning processes on the substrate, respectively.
  • a pattern including a gate layer 2, a drain layer 3, and a source layer 6 is formed thereon, wherein a patterning process simultaneously forms a pattern including the gate layer 2 and the drain layer 3, and another patterning process is formed including The pattern of the source layer 6.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.; A process of forming a pattern using a photoresist, a mask, an exposure machine, or the like, including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the method for fabricating the above array substrate includes, for example, the following steps (step S1) - step S5), that is, the step of forming a thin film transistor):
  • Step S1) forming a pattern including the gate layer 2 and the drain layer 3 on the substrate 1, and a gap or a trench is formed between the gate layer 2 and the drain layer 3.
  • an electrode metal film is first formed on the substrate 1, and a pattern including the gate layer 2, the gate scan line 21, and the drain layer 3 is formed by a patterning process using a common mask, as shown in FIGS. 3A and 3a. Show. Among them, an electrode metal film is formed on the substrate 1 by deposition, sputtering or thermal evaporation.
  • the ratios of the cross-sectional view 3A to the plan view 3a are set to different ratios; and at the same time, in order to facilitate understanding of the position between the layers of the thin film transistor Relationship, each layer in each plan view is set to have a certain transparency, and the following plan views are the same as the respective cross-sectional views.
  • a gate insulating film (FGI) is formed on the substrate 1 on which step S1) is completed.
  • a gate insulating layer 4 is formed on the gate layer 2 as shown in FIGS. 3B and 3b.
  • the gate insulating layer film may be formed by plasma enhanced chemical vapor deposition, and the gate insulating layer 4 may be formed by a single photolithography process using a common mask.
  • Step S3) forming a pattern including the composite layer 5 on the gate insulating layer 4 and a part of the drain layer 3.
  • a composite layer film 50 is formed on the substrate 1 on which the step S2) is completed, and a composite film layer may be formed by deposition, sputtering or thermal evaporation.
  • the composite layer film 50 includes a source layer film and an etch barrier film disposed over the active layer film (deposited separately during deposition; respectively), which may be used in the gate insulating layer 4 and a portion by a patterning process using a conventional mask
  • a pattern including the composite layer 5 is formed on the drain layer 3 as shown in Figs. 3F and 3f.
  • Other reticle such as a halftone reticle, capable of implementing the structure is employed.
  • an electrode metal film 60 is formed on the substrate 1 on which the step S3) is completed, as shown in FIG. 3D, the gate layer may be corresponding to the gate layer on the composite layer 5 by a patterning process using a conventional mask.
  • the area of 2 forms a pattern including the source layer 6 and the data line 61 as shown in Figs. 3E, 3e.
  • an electrode metal film is formed on the substrate 1 by deposition, sputtering or thermal evaporation. Of course, other reticles capable of realizing the structure can also be employed. It should be understood that, in order to process the process, in step S3) and step S4), it is actually possible to form the composite film 50 (as shown in FIG.
  • the thin film transistor is completed, and the gate scan line 21 and the data line are formed in advance.
  • step S4 a passivation film is formed on the substrate 1 on which step S4) is completed (PVX)
  • Deposition may be formed on the source layer 6, a portion of the composite layer 5 not covered by the source layer 6, and a portion of the drain layer not covered by the composite layer 5 by a patterning process using a common mask
  • a pattern including the passivation layer 7 is formed, and a pattern including the via holes 9 is formed in the passivation layer 7 by etching.
  • a passivation layer film is formed by deposition, sputtering or thermal evaporation. Of course, other reticles capable of realizing the structure can also be employed.
  • Step S6 forming a pattern including the pixel electrode layer 8 over the passivation layer 7, and the drain electrode layer 3 and the pixel electrode layer 8 are connected through the via hole 9.
  • a transparent conductive film is formed on the substrate 1 on which the step S5) is completed, and a pattern including the pixel electrode layer 8 can be formed over the passivation layer 7 by a patterning process using a common mask.
  • the drain layer 3 and the pixel electrode layer 8 are connected through a via 9; wherein a transparent conductive film is formed by deposition, sputtering or thermal evaporation.
  • the active layer in the thin film transistor is formed by using a metal oxide semiconductor such as at least one of indium gallium oxide (IGZO), indium oxide, indium tin oxide, and indium gallium tin oxide.
  • IGZO indium gallium oxide
  • the electron mobility between the electrode layer and the drain layer is increased, so that a good electron mobility between the source layer and the drain layer can be obtained.
  • the embodiment further provides a display device comprising the above array substrate. As shown in FIG. 4, an array of a plurality of TFTs is arranged on the array substrate.
  • Example 2
  • the active layer in the thin film transistor and the corresponding array substrate of the present embodiment is formed of an amorphous silicon material.
  • the composite layer includes an active layer and an ohmic contact layer disposed above the active layer, the active layer is formed of an amorphous silicon material, and the active layer has a thickness ranging from 200 ⁇ 3000 A;
  • the ohmic contact layer is formed of an amorphous silicon material doped with phosphorus, and the ohmic contact layer has a thickness ranging from 200 to 3000 ⁇ .
  • the step S3) is specifically: forming a pattern including a composite layer on the substrate on which the step S2) is completed, the composite layer including an active layer and an ohmic contact layer disposed above the active layer (formation process)
  • the layers are sequentially deposited, respectively, and a composite layer is formed on the gate insulating layer and a portion of the drain layer by a patterning process using a common mask.
  • the active layer is formed of an amorphous silicon material, and thus the electron mobility between the source layer and the drain layer is smaller than that of the first embodiment.
  • the source and the drain are formed on different layers (specifically, the drain layer and the gate layer are formed in the same layer, the source layer and the data The lines are done on the same floor). Therefore, in the method of fabricating the thin film transistor and the array substrate, the step of forming a channel by etching is no longer required between the source layer and the drain layer, thereby fundamentally avoiding the source and the drain.
  • the problem of bridging occurs, which reduces the bright spots caused by poor pixel defects caused by process problems and improves product yield.

Landscapes

  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Liquid Crystal (AREA)

Abstract

提供一种薄膜晶体管、阵列基板、制备方法以及显示装置。该薄膜晶体管包括基板（1）上的栅极层（2）、源极层（6）、漏极层（3），源极层（6）和漏极层（3）设置在不同的层上且漏极层（3）与栅极层（2）同层设置。

Description

薄膜晶体管、 阵列基板、 制备方法以及显示装置 技术领域
本发明属于显示技术领域， 具体涉及一种薄膜晶体管及其阵列基板、 它 们各自的制备方法以及包括该阵列基板的显示装置。 背景技术
随着科学技术的发展， 平板显示装置已取代笨重的 CRT(Cathode Ray Tube ,阴极射线管)显示装置日益深入人们的日常生活中。 目前， 常用的平板 显示装置包括 LCD( Liquid Crystal Display:液晶显示装置）和 OLED( Organic
Light-Emitting Diode:有机发光二极管）显示装置。
在成像过程中， LCD显示装置和有源矩阵驱动式 OLED ( Active Matrix
Organic Light Emission Display, 筒称 AMOLED )显示装置中的每一像素点都 由集成在阵列基板中的薄膜晶体管（ Thin Film Transistor: 筒称 TFT )来驱动， 从而实现图像显示。 薄膜晶体管作为发光控制开关， 是实现 LCD显示装置 和 OLED显示装置显示的关键， 直接关系到高性能显示装置的发展方向。
如图 1A所示， 薄膜晶体管包括基板 1以及在基板 1上形成的栅极层 2、 栅极绝缘层 4、有源层以及相应的隔绝层（即复合层 5 )、源极层 6、漏极层 3。 目前， 薄膜晶体管中的源极（Source )和漏极（ Drain )通常设置在同一层中， 例如形成中间间隔有间隙或沟槽的漏极层 6和源极层 3。 相应的， 现有的薄 膜晶体管的制备工艺中， 通过成膜步骤形成源漏极膜层， 然后对源漏极膜层 进行曝光、 显影、 刻蚀步骤形成中间有间隙或沟槽的源漏极， 从而形成位于 同一层中的互相分离的源极和漏极。
如图 1B所示， 阵列基板包括上述的薄膜晶体管 （TFT ) 以及钝化层 7、 像素电极层 8, 其中， 钝化层 7中设置于 TFT的上方， 钝化层 7中还开设有 过孔 9, 像素电极层 8设置于钝化层 7的上方， TFT的漏极层 3与像素电极 层 8通过过孔 9连接。
但是， 受目前工艺设备与工艺能力的限制， 沟道（被限制在源极和漏极 之间的导电区域称为沟道）常出现未被完全刻蚀的现象， 使得源极和漏极出 现桥连（Bridge )现象， 导致像素 （Pixel ) 出现亮点不良， 降低产品质量等 级（例如： 产品质量等级从 P级降到 S级）。 因此， 如何保证薄膜晶体管中 源极和漏极之间能完全阻断， 提高产品质量成为目前业界 待解决的问题。 发明内容
本发明的目的是提供一种薄膜晶体管、 阵列基板、 制备方法以及显示装 置， 该薄膜晶体管以及相应的阵列基板中源极与漏极之间能完全阻断， 从而 保证源极与漏极之间不会出现桥连现象， 提高了显示装置的产品质量。
根据本发明的第一方面， 提供一种薄膜晶体管， 包括基板以及设置于所 述基板上的栅极层、 源极层、 漏极层， 其中所述源极层与所述漏极层设置在 不同的层上且所述漏极层与所述栅极层同层设置。
在一个示例中， 所述漏极层与所述栅极层之间开有间隙； 所述源极层设 置在所述栅极层的上方， 所述源极层与所述栅极层之间设置有栅极绝缘层以 及复合层， 所述栅极绝缘层设置于所述栅极层上方以及复合层的下方， 所述 复合层从所述栅极绝缘层覆盖所述间隙并部分延伸至所述漏极层上方。
在一个示例中， 所述栅极层、 源极层和漏极层均采用钼、 钼铌合金、 铝、 铝钕合金、 钛和铜中的至少一种材料形成， 所述栅极层、 源极层和漏极层的 厚度范围为 2000 ~ 1000θΑ。
在一个示例中， 所述复合层包括有源层以及设置于所述有源层上方的欧 姆接触层，所述有源层采用非晶硅材料形成，所述有源层的厚度范围为 200 ~
3000 A; 所述欧姆接触层采用掺杂磷元素的非晶硅材料形成， 所述欧姆接触 层的厚度范围为 200 ~ 3000 A。
在一个示例中， 所述复合层包括有源层以及设置于所述有源层上方的刻 蚀阻挡层， 所述有源层采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡 中的至少一种材料形成， 所述有源层的厚度范围为 100 ~ 2000 A; 所述刻蚀 阻挡层采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少两种材料形 成， 所述刻蚀阻挡层的厚度范围为 5 00 ~ 4000 A。
在一个示例中， 其特征在于， 所述栅极绝缘层为单层、 双层或多层， 采 用硅氧化物、 硅氮化物、 铪氧化物、 硅氮氧化物、 铝氧化物中的至少一种材 料形成， 所述栅极绝缘层的厚度范围为 2000 ~ 6000 A。 根据本发明的第二方面， 提供一种阵列基板， 包括上述的薄膜晶体管。 在一个示例中， 所述阵列基板还包括钝化层， 所述钝化层设置在所述源 极层与所述漏极层的上方， 所述钝化层对应着漏极层的区域开设有过孔， 所 述钝化层采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少两种材料 形成， 所述钝化层的厚度范围为 1000 ~ 4000 A。
在一个示例中， 所述阵列基板还包括像素电极层， 所述像素电极层设置 在所述钝化层上方， 所述漏极层与所述像素电极层通过过孔连接， 所述像素 电极层采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材 料形成， 所述像素电极层的厚度范围为 300 ~ 150θ Α。
根据本发明的第三方面， 提供一种显示装置， 包括上述的阵列基板。 根据本发明的第四方面， 提供一种薄膜晶体管的制备方法， 包括将所述 源极层与所述漏极层形成在不同的层上且将栅极层与漏极层形成在同一层上 的步骤。
在一个示例中， 所述将所述源极层与所述漏极层形成在不同的层上且将 栅极层与漏极层形成在同一层上的步骤包括：
通过一次构图工艺同时形成所述栅极层和所述漏极层的图形， 以及通过 另一次构图工艺形成所述源极层的图形。
根据本发明的第五方面， 提供一种薄膜晶体管的制备方法， 包括： 在基板上形成栅极层以及漏极层的图形， 所述栅极层与所述漏极层之间 具有间隙或沟槽；
在所述栅极层上形成栅极绝缘层的图形；
在所述栅极绝缘层与部分所述漏极层上形成复合层的图形；
在所述复合层上对应着所述栅极层的区域形成源极层的图形。
在一个示例中， 所述在基板上形成栅极层以及漏极层的图形， 所述栅极 层与所述漏极层之间具有间隙或沟槽的步骤包括：在基板上形成电极金属膜， 通过一次构图工艺形成包括栅极层和漏极层的图形。
在一个示例中，所述在所述栅极层上形成栅极绝缘层的图形的步骤包括： 形成栅极绝缘层膜， 通过一次构图工艺在所述栅极层上形成栅极绝缘层的图 形。
在一个示例中， 所述在所述栅极绝缘层与部分所述漏极层上形成复合层 的图形的步骤包括： 形成复合层膜， 所述复合层膜包括有源层膜以及设置于 所述有源层膜上方的欧姆接触层膜， 通过一次构图工艺在在所述栅极绝缘层 与部分所述漏极层上形成复合层的图形。
在一个示例中， 所述在所述栅极绝缘层与部分所述漏极层上形成复合层 的图形的步骤包括： 形成复合层膜， 所述复合层膜包括有源层膜以及设置于 所述有源层上方的刻蚀阻挡层膜， 通过一次构图工艺在在所述栅极绝缘层与 部分所述漏极层上形成复合层的图形。
在一个示例中， 所述在所述复合层上对应着所述栅极层的区域形成源极 层的图形的步骤包括： 形成电极金属膜， 通过一次构图工艺在所述复合层上 对应着所述栅极层的区域形成源极层图形。
根据本发明的第六方面， 提供一种阵列基板的制备方法， 包括上述的薄 膜晶体管的制备方法。
在一个示例中， 还包括如下步骤：
在所述源极层、 未被所述源极层覆盖的部分复合层以及未被所述复合层 覆盖的部分漏极层上形成钝化层的图形；
在所述钝化层中形成过孔， 在所述钝化层上方形成包括像素电极层的图 形， 所述漏极层与所述像素电极层通过过孔连接。
在一个示例中， 所述在所述源极层、 未被所述源极层覆盖的部分复合层 以及未被所述复合层覆盖的部分漏极层上形成钝化层的图形的步骤包括： 形 成钝化层膜， 通过一次构图工艺在所述源极层、 未被所述源极层覆盖的部分 复合层以及未被所述复合层覆盖的部分漏极层上形成包括钝化层以及过孔的 图形。
在一个示例中， 所述在所述钝化层中形成过孔， 在所述钝化层上方形成 像素电极层的图形，所述漏极层与所述像素电极层通过过孔连接的步骤包括： 在完成步骤 S5 )的基板上形成透明导电膜， 通过一次构图工艺在所述钝化层 上方形成像素电极层的图形， 所述漏极层与所述像素电极层通过过孔连接。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1A为现有技术中薄膜晶体管的剖视图；
图 1B为现有技术中阵列基板的剖视图；
图 2为本发明实施例 1中阵列基板的剖视图；
图 3A、 3a分别为形成栅极层和漏极层的阵列基板的剖视图与平面示意 图；
图 3B、 3b分别为形成栅极绝缘层的阵列基板的剖视图与平面示意图； 图 3C-3E为形成源极层的阵列基板的剖视图；
图 3e为形成源极层的阵列基板的平面示意图；
图 3F、 3f分别为形成复合层的阵列基板的剖视图与平面示意图； 图 3G、 3g分别为形成钝化层和过孔的阵列基板的剖视图与平面示意图； 图 3H、 3h分别为形成像素电极层的阵列基板的剖视图与平面示意图； 图 4为具有多个 TFT阵列的阵列基板的平面示意图。
附图标记： ΡΙ,Ι—基板； Ρ2,2—栅极层； Ρ3,3—漏极层； Ρ4,4-栅极绝缘 层； Ρ5,5 -复合层； 50-复合层膜； Ρ6,6 -源极层； 60-电极金属膜； Ρ7,7 -钝 化层； Ρ8,8 -像素电极层； Ρ9,9 -过孔； 21-栅极扫描线； 61-数据线。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。 实施例 1:
本实施例提供一种薄膜晶体管， 包括基板以及设置于所述基板上的栅极 层、 源极层、 漏极层， 所述源极层与所述漏极层设置在不同的层上， 且所述 漏极层与所述栅极层同层设置。
还提供一种阵列基板， 包括上述的薄膜晶体管。
如图 2所示， 在薄膜晶体管中， 所述漏极层 3与所述栅极层 2同层设置 在所述基板 1上， 所述漏极层 3与所述栅极层 2之间开有间隙或沟槽； 所述 源极层 6设置在所述栅极层 2的上方， 所述源极层 6与所述栅极层 2之间设 置有栅极绝缘层 4以及复合层 5 , 所述栅极绝缘层 4设置于所述栅极层 2上 方以及复合层 5的下方， 所述复合层 5从所述栅极绝缘层 4覆盖所述间隙或 沟槽并部分延伸至所述漏极层 3上方。
其中， 所述栅极层 2、 源极层 6和漏极层 3均可采用钼、 钼铌合金、 铝、 铝钕合金、 钛和铜中的至少一种材料形成， 所述栅极层 2、 源极层 6和漏极 层 3的厚度范围为 2000 ~ 1000θΑ。
在本实施例中， 所述复合层 5包括有源层以及设置于所述有源层上方的 刻蚀阻挡层， 所述有源层采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓 锡中的至少一种材料形成， 所述有源层的厚度范围为 100 ~ 2000 A; 所述刻 蚀阻挡层可采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少两种材 料形成， 所述刻蚀阻挡层的厚度范围为 500 ~ 4000 A。
所述栅极绝缘层 4可为单层、双层或多层， 可采用硅氧化物、硅氮化物、 铪氧化物、 硅氮氧化物、 铝氧化物中的至少一种材料形成， 所述栅极绝缘层 4的厚度范围为 2000 ~ 6000 A。
本实施例中的阵列基板中包括上述的 TFT, 还包括钝化层 7以及像素电 极层 8, 所述钝化层 7设置在所述源极层 6与所述漏极层 3的上方， 所述钝 化层 7对应着漏极层 3的区域开设有过孔 9,所述钝化层 7可采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少两种材料形成， 所述钝化层 7的厚 度范围为 1000 ~ 4000 A。
所述像素电极层 8设置在所述钝化层 7上方， 所述漏极层 3与所述像素 电极层 8通过过孔 9连接，所述像素电极层 8可采用氧化铟镓辞、氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料形成， 所述像素电极层 8的厚度范 围为 300 ~ 1500 A。
相应的， 上述薄膜晶体管的制备方法， 包括将所述栅极层 2与所述漏极 层 3形成在同一层上的步骤； 上述阵列基板的制备方法， 除了上述薄膜晶体 管的制备方法的步骤外， 同时还包括形成所述钝化层 7、 所述过孔 9以及将 所述漏极层 3与所述像素电极层 8通过过孔 9连接的步骤。
在一个示例中， 薄膜晶体管的制备方法即分别采用两次构图工艺在基板 1上形成包括栅极层 2、漏极层 3以及源极层 6的图形，其中一次构图工艺同 时形成包括所述栅极层 2和所述漏极层 3的图形， 另一次构图工艺形成包括 所述源极层 6的图形。
在本发明中， 构图工艺， 可只包括光刻工艺， 或， 包括光刻工艺以及刻 蚀步骤， 同时还可以包括打印、 喷墨等其他用于形成预定图形的工艺； 光刻 工艺， 是指包括成膜、 曝光、 显影等工艺过程的利用光刻胶、 掩模板、 曝光 机等形成图形的工艺。 可根据本发明中所形成的结构选择相应的构图工艺。
如图 3A-3h所示， 上述阵列基板的制备方法例如包括如下步骤（其中步 骤 S1 ) -步骤 S5 ) 即形成薄膜晶体管的步骤）：
步骤 S1 ): 在基板 1上形成包括栅极层 2以及漏极层 3的图形， 所述栅 极层 2与所述漏极层 3之间开有间隙或沟槽。
在该步骤中： 先在基板 1上形成电极金属膜， 采用普通掩摸板通过一次 构图工艺形成包括栅极层 2、 栅极扫描线 21和漏极层 3的图形， 如图 3A、 3a所示。其中，采用沉积、溅射或热蒸发的方法在基板 1上形成电极金属膜。
这里，为能更突出地示意本实施例中阵列基板在制备过程中的剖面结构， 剖面图 3A与平面图 3a的比例设置为不同的比例； 同时， 为便于了解薄膜晶 体管的各层之间的位置关系， 各平面图中的各层设置为具有一定透明度， 以 下各平面图与各剖面图与此同。
步骤 S2 ): 在所述栅极层 2上形成包括栅极绝缘层 4的图形。
在该步骤中： 在完成步骤 S1 ) 的基板 1 上形成栅极绝缘层膜（FGI
Deposition ), 即在所述栅极层 2上形成栅极绝缘层 4, 如图 3B、 3b所示。 其 中， 形成栅极绝缘层膜可采用等离子体增强化学气相沉积法， 栅极绝缘层 4 可利用普通掩模板通过一次光刻工艺形成。
步骤 S3 ): 在所述栅极绝缘层 4与部分所述漏极层 3上形成包括复合层 5的图形。
在该步骤中： 在完成步骤 S2 ) 的基板 1上形成复合层膜 50, 形成复合 膜层可以采用沉积、 溅射或热蒸发等方法， 如图 3C所示， 所述复合层膜 50 包括有源层膜以及设置于所述有源层膜上方的刻蚀阻挡层膜（沉积过程中分 别依次沉积；)，可利用普通掩模板通过一次构图工艺在所述栅极绝缘层 4与部 分所述漏极层 3上形成包括复合层 5的图形， 如图 3F、 3f所示。 当然， 也可 采用其他能够实现本结构的掩模板， 例如半色调掩模板。
步骤 S4 )： 在所述复合层 5上对应着所述栅极层 2的区域形成包括源极 层 6的图形。
在该步骤中： 在完成步骤 S3 ) 的基板 1上形成电极金属膜 60, 如图 3D 所示， 可利用普通掩模板通过一次构图工艺在在所述复合层 5上对应着所述 栅极层 2的区域形成包括源极层 6和数据线 61的图形， 如图 3E、 3e所示。 其中， 采用沉积、 溅射或热蒸发的方法在基板 1上形成电极金属膜。 当然， 也可采用其他能够实现本结构的掩模板。 应该理解的是， 为了筒化工艺流程， 在步骤 S3 )和步骤 S4 ) 中， 实际 可以采用先形成复合层膜 50 (如图 3C所示 ), 然后形成电极金属膜 60 (如 图 3D所示；);接着采用构图工艺先形成包括相对上层的源极层 6和数据线 61 的图形 （如图 3E、 3e所示）， 然后采用构图工艺再形成包括相对下层的复合 层 5的图形 （如图 3F、 3f所示） 的工艺流程， 具体步骤这里不再详述。
至此， 薄膜晶体管即制备完成， 并预先形成了栅极扫描线 21 和数据线
61 , 以方便阵列基板的布线。
步骤 S5 ): 在所述源极层 6、 未被所述源极层 6覆盖的部分复合层 5以 及未被所述复合层 5覆盖的部分漏极层 3上形成包括钝化层 7以及过孔 9的 图形。
在该步骤中： 在完成步骤 S4 ) 的基板 1 上形成钝化层膜 （PVX
Deposition ), 可利用普通掩模板通过一次构图工艺在所述源极层 6、 未被所 述源极层 6覆盖的部分复合层 5以及未被所述复合层 5覆盖的部分漏极层上 形成包括钝化层 7的图形， 并采用刻蚀方式在所述钝化层 7中形成包括过孔 9 的图形。 其中， 采用沉积、 溅射或热蒸发的方法形成钝化层膜。 当然， 也 可采用其他能够实现本结构的掩模板。 步骤 S6 ): 在所述钝化层 7上方形成包括像素电极层 8的图形， 所述漏 极层 3与所述像素电极层 8通过所述过孔 9连接。
在该步骤中， 在完成步骤 S5 )的基板 1上形成透明导电膜， 可利用普通 掩模板通过一次构图工艺在所述钝化层 7上方形成包括像素电极层 8的图形， 所述漏极层 3与所述像素电极层 8通过过孔 9连接； 其中， 采用沉积、 溅射 或热蒸发的方法形成透明导电膜。 当然， 也可采用其他能够实现本结构的掩 模板。 本实施例中， 薄膜晶体管中的有源层采用了金属氧化物半导体， 例如氧 化铟镓辞（IGZO )、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料形 成， 使得源极层与漏极层之间的电子迁移率增加， 因此能获得较好的源极层 与漏极层之间的电子迁移率。
本实施例还提供一种显示装置， 包括上述的阵列基板， 如图 4所示， 在 该阵列基板上布置有多个 TFT的阵列。 实施例 2:
本实施例与实施例 1的区别在于， 本实施例薄膜晶体管以及相应的阵列 基板中的有源层采用非晶硅材料形成。
在本实施例中， 所述复合层包括有源层以及设置于所述有源层上方的欧 姆接触层，所述有源层采用非晶硅材料形成，所述有源层的厚度范围为 200 ~ 3000 A; 所述欧姆接触层采用掺杂磷元素的非晶硅材料形成， 所述欧姆接触 层的厚度范围为 200 ~ 3000 A。
本实施例中薄膜晶体管阵列基板的制备方法具体可参考实施例 1。 区别 在于， 所述步骤 S3 )具体为： 在完成步骤 S2 ) 的基板上形成包括复合层的 图形， 所述复合层包括有源层以及设置于所述有源层上方的欧姆接触层（形 成过程中分别依次沉积 ),利用普通掩模板通过一次构图工艺在所述栅极绝缘 层与部分所述漏极层上形成复合层。
本实施例中， 有源层采用了非晶硅材料形成， 因此源极层与漏极层之间 的电子迁移率相对实施例 1较小。 实施例 1、 2的薄膜晶体管以及相应的阵列基板中，通过将源极与漏极形 成在不同的层上（具体的是将漏极层与栅极层做在同一层， 源极层与数据线 做在同一层）。 因此， 在薄膜晶体管、 阵列基板的制备方法中， 在源极层与漏 极层之间不再需要通过刻蚀形成沟道的步骤， 从而从根本上避免了源极与漏 极发生桥连的问题， 降低了因工艺问题造成的像素不良而导致的亮点， 提高 了产品良率。 以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种薄膜晶体管，包括基板以及设置于所述基板上的栅极层、源极层、 漏极层， 其中所述源极层与所述漏极层设置在不同的层上且所述漏极层与所 述栅极层同层设置。
2.根据权利要求 1所述的薄膜晶体管，其中所述漏极层与所述栅极层之 间开有间隙或沟槽； 所述源极层设置在所述栅极层的上方， 所述源极层与所 述栅极层之间设置有栅极绝缘层以及复合层， 所述栅极绝缘层设置于所述栅 极层上方以及复合层的下方， 所述复合层从所述栅极绝缘层覆盖所述间隙或 沟槽并部分延伸至所述漏极层上方。
3.根据权利要求 2所述的薄膜晶体管， 其中所述栅极层、 源极层和漏极 层均采用钼、 钼铣合金、 铝、 铝钕合金、 钛和铜中的至少一种材料形成， 所 述栅极层、 源极层和漏极层的厚度范围为 2000 ~ 1000θΑ。
4.根据权利要求 3所述的薄膜晶体管，其中所述复合层包括有源层以及 设置于所述有源层上方的欧姆接触层， 所述有源层采用非晶硅材料形成， 所 述有源层的厚度范围为 200 ~ 3000 A; 所述欧姆接触层采用掺杂磷元素的非 晶硅材料形成， 所述欧姆接触层的厚度范围为 200 ~ 3000 A。
5.根据权利要求 3所述的薄膜晶体管，其中所述复合层包括有源层以及 设置于所述有源层上方的刻蚀阻挡层， 所述有源层采用氧化铟镓辞、 氧化铟 辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料形成， 所述有源层的厚度范围 为 100 ~ 2000 A; 所述刻蚀阻挡层采用硅氧化物、 硅氮化物、 铪氧化物、 铝 氧化物中的至少两种材料形成，所述刻蚀阻挡层的厚度范围为 5 00 ~ 4000 A。
6.根据权利要求 2所述的薄膜晶体管， 其中所述栅极绝缘层为单层、 双 层或多层， 采用硅氧化物、 硅氮化物、 铪氧化物、 硅氮氧化物、 铝氧化物中 的至少一种材料形成， 所述栅极绝缘层的厚度范围为 2000 ~ 6000 A。
7.—种阵列基板， 包括权利要求 1-6任一项所述的薄膜晶体管。
8.根据权利要求 7所述的阵列基板， 还包括钝化层， 所述钝化层设置在 所述源极层与所述漏极层的上方， 所述钝化层对应着漏极层的区域开设有过 孔， 所述钝化层采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少两 种材料形成， 所述钝化层的厚度范围为 1000 ~ 4000 A。
9.根据权利要求 8所述的阵列基板， 还包括像素电极层， 所述像素电极 层设置在所述钝化层上方， 所述漏极层与所述像素电极层通过过孔连接， 所 述像素电极层采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少 一种材料形成， 所述像素电极层的厚度范围为 300 ~ 1500 A。
10.一种显示装置， 包括权利要求 7-10任一项所述的阵列基板。
11.一种薄膜晶体管的制备方法， 包括将所述源极层与所述漏极层形成 在不同的层上且将栅极层与漏极层形成在同一层上的步骤。
12.根据权利要求 11所述的制备方法，其中所述将所述源极层与所述漏 极层形成在不同的层上且将栅极层与漏极层形成在同一层上的步骤包括： 通过一次构图工艺同时形成所述栅极层和所述漏极层的图形， 以及通过 另一次构图工艺形成所述源极层的图形。
13.一种薄膜晶体管的制备方法， 包括：
在基板上形成栅极层以及漏极层的图形， 所述栅极层与所述漏极层之间 具有间隙或沟槽；
在所述栅极层上形成栅极绝缘层的图形；
在所述栅极绝缘层与部分所述漏极层上形成复合层的图形；
在所述复合层上对应着所述栅极层的区域形成源极层的图形。
14.根据权利要求 13所述的制备方法，其中所述在基板上形成栅极层以 在基板上形成电极金属膜， 通过一次构图工艺形成栅极层和漏极层的图形。
15.根据权利要求 14所述的制备方法，其中所述在所述栅极层上形成栅 极绝缘层的图形的步骤包括： 形成栅极绝缘层膜， 通过一次构图工艺在所述 栅极层上形成栅极绝缘层的图形。
16.根据权利要求 15所述的制备方法，其中所述在所述栅极绝缘层与部 分所述漏极层上形成复合层的图形的步骤包括： 形成复合层膜， 所述复合层 膜包括有源层膜以及设置于所述有源层膜上方的欧姆接触层膜， 通过一次构 图工艺在在所述栅极绝缘层与部分所述漏极层上形成复合层的图形。
17.根据权利要求 15所述的制备方法，其中所述在所述栅极绝缘层与部 分所述漏极层上形成复合层的图形的步骤包括： 形成复合层膜， 所述复合层 膜包括有源层膜以及设置于所述有源层上方的刻蚀阻挡层膜， 通过一次构图 工艺在在所述栅极绝缘层与部分所述漏极层上形成复合层的图形。
18.根据权利要求 16或 17所述的制备方法， 其中在所述复合层上对应 着所述栅极层的区域形成源极层的图形的步骤包括： 形成电极金属膜， 通过 一次构图工艺在所述复合层上对应着所述栅极层的区域形成源极层图形。
19.一种阵列基板的制备方法， 其中包括权利要求 11-18任一所述的薄膜 晶体管的制备方法。
20.根据权利要求 19所述的制备方法， 还包括：
在所述源极层、 未被所述源极层覆盖的部分复合层以及未被所述复合层 覆盖的部分漏极层上形成钝化层的图形；
在所述钝化层中形成过孔， 在所述钝化层上方形成像素电极层的图形， 所述漏极层与所述像素电极层通过过孔连接。
21.根据权利要求 20所述的制备方法， 其中所述在所述源极层、 未被所 述源极层覆盖的部分复合层以及未被所述复合层覆盖的部分漏极层上形成钝 化层的图形的步骤包括： 形成钝化层膜， 通过一次构图工艺在所述源极层、 未被所述源极层覆盖的部分复合层以及未被所述复合层覆盖的部分漏极层上 形成钝化层以及过孔的图形。
22.根据权利要求 21所述的制备方法，其中所述在所述钝化层中形成过 孔， 在所述钝化层上方形成像素电极层的图形， 所述漏极层与所述像素电极 层通过过孔连接的步骤包括： 形成透明导电膜， 通过一次构图工艺在所述钝 化层上方形成像素电极层的图形， 所述漏极层与所述像素电极层通过过孔连 接。
PCT/CN2013/077730 2013-04-10 2013-06-24 薄膜晶体管、阵列基板、制备方法以及显示装置 Ceased WO2014166168A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/378,491 US10326024B2 (en) 2013-04-10 2013-06-24 Thin film transistor, array substrate, manufacturing method and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310123873.7A CN103219392B (zh) 2013-04-10 2013-04-10 薄膜晶体管、阵列基板、制备方法以及显示装置
CN201310123873.7 2013-04-10

Publications (1)

Publication Number Publication Date
WO2014166168A1 true WO2014166168A1 (zh) 2014-10-16

Family

ID=48817014

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/077730 Ceased WO2014166168A1 (zh) 2013-04-10 2013-06-24 薄膜晶体管、阵列基板、制备方法以及显示装置

Country Status (3)

Country Link
US (1) US10326024B2 (zh)
CN (1) CN103219392B (zh)
WO (1) WO2014166168A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097676A (zh) * 2015-09-24 2015-11-25 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板
US20170040466A1 (en) * 2015-03-18 2017-02-09 Boe Technology Group Co., Ltd. Thin film transistor and manufacturing method thereof, array substrate and display device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715200A (zh) * 2013-12-19 2014-04-09 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN103680317B (zh) * 2013-12-20 2015-09-23 合肥京东方光电科技有限公司 一种阵列基板及其制造方法和显示装置
KR102471021B1 (ko) * 2016-09-29 2022-11-25 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 이의 제조 방법
CN108958536A (zh) * 2018-03-28 2018-12-07 京东方科技集团股份有限公司 触控与显示驱动器集成模组及其制造方法、电子设备
CN110600426A (zh) * 2019-08-22 2019-12-20 武汉华星光电技术有限公司 阵列基板的制备方法及阵列基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7864257B2 (en) * 2007-12-24 2011-01-04 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same
CN102082179A (zh) * 2010-11-04 2011-06-01 友达光电股份有限公司 薄膜晶体管与具有此薄膜晶体管的像素结构
CN103000693A (zh) * 2012-10-08 2013-03-27 京东方科技集团股份有限公司 薄膜晶体管、显示器件及其制造方法、显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4422090A (en) * 1979-07-25 1983-12-20 Northern Telecom Limited Thin film transistors
US5198379A (en) * 1990-04-27 1993-03-30 Sharp Kabushiki Kaisha Method of making a MOS thin film transistor with self-aligned asymmetrical structure
WO1998023995A1 (en) * 1996-11-27 1998-06-04 Hitachi, Ltd. Active matrix liquid crystal display
KR101579135B1 (ko) 2008-12-03 2015-12-22 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
JP2011164196A (ja) * 2010-02-05 2011-08-25 Seiko Epson Corp 電気光学装置用基板、電気光学装置及び電子機器
KR101774933B1 (ko) * 2010-03-02 2017-09-06 삼성전자 주식회사 듀얼 디플리션을 나타내는 고 전자 이동도 트랜지스터 및 그 제조방법
KR101125904B1 (ko) * 2010-07-26 2012-03-21 서울대학교산학협력단 박막 트랜지스터 및 박막 트랜지스터의 제조 방법
KR101929834B1 (ko) * 2011-07-25 2018-12-18 삼성디스플레이 주식회사 박막 트랜지스터 기판, 이를 갖는 액정 표시 장치, 및 박막 트랜지스터 기판의 제조 방법
KR101903565B1 (ko) * 2011-10-13 2018-10-04 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
CN203423187U (zh) * 2013-04-10 2014-02-05 合肥京东方光电科技有限公司 薄膜晶体管、阵列基板以及显示装置
CN203420187U (zh) 2013-09-17 2014-02-05 浙江天铁实业股份有限公司 轨道吸音板装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7864257B2 (en) * 2007-12-24 2011-01-04 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same
CN102082179A (zh) * 2010-11-04 2011-06-01 友达光电股份有限公司 薄膜晶体管与具有此薄膜晶体管的像素结构
CN103000693A (zh) * 2012-10-08 2013-03-27 京东方科技集团股份有限公司 薄膜晶体管、显示器件及其制造方法、显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170040466A1 (en) * 2015-03-18 2017-02-09 Boe Technology Group Co., Ltd. Thin film transistor and manufacturing method thereof, array substrate and display device
US9882063B2 (en) * 2015-03-18 2018-01-30 Boe Technology Group Co., Ltd. Thin film transistor and manufacturing method thereof, array substrate and display device
CN105097676A (zh) * 2015-09-24 2015-11-25 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板
US9842867B2 (en) 2015-09-24 2017-12-12 Boe Technology Group Co., Ltd. Array substrate and method of manufacturing the same, and display panel

Also Published As

Publication number Publication date
US20160141424A1 (en) 2016-05-19
US10326024B2 (en) 2019-06-18
CN103219392A (zh) 2013-07-24
CN103219392B (zh) 2017-04-12

Similar Documents

Publication Publication Date Title
KR101213708B1 (ko) 어레이 기판 및 이의 제조방법
CN104576705B (zh) 一种阵列基板及制作方法、显示装置
KR101128333B1 (ko) 어레이 기판 및 이의 제조방법
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
WO2018176787A1 (zh) 阵列基板及其制备方法、显示面板
WO2017202035A1 (zh) 像素单元及其制备方法、阵列基板和显示装置
WO2016000336A1 (zh) 低温多晶硅tft阵列基板及其制备方法、显示装置
WO2015000247A1 (zh) 阵列基板、阵列基板的制备方法以及显示装置
WO2016023294A1 (zh) 阵列基板及制备方法和显示装置
WO2019109748A1 (zh) 阵列基板及其制备方法、显示装置
WO2015123975A1 (zh) 阵列基板及制备方法、显示面板
WO2014206035A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
WO2015096350A1 (zh) 阵列基板及其制备方法
KR101134989B1 (ko) 어레이 기판의 제조방법
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
WO2018176784A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN103219392B (zh) 薄膜晶体管、阵列基板、制备方法以及显示装置
WO2017173712A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN108493216B (zh) 一种tft阵列基板、显示装置及tft阵列基板的制备方法
KR20110009954A (ko) 어레이 기판 및 이의 제조방법
KR20140013166A (ko) 유기발광소자표시장치 및 그 제조방법
WO2015100859A1 (zh) 阵列基板及其制造方法和显示装置
WO2021097995A1 (zh) 一种阵列基板及其制备方法
KR20110053721A (ko) 어레이 기판 및 이의 제조방법
CN203423187U (zh) 薄膜晶体管、阵列基板以及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14378491

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13882046

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13882046

Country of ref document: EP

Kind code of ref document: A1