CN103219392A - 薄膜晶体管、阵列基板、制备方法以及显示装置 - Google Patents

薄膜晶体管、阵列基板、制备方法以及显示装置 Download PDF

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CN103219392A
CN103219392A CN2013101238737A CN201310123873A CN103219392A CN 103219392 A CN103219392 A CN 103219392A CN 2013101238737 A CN2013101238737 A CN 2013101238737A CN 201310123873 A CN201310123873 A CN 201310123873A CN 103219392 A CN103219392 A CN 103219392A
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electrode layer
drain electrode
composite bed
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CN103219392B (zh
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孟庆超
罗强强
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to PCT/CN2013/077730 priority patent/WO2014166168A1/zh
Priority to US14/378,491 priority patent/US10326024B2/en
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Abstract

本发明属于显示技术领域，具体涉及一种薄膜晶体管、阵列基板、制备方法以及显示装置。一种薄膜晶体管，包括基板以及设置于所述基板上的栅极层、源极层、漏极层，所述源极层与所述漏极层设置在不同的层上且所述漏极层与所述栅极层同层设置。采用该薄膜晶体管的阵列基板，由于源极与漏极之间能完全阻断，从而保证源极与漏极之间不会出现桥连现象，提高了显示装置的产品质量。

Description

薄膜晶体管、阵列基板、制备方法以及显示装置
技术领域
本发明属于显示技术领域，具体涉及一种薄膜晶体管、阵列基板、制备方法以及显示装置。
背景技术
随着科学技术的发展，平板显示装置已取代笨重的CRT(Cathode Ray Tube,阴极射线管)显示装置日益深入人们的日常生活中。目前，常用的平板显示装置包括LCD（Liquid CrystalDisplay：液晶显示装置）和OLED（Organic Light-Emitting Diode:有机发光二极管）显示装置。
在成像过程中，LCD显示装置和有源矩阵驱动式OLED（ActiveMatrix Organic Light Emission Display，简称AMOLED）显示装置中的每一像素点都由集成在阵列基板中的薄膜晶体管（ThinFilm Transistor：简称TFT）来驱动，从而实现图像显示。薄膜晶体管作为发光控制开关，是实现LCD显示装置和OLED显示装置显示的关键，直接关系到高性能显示装置的发展方向。
如图1A所示，薄膜晶体管包括基板1以及在基板上形成的栅极层2、栅极绝缘层4、有源层以及相应的隔绝层（即复合层5）、源极层6、漏极层3。目前，薄膜晶体管中的源极（Source）和漏极（Drain）通常设置在同一层中，例如形成中间间隔有间隙或沟槽的漏极层6和源极层3。相应的，现有的薄膜晶体管的制备工艺中，通过成膜步骤形成源漏极膜层，然后对源漏极膜层进行曝光、显影、刻蚀步骤形成中间有间隙或沟槽的源漏极，从而形成位于同一层中的互相分离的源极和漏极。
如图1B所示，阵列基板包括上述的薄膜晶体管（TFT）以及钝化层7、像素电极层8，其中，钝化层7中设置于TFT的上方，钝化层7中还开设有过孔9，像素电极层8设置于钝化层7的上方，TFT的漏极层3与像素电极层8通过过孔9连接。
但是，受目前工艺设备与工艺能力的限制，沟道（被限制在源极和漏极之间的导电区域称为沟道，栅压打开时源极和漏极之间的间隙或沟槽相对应的半导体部分）常出现未被完全刻蚀的现象，使得源极和漏极出现桥连（Bridge）现象，导致像素（Pixel）出现亮点不良，降低产品质量等级（例如：产品质量等级从P级降到S级）。因此，如何保证薄膜晶体管中源极和漏极之间能完全阻断，提高产品质量成为目前业界亟待解决的问题。
发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不足，提供一种薄膜晶体管、阵列基板、制备方法以及显示装置，该薄膜晶体管以及相应的阵列基板中源极与漏极之间能完全阻断，从而保证源极与漏极之间不会出现桥连现象，提高了显示装置的产品质量。
解决本发明技术问题所采用的技术方案是该薄膜晶体管，包括基板以及设置于所述基板上的栅极层、源极层、漏极层，所述源极层与所述漏极层设置在不同的层上且所述漏极层与所述栅极层同层设置。
优选的是，所述漏极层与所述栅极层同层设置在所述基板上，所述漏极层与所述栅极层之间开有间隙；所述源极层设置在所述栅极层的上方，所述源极层与所述栅极层之间设置有栅极绝缘层以及复合层，所述栅极绝缘层设置于所述栅极层上方以及复合层的下方，所述复合层从所述栅极绝缘层覆盖所述间隙并部分延伸至所述漏极层上方。
优选的是，所述栅极层、源极层和漏极层均采用钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种材料形成，所述栅极层、源极层和漏极层的厚度范围为
Figure BDA00003031933300021
优选的是，所述复合层包括有源层以及设置于所述有源层上方的欧姆接触层，所述有源层采用非晶硅材料形成，所述有源层的厚度范围为
Figure BDA00003031933300031
所述欧姆接触层采用掺杂磷元素的非晶硅材料形成，所述欧姆接触层的厚度范围为
Figure BDA00003031933300032
优选的是，所述复合层包括有源层以及设置于所述有源层上方的刻蚀阻挡层，所述有源层采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种材料形成，所述有源层的厚度范围为
Figure BDA00003031933300033
所述刻蚀阻挡层采用硅氧化物、硅氮化物、铪氧化物、铝氧化物中的至少两种材料形成，所述刻蚀阻挡层的厚度范围为
Figure BDA00003031933300034
优选的是，其特征在于，所述栅极绝缘层为单层、双层或多层，采用硅氧化物、硅氮化物、铪氧化物、硅氮氧化物、铝氧化物中的至少一种材料形成，所述栅极绝缘层的厚度范围为
Figure BDA00003031933300035
一种阵列基板，包括上述的薄膜晶体管。
优选的是，所述阵列基板中还包括钝化层，所述钝化层设置在所述源极层与所述漏极层的上方，所述钝化层对应着漏极层的区域开设有过孔，所述钝化层采用硅氧化物、硅氮化物、铪氧化物、铝氧化物中的至少两种材料形成，所述钝化层的厚度范围为
Figure BDA00003031933300037
优选的是，所述阵列基板中还包括像素电极层，所述像素电极层设置在所述钝化层上方，所述漏极层与所述像素电极层通过过孔连接，所述像素电极层采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种材料形成，所述像素电极层的厚度范围为
Figure BDA00003031933300038
一种显示装置，包括上述的阵列基板。
一种薄膜晶体管的制备方法，包括将所述源极层与所述漏极层形成在不同的层上且将栅极层与漏极层形成在同一层上的步骤。
优选的是，分别采用两次构图工艺在基板上形成包括栅极层、漏极层以及源极层的图形，其中一次构图工艺同时形成所述包括栅极层和所述漏极层的图形，另一次构图工艺形成所述包括源极层的图形。
进一步优选的是，该方法具体包括如下步骤：
步骤S1）：在基板上形成包括栅极层以及漏极层的图形，所述栅极层与所述漏极层之间开有间隙；
步骤S2）：在所述栅极层上形成包括栅极绝缘层的图形；
步骤S3）：在所述栅极绝缘层与部分所述漏极层上形成包括复合层的图形；
步骤S4）：在所述复合层上对应着所述栅极层的区域形成包括源极层的图形。
优选的是，所述步骤S1）具体为：在基板上形成电极金属膜，通过一次构图工艺形成包括栅极层和漏极层的图形。
优选的是，所述步骤S2）具体为：在完成步骤S1）的基板上形成栅极绝缘层膜，通过一次构图工艺在所述栅极层上形成包括栅极绝缘层的图形。
优选的是，所述步骤S3）具体为：在完成步骤S2）的基板上形成复合层膜，所述复合层膜包括有源层膜以及设置于所述有源层膜上方的欧姆接触层膜，通过一次构图工艺在在所述栅极绝缘层与部分所述漏极层上形成包括复合层的图形。
优选的是，所述步骤S3）具体为：在完成步骤S2）的基板上形成复合层，所述复合层包括有源层以及设置于所述有源层上方的刻蚀阻挡层，通过一次构图工艺在在所述栅极绝缘层与部分所述漏极层上形成包括复合层的图形。
优选的是，所述步骤S4）具体为：在完成步骤S3）的基板上形成电极金属膜，通过一次构图工艺在所述复合层上对应着所述栅极层的区域形成包括源极层图形。
一种阵列基板的制备方法，包括上述的薄膜晶体管的制备方法。
优选的是，还包括如下步骤：
步骤S5）：在所述源极层、未被所述源极层覆盖的部分复合层以及未被所述复合层覆盖的部分漏极层上形成包括钝化层的图形；
步骤S6）：在所述钝化层中形成过孔，在所述钝化层上方形成包括像素电极层的图形，所述漏极层与所述像素电极层通过过孔连接。
优选的是，所述步骤S5）具体为：在完成步骤S4）的基板上形成钝化层膜，通过一次构图工艺在所述源极层、未被所述源极层覆盖的部分复合层以及未被所述复合层覆盖的部分漏极层上形成包括钝化层以及过孔的图形。
优选的是，所述步骤S6）具体为：在完成步骤S5）的基板上形成透明导电膜，通过一次构图工艺在所述钝化层上方形成包括像素电极层的图形，所述漏极层与所述像素电极层通过过孔连接。
本发明的有益效果是：本发明中的薄膜晶体管通过将源极与漏极形成在不同的层上，在相应的薄膜晶体管或阵列基板的制备方法中，在源极与漏极之间不再需要通过刻蚀形成沟道的步骤，从而从根本上避免了阵列基板中源极与漏极发生桥连的问题，降低了因工艺问题造成的像素不良而导致的亮点，提高了显示装置的产品良率。
附图说明
图1A为现有技术中薄膜晶体管的剖视图；
图1B为现有技术中阵列基板的剖视图；
图2为本发明实施例1中阵列基板的剖视图；
图3为图2中阵列基板的制备流程图；
其中：
图3A、3a分别为形成栅极层和漏极层的剖视图与平面示意图；
图3B、3b分别为形成栅极绝缘层的剖视图与平面示意图；
图3C-3E、3e分别为形成源极层的剖视图与平面示意图；
图3F、3f分别为形成复合层的剖视图与平面示意图；
图3G、3g分别为形成钝化层和过孔的剖视图与平面示意图；
图3H、3h分别为形成像素电极层的剖视图与平面示意图；
图4为具有多个TFT阵列的阵列基板的平面示意图。
附图标记：1－基板；2－栅极层；3－漏极层；4-栅极绝缘层；5－复合层；50-复合层膜；6－源极层；60-电极金属膜；7－钝化层；8－像素电极层；9－过孔；21-栅极扫描线；61-数据线。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明薄膜晶体管、阵列基板、制备方法以及显示装置作进一步详细描述。
一种薄膜晶体管，包括基板以及设置于所述基板上的栅极层、源极层、漏极层，所述源极层与所述漏极层设置在不同的层上且所述漏极层与所述栅极层同层设置。
一种阵列基板，包括上述的薄膜晶体管。
一种显示装置，包括上述的阵列基板。
一种薄膜晶体管的制备方法，包括将所述源极层与所述漏极层形成在不同的层上且将栅极层与漏极层形成在同一层上的步骤。
一种阵列基板的制备方法，包括上述的薄膜晶体管的制备方法。
实施例1：
一种薄膜晶体管，包括基板以及设置于所述基板上的栅极层、源极层、漏极层，所述源极层与所述漏极层设置在不同的层上，且所述漏极层与所述栅极层同层设置。
一种阵列基板，包括上述的薄膜晶体管。
如图2所示，在薄膜晶体管中，所述漏极层3与所述栅极层2同层设置在所述基板1上，所述漏极层3与所述栅极层2之间开有间隙或沟槽；所述源极层6设置在所述栅极层2的上方，所述源极层6与所述栅极层2之间设置有栅极绝缘层4以及复合层5，所述栅极绝缘层4设置于所述栅极层2上方以及复合层5的下方，所述复合层5从所述栅极绝缘层4覆盖所述间隙或沟槽并部分延伸至所述漏极层3上方。
其中，所述栅极层2、源极层6和漏极层3均采用钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种材料形成，所述栅极层2、源极层6和漏极层3的厚度范围为
Figure BDA00003031933300071
在本实施例中，所述复合层5包括有源层以及设置于所述有源层上方的刻蚀阻挡层，所述有源层采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种材料形成，所述有源层的厚度范围为
Figure BDA00003031933300072
所述刻蚀阻挡层采用硅氧化物、硅氮化物、铪氧化物、铝氧化物中的至少两种材料形成，所述刻蚀阻挡层的厚度范围为
Figure BDA00003031933300073
所述栅极绝缘层4为单层、双层或多层，采用硅氧化物、硅氮化物、铪氧化物、硅氮氧化物、铝氧化物中的至少一种材料形成，所述栅极绝缘层4的厚度范围为
Figure BDA00003031933300074
本实施例中的阵列基板中包括上述的TFT，还包括钝化层7以及像素电极层8，所述钝化层7设置在所述源极层6与所述漏极层3的上方，所述钝化层7对应着漏极层3的区域开设有过孔9，所述钝化层7采用硅氧化物、硅氮化物、铪氧化物、铝氧化物中的至少两种材料形成，所述钝化层7的厚度范围为
Figure BDA00003031933300075
所述像素电极层8设置在所述钝化层7上方，所述漏极层3与所述像素电极层8通过过孔9连接，所述像素电极层8采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种材料形成，所述像素电极层8的厚度范围为
Figure BDA00003031933300076
相应的，上述薄膜晶体管的制备方法，包括将所述源极层6与所述漏极层3形成在不同的层上，并将所述栅极层2与所述漏极层3形成在同一层上的步骤；上述阵列基板的制备方法，除了上述薄膜晶体管的制备方法的步骤外，同时还包括形成所述钝化层7、所述过孔9以及将所述漏极层3与所述像素电极层8通过过孔9连接的步骤。
简单来说，薄膜晶体管的制备方法即分别采用两次构图工艺在基板1上形成包括栅极层2、漏极层3以及源极层6的图形，其中一次构图工艺同时形成包括所述栅极层2和所述漏极层3的图形，另一次构图工艺形成包括所述源极层6的图形。
在本发明中，构图工艺，可只包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
如图3所示，上述阵列基板的制备方法具体包括如下步骤（其中步骤S1）-步骤S5）即形成薄膜晶体管的步骤）：
步骤S1）：在基板1上形成包括栅极层2以及漏极层3的图形，所述栅极层2与所述漏极层3之间开有间隙或沟槽。
在该步骤中：先在基板1上形成电极金属膜，采用普通掩摸板通过一次构图工艺形成包括栅极层2、栅极扫描线21和漏极层3的图形，如图3A、3a所示。其中，采用沉积、溅射或热蒸发的方法在基板1上形成电极金属膜。
这里，为能更突出地示意本实施例中阵列基板在制备过程中的剖面结构，剖面图3A与平面图3a的比例设置为不同的比例；同时，为便于了解薄膜晶体管的各层结构以及各层之间的位置关系，平面图3a中的各层设置为具有一定透明度，以下各平面图与各剖面图与此同。
步骤S2）：在所述栅极层2上形成包括栅极绝缘层4的图形。
在该步骤中：在完成步骤S1）的基板1上形成栅极绝缘层膜（FGI Deposition），即在所述栅极层2上形成栅极绝缘层4，如图3B、3b所示。其中，形成栅极绝缘层膜可采用等离子体增强化学气相沉积法，栅极绝缘层4可利用普通掩模板通过一次光刻工艺形成。
步骤S3）：在所述栅极绝缘层4与部分所述漏极层3上形成包括复合层5的图形。
在该步骤中：在完成步骤S2）的基板1上形成复合层膜50，形成复合膜层可以采用沉积、溅射或热蒸发等方法，如图3C所示，所述复合层膜50包括有源层膜以及设置于所述有源层膜上方的刻蚀阻挡层膜（沉积过程中分别依次沉积），可利用普通掩模板通过一次构图工艺在所述栅极绝缘层4与部分所述漏极层3上形成包括复合层5的图形，如图3F、3f所示。当然，也可采用其他能够实现本结构的掩模板。
步骤S4）：在所述复合层5上对应着所述栅极层2的区域形成包括源极层6的图形。
在该步骤中：在完成步骤S3）的基板1上形成电极金属膜60，如图3D所示，可利用普通掩模板通过一次构图工艺在在所述复合层5上对应着所述栅极层2的区域形成包括源极层6和数据线61的图形，如图3E、3e所示。其中，采用沉积、溅射或热蒸发的方法在基板1上形成电极金属膜。当然，也可采用其他能够实现本结构的掩模板。
这里应该理解的是，为了简化工艺流程，在步骤S3）和步骤S4）中，实际可以采用先形成复合层膜50（如图3C所示），然后形成电极金属膜60（如图3D所示）；接着采用构图工艺先形成包括相对上层的源极层6和数据线61的图形（如图3E、3e所示），然后采用构图工艺再形成包括相对下层的复合层5的图形（如图3F、3f所示）的工艺流程，具体步骤这里不再详述。
至此，薄膜晶体管即制备完成，并预先形成了栅极扫描线21和数据线61，以方便阵列基板的布线。
步骤S5）：在所述源极层6、未被所述源极层6覆盖的部分复合层5以及未被所述复合层5覆盖的部分漏极层3上形成包括钝化层7以及过孔9的图形。
在该步骤中：在完成步骤S4）的基板1上形成钝化层膜（PVXDeposition），可利用普通掩模板通过一次构图工艺在所述源极层6、未被所述源极层6覆盖的部分复合层5以及未被所述复合层5覆盖的部分漏极层上形成包括钝化层7的图形，并采用刻蚀方式在所述钝化层7中形成包括过孔9的图形。其中，采用沉积、溅射或热蒸发的方法形成钝化层膜。当然，也可采用其他能够实现本结构的掩模板。
步骤S6）：在所述钝化层7上方形成包括像素电极层8的图形，所述漏极层3与所述像素电极层8通过所述过孔9连接。
在该步骤中，在完成步骤S5）的基板1上形成透明导电膜，可利用普通掩模板通过一次构图工艺在所述钝化层7上方形成包括像素电极层8的图形，所述漏极层3与所述像素电极层8通过过孔9连接；其中，采用沉积、溅射或热蒸发的方法形成透明导电膜。当然，也可采用其他能够实现本结构的掩模板。
本实施例中，薄膜晶体管中的有源层采用了金属氧化物半导体，例如氧化铟镓锌（IGZO）、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种材料形成，使得源极层与漏极层之间的电子迁移率增加，因此能获得较好的源极层与漏极层之间的电子迁移率。
一种显示装置，包括上述的阵列基板。如图4所示为具有多个阵列的阵列基板的平面示意图。
实施例2：
本实施例与实施例1的区别在于，本实施例薄膜晶体管以及相应的阵列基板中的有源层采用非晶硅材料形成。
在本实施例中，所述复合层包括有源层以及设置于所述有源层上方的欧姆接触层，所述有源层采用非晶硅材料形成，所述有源层的厚度范围为
Figure BDA00003031933300101
所述欧姆接触层采用掺杂磷元素的非晶硅材料形成，所述欧姆接触层的厚度范围为
Figure BDA00003031933300102
Figure BDA00003031933300103
本实施例中薄膜晶体管阵列基板的制备方法具体可参考实施例1。区别在于，所述步骤S3）具体为：在完成步骤S2）的基板上形成包括复合层的图形，所述复合层包括有源层以及设置于所述有源层上方的欧姆接触层（形成过程中分别依次沉积），利用普通掩模板通过一次构图工艺在所述栅极绝缘层与部分所述漏极层上形成复合层。
本实施例中，有源层采用了非晶硅材料形成，因此源极层与漏极层之间的电子迁移率相对实施例1较小。
实施例1、2的薄膜晶体管以及相应的阵列基板中，通过将源极与漏极形成在不同的层上（具体的是将漏极层与栅极层做在同一层，源极层与数据线做在同一层）。因此，在薄膜晶体管、阵列基板的制备方法中，在源极层与漏极层之间不再需要通过刻蚀形成沟道的步骤，从而从根本上避免了源极与漏极发生桥连的问题，降低了因工艺问题造成的像素不良而导致的亮点，提高了产品良率。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (22)

1.一种薄膜晶体管，包括基板以及设置于所述基板上的栅极层、源极层、漏极层，其特征在于，所述源极层与所述漏极层设置在不同的层上且所述漏极层与所述栅极层同层设置。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述漏极层与所述栅极层同层设置在所述基板上，所述漏极层与所述栅极层之间开有间隙或沟槽；所述源极层设置在所述栅极层的上方，所述源极层与所述栅极层之间设置有栅极绝缘层以及复合层，所述栅极绝缘层设置于所述栅极层上方以及复合层的下方，所述复合层从所述栅极绝缘层覆盖所述间隙或沟槽并部分延伸至所述漏极层上方。
3.根据权利要求2所述的薄膜晶体管，其特征在于，所述栅极层、源极层和漏极层均采用钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种材料形成，所述栅极层、源极层和漏极层的厚度范围为
Figure FDA00003031933200011
4.根据权利要求3所述的薄膜晶体管，其特征在于，所述复合层包括有源层以及设置于所述有源层上方的欧姆接触层，所述有源层采用非晶硅材料形成，所述有源层的厚度范围为
Figure FDA00003031933200012
Figure FDA00003031933200013
所述欧姆接触层采用掺杂磷元素的非晶硅材料形成，所述欧姆接触层的厚度范围为
Figure FDA00003031933200014
5.根据权利要求3所述的薄膜晶体管，其特征在于，所述复合层包括有源层以及设置于所述有源层上方的刻蚀阻挡层，所述有源层采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种材料形成，所述有源层的厚度范围为
Figure FDA00003031933200015
所述刻蚀阻挡层采用硅氧化物、硅氮化物、铪氧化物、铝氧化物中的至少两种材料形成，所述刻蚀阻挡层的厚度范围为
Figure FDA00003031933200021
Figure FDA00003031933200022
6.根据权利要求4或5所述的薄膜晶体管，其特征在于，所述栅极绝缘层为单层、双层或多层，采用硅氧化物、硅氮化物、铪氧化物、硅氮氧化物、铝氧化物中的至少一种材料形成，所述栅极绝缘层的厚度范围为
Figure FDA00003031933200023
7.一种阵列基板，其特征在于，包括权利要求1-6任一项所述的薄膜晶体管。
8.根据权利要求7所述的阵列基板，其特征在于，所述阵列基板中还包括钝化层，所述钝化层设置在所述源极层与所述漏极层的上方，所述钝化层对应着漏极层的区域开设有过孔，所述钝化层采用硅氧化物、硅氮化物、铪氧化物、铝氧化物中的至少两种材料形成，所述钝化层的厚度范围为
9.根据权利要求8所述的阵列基板，其特征在于，所述阵列基板中还包括像素电极层，所述像素电极层设置在所述钝化层上方，所述漏极层与所述像素电极层通过过孔连接，所述像素电极层采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一种材料形成，所述像素电极层的厚度范围为
Figure FDA00003031933200025
10.一种显示装置，其特征在于，包括权利要求7-10任一项所述的阵列基板。
11.一种薄膜晶体管的制备方法，其特征在于，包括将所述源极层与所述漏极层形成在不同的层上且将栅极层与漏极层形成在同一层上的步骤。
12.根据权利要求11所述的制备方法，其特征在于，分别采用两次构图工艺在基板上形成包括栅极层、漏极层以及源极层的图形，其中一次构图工艺同时形成所述包括栅极层和所述漏极层的图形，另一次构图工艺形成所述包括源极层的图形。
13.根据权利要求12所述的制备方法，其特征在于，该方法具体包括如下步骤：
步骤S1）：在基板上形成包括栅极层以及漏极层的图形，所述栅极层与所述漏极层之间开有间隙或沟槽；
步骤S2）：在所述栅极层上形成包括栅极绝缘层的图形；
步骤S3）：在所述栅极绝缘层与部分所述漏极层上形成包括复合层的图形；
步骤S4）：在所述复合层上对应着所述栅极层的区域形成包括源极层的图形。
14.根据权利要求13所述的制备方法，其特征在于，所述步骤S1）具体为：在基板上形成电极金属膜，通过一次构图工艺形成包括栅极层和漏极层的图形。
15.根据权利要求14所述的制备方法，其特征在于，所述步骤S2）具体为：在完成步骤S1）的基板上形成栅极绝缘层膜，通过一次构图工艺在所述栅极层上形成包括栅极绝缘层的图形。
16.根据权利要求15所述的制备方法，其特征在于，所述步骤S3）具体为：在完成步骤S2）的基板上形成复合层膜，所述复合层膜包括有源层膜以及设置于所述有源层膜上方的欧姆接触层膜，通过一次构图工艺在在所述栅极绝缘层与部分所述漏极层上形成包括复合层的图形。
17.根据权利要求15所述的制备方法，其特征在于，所述步骤S3）具体为：在完成步骤S2）的基板上形成复合层，所述复合层包括有源层以及设置于所述有源层上方的刻蚀阻挡层，通过一次构图工艺在在所述栅极绝缘层与部分所述漏极层上形成包括复合层的图形。
18.根据权利要求16或17所述的制备方法，其特征在于，所述步骤S4）具体为：在完成步骤S3）的基板上形成电极金属膜，通过一次构图工艺在所述复合层上对应着所述栅极层的区域形成包括源极层图形。
19.一种阵列基板的制备方法，其特征在于，包括权利要求11-18任一所述的薄膜晶体管的制备方法。
20.根据权利要求19所述的制备方法，其特征在于，还包括：
步骤S5）：在所述源极层、未被所述源极层覆盖的部分复合层以及未被所述复合层覆盖的部分漏极层上形成包括钝化层的图形；
步骤S6）：在所述钝化层中形成过孔，在所述钝化层上方形成包括像素电极层的图形，所述漏极层与所述像素电极层通过过孔连接。
21.根据权利要求20所述的制备方法，其特征在于，所述步骤S5）具体为：在完成步骤S4）的基板上形成钝化层膜，通过一次构图工艺在所述源极层、未被所述源极层覆盖的部分复合层以及未被所述复合层覆盖的部分漏极层上形成包括钝化层以及过孔的图形。
22.根据权利要求21所述的制备方法，其特征在于，所述步骤S6）具体为：在完成步骤S5）的基板上形成透明导电膜，通过一次构图工艺在所述钝化层上方形成包括像素电极层的图形，所述漏极层与所述像素电极层通过过孔连接。
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