WO2018107524A1 - Tft背板及其制作方法 - Google Patents

Tft背板及其制作方法 Download PDF

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Publication number
WO2018107524A1
WO2018107524A1 PCT/CN2016/112525 CN2016112525W WO2018107524A1 WO 2018107524 A1 WO2018107524 A1 WO 2018107524A1 CN 2016112525 W CN2016112525 W CN 2016112525W WO 2018107524 A1 WO2018107524 A1 WO 2018107524A1
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layer
forming
drain
pixel defining
anode
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PCT/CN2016/112525
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English (en)
French (fr)
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陈哲
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武汉华星光电技术有限公司
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Priority to US15/505,110 priority Critical patent/US20180226508A1/en
Publication of WO2018107524A1 publication Critical patent/WO2018107524A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT backplane and a method of fabricating the same.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the working temperature has wide adaptability, light volume, fast response, easy to realize color display and large screen display, easy to realize integration with integrated circuit driver, easy to realize flexible display, and the like, and thus has broad application prospects.
  • the OLED generally includes a substrate, an anode provided on the substrate, a hole injection layer provided on the anode, a hole transport layer provided on the hole injection layer, a light-emitting layer provided on the hole transport layer, and a light-emitting layer.
  • the principle of OLED illumination is that the semiconductor material and the organic luminescent material are driven by an electric field, causing luminescence by carrier injection and recombination.
  • the OLED generally adopts an ITO (Indium Tin Oxide) electrode and a metal electrode as anodes and cathodes of the device, respectively.
  • ITO Indium Tin Oxide
  • electrons and holes are injected from the cathode and the anode to the electron transport layer and the hole transport layer, respectively.
  • the electrons and holes migrate to the light-emitting layer through the electron transport layer and the hole transport layer, respectively, and meet in the light-emitting layer to form excitons and excite the light-emitting molecules, and the latter emits visible light through radiation relaxation.
  • OLEDs can be classified into passive matrix OLED (PM OLED) and active matrix OLED (AMOLED).
  • PM OLED passive matrix OLED
  • AMOLED active matrix OLED
  • PMOLED is light-emitting when data is written, and does not emit light when data is not written.
  • This driving method is simple in structure, low in cost, and easy to design, and is mainly suitable for small and medium-sized displays.
  • the biggest difference between AMOLED and PMOLED is that each pixel has a capacitor to store data, so that each pixel is kept in the light state. Since the power consumption of AMOLED is significantly smaller than that of PMOLED, and its driving method is suitable for developing large-size and high-resolution displays, AMOLED has become the main direction of future development.
  • oxide TFT Thin Film Transistor
  • low temperature polysilicon TFT backplane The main difference between the two backplane technologies is the design of TFT. Different from the structure, the low-temperature polysilicon TFT has many manufacturing processes and complicated processes, which makes the oxide TFT backplane become the mainstream development direction.
  • the TFT backplane includes a base substrate 100, a gate electrode 110, a gate insulating layer 200, an oxide semiconductor layer 300, an etch stop layer 400, a source 510 and a drain 520, and passivation which are sequentially stacked from bottom to top.
  • the pixel defining layer 800 and the supporting layer 900 need to use a mask plate and are each fabricated by a yellow light process, so that the production cost is high and the processing time is long; Since the support layer 900 and the pixel defining layer 800 are separately formed, the adhesion between the supporting layer 900 and the pixel defining layer 800 is poor, and the supporting layer 900 is easily damaged and falls off in the post process. This is not conducive to the protection of the support layer 900, and also causes the display quality of the display to be degraded because the support layer 900 falls off to the display area.
  • An object of the present invention is to provide a method for fabricating a TFT backplane, which can effectively save the cost of the fixture and the production cost, and can prevent the support layer from falling off and effectively improve the display quality of the display.
  • Another object of the present invention is to provide a TFT backplane, which is simple in process, low in production cost, and can prevent the support layer from falling off, thereby effectively improving the display quality of the display.
  • the present invention provides a method for fabricating a TFT backplane, including the following steps:
  • Step 1 providing a substrate, forming a gate on the substrate, and forming a gate insulating layer on the gate and the substrate;
  • Step 2 forming an active layer corresponding to the gate on the gate insulating layer, forming an etch barrier layer on the active layer and the gate insulating layer, on the etch barrier layer Forming first and second through holes respectively corresponding to both ends of the active layer;
  • Step 3 forming a passivation layer on the source, drain and etch barrier layer, forming a planar layer on the passivation layer;
  • Step 4 forming an organic photoresist layer on the anode and the flat layer, exposing and developing the organic photoresist layer by using a halftone mask, and simultaneously obtaining a pixel defining layer and being disposed on the pixel defining layer Supporting layer, the pixel defining layer is provided with an opening corresponding to the upper portion of the anode,
  • the support layer includes a plurality of supports disposed at intervals.
  • the halftone mask includes a total transmission area corresponding to the opening, a non-transmission area corresponding to the support layer, and a pixel corresponding to the pixel definition layer except the opening and a semi-transmissive region of the region other than the region covered by the support layer.
  • the light transmittance of the total transmission region is 100%, the light transmittance of the semi-transmissive region is 50%, and the light transmittance of the non-transmissive region is 0%.
  • the material of the active layer is an oxide semiconductor.
  • the oxide semiconductor is indium gallium zinc oxide.
  • the shape of the support is columnar.
  • the present invention also provides a TFT backplane, including: a substrate, a gate disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and the gate is disposed on the gate And an etch stop layer disposed on the active layer and the gate insulating layer, a source and a drain provided on the etch stop layer a passivation layer disposed on the source, the drain and the etch stop layer, a flat layer disposed on the passivation layer, an anode disposed on the flat layer, and disposed on the anode a pixel defining layer on the flat layer, and a supporting layer disposed on the pixel defining layer;
  • the etch barrier layer is provided with a first via hole and a second via hole respectively corresponding to both ends of the active layer, and the source and the drain are respectively connected via the first via hole and the second via hole Both ends of the active layer are in contact;
  • the passivation layer and the flat layer are provided with a third through hole corresponding to the upper side of the drain, and the anode is in contact with the drain via the third through hole;
  • the pixel defining layer is provided with an opening corresponding to the upper portion of the anode, and the supporting layer comprises a plurality of supports arranged at intervals;
  • the pixel defining layer is integral with the supporting layer and has the same material.
  • the material of the active layer is an oxide semiconductor.
  • the oxide semiconductor is indium gallium zinc oxide.
  • the shape of the support is columnar.
  • the invention also provides a method for fabricating a TFT backplane, comprising the following steps:
  • Step 1 providing a substrate, forming a gate on the substrate, and forming a gate insulating layer on the gate and the substrate;
  • Step 2 forming an active layer corresponding to the gate on the gate insulating layer, forming an etch barrier layer on the active layer and the gate insulating layer, on the etch barrier layer Forming first and second through holes respectively corresponding to both ends of the active layer;
  • Step 3 forming a passivation layer on the source, drain and etch barrier layer, forming a planar layer on the passivation layer;
  • Step 4 forming an organic photoresist layer on the anode and the flat layer, exposing and developing the organic photoresist layer by using a halftone mask, and simultaneously obtaining a pixel defining layer and being disposed on the pixel defining layer Supporting layer, the pixel defining layer is provided with an opening corresponding to the upper portion of the anode, and the supporting layer comprises a plurality of supports arranged at intervals;
  • the material of the active layer is an oxide semiconductor
  • the shape of the support is columnar.
  • the present invention provides a method for fabricating a TFT backplane, which uses a halftone mask having three light transmittances to perform a yellow light process on the organic photoresist layer, and a yellow light process can be used.
  • the three exposure effects are realized, thereby simultaneously forming the pixel definition layer, the opening on the pixel definition layer, and the support layer.
  • the invention saves a mask plate and a yellow light process, and can effectively save the fixture. Cost and production cost; at the same time, the support layer and the pixel defining layer are integrated as a whole, which can avoid the falling off of the supporting layer and effectively improve the display quality of the display.
  • the invention provides a TFT backplane, wherein the pixel defining layer and the supporting layer are formed in the same process, the process is simple, the production cost is low, and since the pixel defining layer and the supporting layer are integrated, the support layer falling off can be avoided.
  • the problem is to effectively improve the display quality of the display.
  • FIG. 1 is a schematic structural view of a conventional oxide TFT backplane
  • FIG. 2 is a flow chart of a method for fabricating a TFT backplane of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT backplane according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a TFT backplane according to the present invention.
  • FIG. 6 to FIG. 7 are schematic diagrams showing the step 4 of the method for fabricating the TFT backplane of the present invention.
  • FIG. 8 is a schematic structural view of a TFT backplane of the present invention.
  • the present invention first provides a method for fabricating a TFT backplane, including the following steps:
  • Step 1 as shown in FIG. 3, a base substrate 10 is provided, a gate electrode 11 is formed on the base substrate 10, and a gate insulating layer 20 is formed on the gate electrode 11 and the base substrate 10.
  • the base substrate 10 is a glass substrate.
  • the material of the gate electrode 11 includes one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and chromium (Cr).
  • Mo molybdenum
  • Al aluminum
  • Cu copper
  • Ti titanium
  • Cr chromium
  • the material of the gate insulating layer 20 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • Step 2 As shown in FIG. 4, an active layer 30 corresponding to the upper surface of the gate electrode 11 is formed on the gate insulating layer 20, and etching is formed on the active layer 30 and the gate insulating layer 20. a barrier layer 40, on the etch stop layer 40, respectively, corresponding to the first through hole 41 and the second through hole 42 of the active layer 30;
  • a source 51 and a drain 52 are formed on the etch barrier layer 40, and the source 51 and the drain 52 are connected to the active layer 30 via the first via hole 41 and the second via hole 42, respectively. Both ends are in contact.
  • the material of the active layer 30 is an oxide semiconductor.
  • the oxide semiconductor is indium gallium zinc oxide (IGZO).
  • the material of the etch barrier layer 40 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the material of the source 51 and the drain 52 includes one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and chromium (Cr).
  • Mo molybdenum
  • Al aluminum
  • Cu copper
  • Ti titanium
  • Cr chromium
  • the etch stop layer 40 can protect the active layer 30 from corrosion by the etchant during the etching process of the source 51 and the drain 52.
  • Step 3 as shown in FIG. 5, a passivation layer 45 is formed on the source 51, the drain 52 and the etch stop layer 40, and a flat layer 50 is formed on the passivation layer 45;
  • An anode 60 is formed on the flat layer 50, and the anode 60 is via the third through hole 53 The drains 52 are in contact.
  • the material of the passivation layer 45 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the flat layer 50 is an organic photoresist material.
  • the anode 60 includes two transparent conductive metal oxide layers and a metal layer interposed between the two transparent conductive metal oxide layers.
  • the transparent conductive metal oxide layer is made of indium tin oxide ( ITO), the material of the metal layer is silver.
  • Step 4 as shown in FIG. 6-7, an organic photoresist layer 70 is formed on the anode 60 and the flat layer 50, and the organic photoresist layer 70 is formed by a half tone mask 75.
  • the supporting layer 90 includes a plurality of supports 91 spaced apart.
  • the opening 85 is used to form a luminescent pixel region of the OLED, and an OLED luminescent layer and a cathode are vapor-deposited in the opening 85 in a subsequent process.
  • the shape of the support 91 is a column shape
  • the support layer 90 is used to support the mask for vapor deposition in the subsequent evaporation process of the OLED light-emitting layer and the cathode.
  • the halftone mask 75 includes a total transmission area 751 corresponding to the opening 85, a non-transmission area 752 corresponding to the support layer 90, and a pixel definition corresponding thereto.
  • the organic photoresist layer 70 is subjected to a yellow light (exposure and development) process by using a halftone mask 75 having three light transmittances, and three exposures can be realized by a yellow light process.
  • the effect is to form the pixel defining layer 80, the opening 85 on the pixel defining layer 80, and the supporting layer 90 at the same time.
  • the invention saves a mask and a yellow light process, and can effectively save the fixture. Cost and production cost; at the same time, the support layer 90 and the pixel defining layer 80 are integrally formed in the structure, so that the support layer 90 can be prevented from falling off, and the display quality of the display is effectively improved.
  • the manufacturing method of the TFT backplane of the present invention can be completed by using a conventional TFT process, and it is not necessary to modify the existing machine configuration.
  • the present invention further provides a TFT backplane, including: a substrate substrate 10, a gate electrode 11 disposed on the substrate substrate 10, and a gate electrode disposed on the gate substrate a gate insulating layer 20 on the electrode 11 and the base substrate 10, an active layer 30 disposed on the gate insulating layer 20 and corresponding to the gate electrode 11, and a gate layer and a gate provided on the active layer 30 Polar insulating layer 20
  • the etch barrier layer 40 is provided with a first through hole 41 and a second through hole 42 respectively corresponding to the two ends of the active layer 30, and the source 51 and the drain 52 respectively pass through the first through hole 41 and the second via hole 42 are in contact with both ends of the active layer 30;
  • the passivation layer 45 and the flat layer 50 are provided with a third through hole 53 corresponding to the upper surface of the drain electrode 52, and the anode 60 is in contact with the drain electrode 52 via the third through hole 53;
  • the pixel defining layer 80 is provided with an opening 85 corresponding to the upper portion of the anode 60, the supporting layer 90 includes a plurality of supports 91 arranged at intervals;
  • the pixel defining layer 80 is integral with the support layer 90 and has the same material.
  • the base substrate 10 is a glass substrate.
  • the material of the gate 11, the source 51 and the drain 52 includes one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and chromium (Cr). .
  • the gate insulating layer 20, etch stop layer 40, and the material of the passivation layer 45 includes one or more of silicon oxide (SiO x) and silicon nitride (SiN x) of.
  • the material of the active layer 30 is an oxide semiconductor.
  • the oxide semiconductor is indium gallium zinc oxide (IGZO).
  • the flat layer 50 is an organic photoresist material.
  • the anode 60 includes two transparent conductive metal oxide layers and a metal layer interposed between the two transparent conductive metal oxide layers; preferably, the transparent conductive metal oxide layer is made of indium tin oxide ( ITO), the material of the metal layer is silver.
  • ITO indium tin oxide
  • the shape of the support 91 is columnar.
  • the TFT backplane, the pixel defining layer 80 and the supporting layer 90 are formed in the same process, the process is simple, the production cost is low, and since the pixel defining layer 80 and the supporting layer 90 are integrated, the support layer 90 can be prevented from falling off. The problem is to effectively improve the display quality of the display.
  • the present invention provides a TFT backplane and a method of fabricating the same.
  • the organic photoresist layer is subjected to a yellow light process by using a halftone mask having three light transmittances, and three exposure effects can be realized by a yellow light process, thereby simultaneously forming
  • the pixel defining layer, the opening on the pixel defining layer, and the supporting layer compared with the prior art, the invention saves a mask plate and a yellow light process, which can effectively save the fixture cost and the production cost; meanwhile, in the structure
  • the support layer and the pixel defining layer are integrated as a whole, which can prevent the supporting layer from falling off and effectively improve the display quality of the display.
  • the pixel defining layer and the supporting layer are in the same
  • the process is simple, the production cost is low, and since the pixel defining layer and the supporting layer are integrated, the problem of the supporting layer falling off can be avoided, thereby effectively improving the display quality of the display.

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Abstract

一种TFT背板及其制作方法，在TFT背板的制作方法中，利用具有三种光线穿透率的半色调掩膜板（75）对有机光阻层（70）进行黄光制程，通过一道黄光工序即可实现三种曝光效果，从而同时形成像素定义层（80）、像素定义层（80）上的开口（85）、及支撑层（90），与现有技术相比，节约了一道掩膜板与一道黄光工序，可有效节省治具成本和生产成本；同时，在结构上支撑层（90）与像素定义层（80）为一个整体，可避免支撑层（90）脱落，有效提高显示器的显示品质。在TFT背板中，像素定义层（80）与支撑层（90）在同一个制程中制得，制程简单，生产成本低，且由于像素定义层（80）与支撑层（90）为一个整体，可避免出现支撑层（90）脱落的问题，从而有效提高显示器的显示品质。

Description

TFT背板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT背板及其制作方法。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED通常包括：基板、设于基板上的阳极、设于阳极上的空穴注入层、设于空穴注入层上的空穴传输层、设于空穴传输层上的发光层、设于发光层上的电子传输层、设于电子传输层上的电子注入层及设于电子注入层上的阴极。OLED的发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致发光。具体的，OLED通常采用ITO(氧化铟锡)电极和金属电极分别作为器件的阳极和阴极，在一定电压驱动下，电子和空穴分别从阴极和阳极注入到电子传输层和空穴传输层，电子和空穴分别经过电子传输层和空穴传输层迁移到发光层，并在发光层中相遇，形成激子并使发光分子激发，后者经过辐射弛豫而发出可见光。
OLED依驱动方式可分为被动式矩阵驱动OLED(Passive Matrix OLED，PMOLED)和主动式矩阵驱动OLED(Active Matrix OLED，AMOLED)两种。其中，PMOLED是当数据写入时发光，数据未写入时不发光，这种驱动方式结构简单、成本较低、较容易设计，主要适用于中小尺寸的显示器。AMOLED与PMOLED最大的差异在于：每一个像素都有一个电容存储数据，让每一像素皆维持在发光状态。由于AMOLED的耗电量明显小于PMOLED，加上其驱动方式适合发展大尺寸与高解析度的显示器，使得AMOLED成为未来发展的主要方向。目前公认的能应用于AMOLED背板驱动的主流技术有两个：氧化物TFT(Thin Film Transistor，薄膜晶体管)背板和低温多晶硅TFT背板，这两种背板技术的主要区别在于TFT的设计与结构差异，其中低温多晶硅TFT的制程工序较多，工艺也较复杂，使得氧化物TFT背板成为目前主流的发展方向。
图1为现有的氧化物TFT背板的结构示意图，如图1所示，所述氧化 物TFT背板包括从下到上依次层叠设置的衬底基板100、栅极110、栅极绝缘层200、氧化物半导体层300、刻蚀阻挡层400、源极510和漏极520、钝化层450、平坦层500、阳极600、像素定义层800及支撑层900；其中，所述支撑层900包括间隔设置的数个支撑物910，所述支撑物910为具有一定高度的柱体。
上述氧化物TFT背板的制程中，所述像素定义层800与支撑层900需要各自使用一道掩膜板并且各自通过一道黄光工序来制作，因此生产成本较高，制程时间较长；并且，由于所述支撑层900与像素定义层800是分开制作的，因此所述支撑层900与像素定义层800之间的附着性较差，在后制程中所述支撑层900极易受到损伤而脱落，这样既不利于支撑层900的保护，也会因为支撑层900脱落到显示区造成显示器的显示品质下降。
发明内容
本发明的目的在于提供一种TFT背板的制作方法，能够有效节省治具成本和生产成本，同时可避免支撑层脱落，有效提高显示器的显示品质。
本发明的目的还在于提供一种TFT背板，制程简单，生产成本低，并且可避免支撑层脱落，从而有效提高显示器的显示品质。
为实现上述目的，本发明提供一种TFT背板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上形成栅极，在所述栅极与衬底基板上形成栅极绝缘层；
步骤2、在所述栅极绝缘层上形成对应于所述栅极上方的有源层，在所述有源层与栅极绝缘层上形成刻蚀阻挡层，在所述刻蚀阻挡层上形成分别对应于所述有源层两端的第一通孔和第二通孔；
在所述刻蚀阻挡层上形成源极和漏极，所述源极和漏极分别经由所述第一通孔和第二通孔与所述有源层的两端相接触；
步骤3、在所述源极、漏极与刻蚀阻挡层上形成钝化层，在所述钝化层上形成平坦层；
在所述钝化层与平坦层上形成对应于所述漏极上方的第三通孔；
在所述平坦层上形成阳极，所述阳极经由所述第三通孔与所述漏极相接触；
步骤4、在所述阳极与平坦层上形成一有机光阻层，采用一半色调掩膜板对所述有机光阻层进行曝光、显影，同时得到像素定义层与设于所述像素定义层上的支撑层，所述像素定义层上设有对应于所述阳极上方的开口， 所述支撑层包括间隔设置的数个支撑物。
所述步骤4中，所述半色调掩膜板包括对应于所述开口的全透射区域、对应于所述支撑层的非透射区域、以及对应于所述像素定义层上除所述开口以及被所述支撑层覆盖的区域以外的其它区域的半透射区域。
所述全透射区域的光线穿透率为100％，所述半透射区域的光线穿透率为50％，所述非透射区域的光线穿透率为0％。
所述有源层的材料为氧化物半导体。
所述氧化物半导体为铟镓锌氧化物。
所述支撑物的形状为柱状。
本发明还提供一种TFT背板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极与衬底基板上的栅极绝缘层、设于所述栅极绝缘层上且对应于所述栅极上方的有源层、设于所述有源层与栅极绝缘层上的刻蚀阻挡层、设于所述刻蚀阻挡层上的源极和漏极、设于所述源极、漏极与刻蚀阻挡层上的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的阳极、设于所述阳极与平坦层上的像素定义层、以及设于所述像素定义层上的支撑层；
所述刻蚀阻挡层上设有分别对应于所述有源层两端的第一通孔和第二通孔，所述源极和漏极分别经由所述第一通孔和第二通孔与所述有源层的两端相接触；
所述钝化层与平坦层上设有对应于所述漏极上方的第三通孔，所述阳极经由所述第三通孔与所述漏极相接触；
所述像素定义层上设有对应于所述阳极上方的开口，所述支撑层包括间隔设置的数个支撑物；
所述像素定义层与支撑层为一个整体，且材料相同。
所述有源层的材料为氧化物半导体。
所述氧化物半导体为铟镓锌氧化物。
所述支撑物的形状为柱状。
本发明还提供一种TFT背板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上形成栅极，在所述栅极与衬底基板上形成栅极绝缘层；
步骤2、在所述栅极绝缘层上形成对应于所述栅极上方的有源层，在所述有源层与栅极绝缘层上形成刻蚀阻挡层，在所述刻蚀阻挡层上形成分别对应于所述有源层两端的第一通孔和第二通孔；
在所述刻蚀阻挡层上形成源极和漏极，所述源极和漏极分别经由所述 第一通孔和第二通孔与所述有源层的两端相接触；
步骤3、在所述源极、漏极与刻蚀阻挡层上形成钝化层，在所述钝化层上形成平坦层；
在所述钝化层与平坦层上形成对应于所述漏极上方的第三通孔；
在所述平坦层上形成阳极，所述阳极经由所述第三通孔与所述漏极相接触；
步骤4、在所述阳极与平坦层上形成一有机光阻层，采用一半色调掩膜板对所述有机光阻层进行曝光、显影，同时得到像素定义层与设于所述像素定义层上的支撑层，所述像素定义层上设有对应于所述阳极上方的开口，所述支撑层包括间隔设置的数个支撑物；
其中，所述有源层的材料为氧化物半导体；
其中，所述支撑物的形状为柱状。
本发明的有益效果：本发明提供的一种TFT背板的制作方法，利用具有三种光线穿透率的半色调掩膜板对有机光阻层进行黄光制程，通过一道黄光工序即可实现三种曝光效果，从而同时形成像素定义层、像素定义层上的开口、及支撑层，与现有技术相比，本发明节约了一道掩膜板与一道黄光工序，可有效节省治具成本和生产成本；同时，在结构上所述支撑层与像素定义层为一个整体，可避免支撑层脱落，有效提高显示器的显示品质。本发明提供的一种TFT背板，像素定义层与支撑层在同一个制程中制得，制程简单，生产成本低，且由于像素定义层与支撑层为一个整体，可避免出现支撑层脱落的问题，从而有效提高显示器的显示品质。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的氧化物TFT背板的结构示意图；
图2为本发明的TFT背板的制作方法的流程图；
图3为本发明的TFT背板的制作方法的步骤1的示意图；
图4为本发明的TFT背板的制作方法的步骤2的示意图；
图5为本发明的TFT背板的制作方法的步骤3的示意图；
图6-图7为本发明的TFT背板的制作方法的步骤4的示意图；
图8为本发明的TFT背板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种TFT背板的制作方法，包括如下步骤：
步骤1、如图3所示，提供一衬底基板10，在所述衬底基板10上形成栅极11，在所述栅极11与衬底基板10上形成栅极绝缘层20。
具体的，所述衬底基板10为玻璃基板。
具体的，所述栅极11的材料包括钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)、铬(Cr)中的一种或多种。
具体的，所述栅极绝缘层20的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种。
步骤2、如图4所示，在所述栅极绝缘层20上形成对应于所述栅极11上方的有源层30，在所述有源层30与栅极绝缘层20上形成刻蚀阻挡层40，在所述刻蚀阻挡层40上形成分别对应于所述有源层30两端的第一通孔41和第二通孔42；
在所述刻蚀阻挡层40上形成源极51和漏极52，所述源极51和漏极52分别经由所述第一通孔41和第二通孔42与所述有源层30的两端相接触。
具体的，所述有源层30的材料为氧化物半导体，优选的，所述氧化物半导体为铟镓锌氧化物(IGZO)。
具体的，所述刻蚀阻挡层40的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种。
具体的，所述源极51和漏极52的材料包括钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)、铬(Cr)中的一种或多种。
具体的，所述刻蚀阻挡层40能够在所述源极51和漏极52的蚀刻制程中保护所述有源层30不受到蚀刻液的腐蚀。
步骤3、如图5所示，在所述源极51、漏极52与刻蚀阻挡层40上形成钝化层45，在所述钝化层45上形成平坦层50；
在所述钝化层45与平坦层50上形成对应于所述漏极52上方的第三通孔53；
在所述平坦层50上形成阳极60，所述阳极60经由所述第三通孔53与 所述漏极52相接触。
具体的，所述钝化层45的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种。
具体的，所述平坦层50为有机光阻材料。
具体的，所述阳极60包括两透明导电金属氧化物层与夹设于两透明导电金属氧化物层之间的金属层，优选的，所述透明导电金属氧化物层的材料为氧化铟锡(ITO)，所述金属层的材料为银。
步骤4、如图6-图7所示，在所述阳极60与平坦层50上形成一有机光阻层70，采用一半色调掩膜板(Half Tone Mask)75对所述有机光阻层70进行曝光、显影，同时得到像素定义层80与设于所述像素定义层80上的支撑层90，所述像素定义层80上设有对应于所述阳极60上方的开口85，所述支撑层90包括间隔设置的数个支撑物91。
具体的，所述开口85用于形成OLED的发光像素区域，后续制程中会在该开口85内蒸镀形成OLED发光层及阴极。
具体的，所述支撑物91的形状为柱状，所述支撑层90用于在后续的OLED发光层及阴极的蒸镀制程中支撑蒸镀用掩膜板。
具体的，所述步骤4中，所述半色调掩膜板75包括对应于所述开口85的全透射区域751、对应于所述支撑层90的非透射区域752、以及对应于所述像素定义层80上除所述开口85以及被所述支撑层90覆盖的区域以外的其它区域的半透射区域753；所述全透射区域751的光线穿透率为100％，所述半透射区域753的光线穿透率为50％，所述非透射区域752的光线穿透率为0％。
上述TFT背板的制作方法，利用具有三种光线穿透率的半色调掩膜板75对有机光阻层70进行黄光(曝光及显影)制程，通过一道黄光工序即可实现三种曝光效果，从而同时形成像素定义层80、像素定义层80上的开口85、及支撑层90，与现有技术相比，本发明节约了一道掩膜板与一道黄光工序，可有效节省治具成本和生产成本；同时，在结构上所述支撑层90与像素定义层80为一个整体，可避免支撑层90脱落，有效提高显示器的显示品质。另外，本发明的TFT背板的制作方法利用传统的TFT工艺即可完成，勿需改造现有的机台配置。
请参阅图8，基于上述TFT背板的制作方法，本发明还提供一种TFT背板，包括：衬底基板10、设于所述衬底基板10上的栅极11、设于所述栅极11与衬底基板10上的栅极绝缘层20、设于所述栅极绝缘层20上且对应于所述栅极11上方的有源层30、设于所述有源层30与栅极绝缘层20上 的刻蚀阻挡层40、设于所述刻蚀阻挡层40上的源极51和漏极52、设于所述源极51、漏极52与刻蚀阻挡层40上的钝化层45、设于所述钝化层45上的平坦层50、设于所述平坦层50上的阳极60、设于所述阳极60与平坦层50上的像素定义层80、以及设于所述像素定义层80上的支撑层90；
所述刻蚀阻挡层40上设有分别对应于所述有源层30两端的第一通孔41和第二通孔42，所述源极51和漏极52分别经由所述第一通孔41和第二通孔42与所述有源层30的两端相接触；
所述钝化层45与平坦层50上设有对应于所述漏极52上方的第三通孔53，所述阳极60经由所述第三通孔53与所述漏极52相接触；
所述像素定义层80上设有对应于所述阳极60上方的开口85，所述支撑层90包括间隔设置的数个支撑物91；
所述像素定义层80与支撑层90为一个整体，且材料相同。
具体的，所述衬底基板10为玻璃基板。
具体的，所述栅极11、源极51和漏极52的材料包括钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)、铬(Cr)中的一种或多种。
具体的，所述栅极绝缘层20、刻蚀阻挡层40、及钝化层45的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种。
具体的，所述有源层30的材料为氧化物半导体，优选的，所述氧化物半导体为铟镓锌氧化物(IGZO)。
具体的，所述平坦层50为有机光阻材料。
具体的，所述阳极60包括两透明导电金属氧化物层与夹设于两透明导电金属氧化物层之间的金属层；优选的，所述透明导电金属氧化物层的材料为氧化铟锡(ITO)，所述金属层的材料为银。
具体的，所述支撑物91的形状为柱状。
上述TFT背板，像素定义层80与支撑层90在同一个制程中制得，制程简单，生产成本低，且由于像素定义层80与支撑层90为一个整体，可避免出现支撑层90脱落的问题，从而有效提高显示器的显示品质。
综上所述，本发明提供一种TFT背板及其制作方法。本发明的TFT背板的制作方法，利用具有三种光线穿透率的半色调掩膜板对有机光阻层进行黄光制程，通过一道黄光工序即可实现三种曝光效果，从而同时形成像素定义层、像素定义层上的开口、及支撑层，与现有技术相比，本发明节约了一道掩膜板与一道黄光工序，可有效节省治具成本和生产成本；同时，在结构上所述支撑层与像素定义层为一个整体，可避免支撑层脱落，有效提高显示器的显示品质。本发明的TFT背板，像素定义层与支撑层在同一 个制程中制得，制程简单，生产成本低，且由于像素定义层与支撑层为一个整体，可避免出现支撑层脱落的问题，从而有效提高显示器的显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种TFT背板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上形成栅极，在所述栅极与衬底基板上形成栅极绝缘层；
    步骤2、在所述栅极绝缘层上形成对应于所述栅极上方的有源层，在所述有源层与栅极绝缘层上形成刻蚀阻挡层，在所述刻蚀阻挡层上形成分别对应于所述有源层两端的第一通孔和第二通孔；
    在所述刻蚀阻挡层上形成源极和漏极，所述源极和漏极分别经由所述第一通孔和第二通孔与所述有源层的两端相接触；
    步骤3、在所述源极、漏极与刻蚀阻挡层上形成钝化层，在所述钝化层上形成平坦层；
    在所述钝化层与平坦层上形成对应于所述漏极上方的第三通孔；
    在所述平坦层上形成阳极，所述阳极经由所述第三通孔与所述漏极相接触；
    步骤4、在所述阳极与平坦层上形成一有机光阻层，采用一半色调掩膜板对所述有机光阻层进行曝光、显影，同时得到像素定义层与设于所述像素定义层上的支撑层，所述像素定义层上设有对应于所述阳极上方的开口，所述支撑层包括间隔设置的数个支撑物。
  2. 如权利要求1所述的TFT背板的制作方法，其中，所述步骤4中，所述半色调掩膜板包括对应于所述开口的全透射区域、对应于所述支撑层的非透射区域、以及对应于所述像素定义层上除所述开口以及被所述支撑层覆盖的区域以外的其它区域的半透射区域。
  3. 如权利要求2所述的TFT背板的制作方法，其中，所述全透射区域的光线穿透率为100％，所述半透射区域的光线穿透率为50％，所述非透射区域的光线穿透率为0％。
  4. 如权利要求1所述的TFT背板的制作方法，其中，所述有源层的材料为氧化物半导体。
  5. 如权利要求4所述的TFT背板的制作方法，其中，所述氧化物半导体为铟镓锌氧化物。
  6. 如权利要求1所述的TFT背板的制作方法，其中，所述支撑物的形状为柱状。
  7. 一种TFT背板，包括：衬底基板、设于所述衬底基板上的栅极、设 于所述栅极与衬底基板上的栅极绝缘层、设于所述栅极绝缘层上且对应于所述栅极上方的有源层、设于所述有源层与栅极绝缘层上的刻蚀阻挡层、设于所述刻蚀阻挡层上的源极和漏极、设于所述源极、漏极与刻蚀阻挡层上的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的阳极、设于所述阳极与平坦层上的像素定义层、以及设于所述像素定义层上的支撑层；
    所述刻蚀阻挡层上设有分别对应于所述有源层两端的第一通孔和第二通孔，所述源极和漏极分别经由所述第一通孔和第二通孔与所述有源层的两端相接触；
    所述钝化层与平坦层上设有对应于所述漏极上方的第三通孔，所述阳极经由所述第三通孔与所述漏极相接触；
    所述像素定义层上设有对应于所述阳极上方的开口，所述支撑层包括间隔设置的数个支撑物；
    所述像素定义层与支撑层为一个整体，且材料相同。
  8. 如权利要求7所述的TFT背板，其中，所述有源层的材料为氧化物半导体。
  9. 如权利要求8所述的TFT背板，其中，所述氧化物半导体为铟镓锌氧化物。
  10. 如权利要求7所述的TFT背板，其中，所述支撑物的形状为柱状。
  11. 一种TFT背板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上形成栅极，在所述栅极与衬底基板上形成栅极绝缘层；
    步骤2、在所述栅极绝缘层上形成对应于所述栅极上方的有源层，在所述有源层与栅极绝缘层上形成刻蚀阻挡层，在所述刻蚀阻挡层上形成分别对应于所述有源层两端的第一通孔和第二通孔；
    在所述刻蚀阻挡层上形成源极和漏极，所述源极和漏极分别经由所述第一通孔和第二通孔与所述有源层的两端相接触；
    步骤3、在所述源极、漏极与刻蚀阻挡层上形成钝化层，在所述钝化层上形成平坦层；
    在所述钝化层与平坦层上形成对应于所述漏极上方的第三通孔；
    在所述平坦层上形成阳极，所述阳极经由所述第三通孔与所述漏极相接触；
    步骤4、在所述阳极与平坦层上形成一有机光阻层，采用一半色调掩膜板对所述有机光阻层进行曝光、显影，同时得到像素定义层与设于所述像 素定义层上的支撑层，所述像素定义层上设有对应于所述阳极上方的开口，所述支撑层包括间隔设置的数个支撑物；
    其中，所述有源层的材料为氧化物半导体；
    其中，所述支撑物的形状为柱状。
  12. 如权利要求11所述的TFT背板的制作方法，其中，所述步骤4中，所述半色调掩膜板包括对应于所述开口的全透射区域、对应于所述支撑层的非透射区域、以及对应于所述像素定义层上除所述开口以及被所述支撑层覆盖的区域以外的其它区域的半透射区域。
  13. 如权利要求12所述的TFT背板的制作方法，其中，所述全透射区域的光线穿透率为100％，所述半透射区域的光线穿透率为50％，所述非透射区域的光线穿透率为0％。
  14. 如权利要求11所述的TFT背板的制作方法，其中，所述氧化物半导体为铟镓锌氧化物。
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