WO2016176893A1 - Amoled背板的制作方法及其结构 - Google Patents

Amoled背板的制作方法及其结构 Download PDF

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WO2016176893A1
WO2016176893A1 PCT/CN2015/081722 CN2015081722W WO2016176893A1 WO 2016176893 A1 WO2016176893 A1 WO 2016176893A1 CN 2015081722 W CN2015081722 W CN 2015081722W WO 2016176893 A1 WO2016176893 A1 WO 2016176893A1
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layer
drain
polysilicon segment
source
insulating layer
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PCT/CN2015/081722
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English (en)
French (fr)
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徐源竣
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深圳市华星光电技术有限公司
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Priority to US14/764,164 priority Critical patent/US10038043B2/en
Publication of WO2016176893A1 publication Critical patent/WO2016176893A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and a structure for fabricating an AMOLED backplane.
  • OLED organic light emitting diodes
  • OLEDs can be classified into passive OLEDs (PMOLEDs) and active OLEDs (AMOLEDs) according to the type of driving.
  • the AMOLED is usually composed of a low temperature poly-Silicon (LTPS) driven backplane and an electroluminescent layer to form a self-illuminating component.
  • LTPS low temperature poly-Silicon
  • electroluminescent layer to form a self-illuminating component.
  • Low-temperature polysilicon has high electron mobility.
  • low-temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, and low energy consumption.
  • FIG. 1 is a schematic cross-sectional view of a conventional AMOLED backplane.
  • the manufacturing method of the AMOLED backplane mainly includes the following steps:
  • Step 1 providing a substrate 100, the substrate 100 includes a switching TFT region, a storage capacitor region, and a driving TFT region, a buffer layer 200 is deposited on the substrate 100;
  • Step 2 depositing an amorphous silicon layer on the buffer layer 200, and crystallizing the amorphous silicon layer into a polysilicon layer by a crystallization process, and then patterning the polysilicon layer through a mask process. Forming a first polysilicon segment 310 in the region of the switching TFT, a second polysilicon segment 320 in the driving TFT region, and a third polysilicon segment 330 in the storage capacitor region;
  • Step 3 depositing a gate insulating layer 400 on the first polysilicon segment 310, the second polysilicon segment 320, the third polysilicon segment 330, and the buffer layer 200;
  • Step 4 depositing a first photoresist layer on the gate insulating layer 400 and patterning the first photoresist layer through a mask process;
  • the first photoresist layer shields the first polysilicon segment 310 and the middle portion of the second polysilicon segment 320, and does not shield the third polysilicon segment 330;
  • the first polysilicon segment 310 and the second polysilicon segment 320, and the third polysilicon segment 330 is heavily P-doped so as to be on both sides of the first polysilicon segment 310 and the second polysilicon segment 320, and the entire third polysilicon segment 330 Forming a P-type heavily doped region;
  • Step 5 removing the first photoresist layer, depositing a first metal layer on the gate insulating layer 400 and patterning the first metal layer through a mask process to form a first gate in the region of the switching TFT a pole 610, a second gate 620 located in the driving TFT region, and a metal electrode 630 located in the storage capacitor region;
  • Step 6 Deposit an interlayer insulating layer 700 on the first gate 610, the second gate 620, the metal electrode 630, and the gate insulating layer 400, and process the interlayer insulating layer 700 through a mask process. And a first via 710 is formed on the gate insulating layer 400 corresponding to the first polysilicon segment 310 and the P-type heavily doped region at both ends of the second polysilicon segment 320;
  • Step 7 depositing a second metal layer on the interlayer insulating layer 700 and patterning the second metal layer through a mask process to form a first source/drain 810, and a second source/drain 820;
  • the first source/drain 810 and the second source/drain 820 pass through the first via 710 and the first polysilicon segment 310 and the P-type at both ends of the second polysilicon segment 320, respectively.
  • the heavily doped regions are in contact;
  • Step 8 forming a flat layer 830 on the first source/drain 810, the second source/drain 820, and the interlayer insulating layer 700, and corresponding to the flat layer 830 through a mask process Forming a second via 840 above the second source/drain 820;
  • Step 9 depositing a conductive film on the flat layer 830 and patterning the conductive film through a mask process to form an anode 850;
  • the anode 850 is in contact with the second source/drain 820 via the second via 840;
  • Step 10 depositing a second photoresist layer on the anode 850, and the flat layer 830, and patterning the second photoresist layer through a mask process to form a pixel defining layer 900;
  • Step 11 Deposit a third photoresist layer on the pixel defining layer 900 and the anode 850, and pattern the third photoresist layer through a mask process to form a photoresist spacer 910.
  • the object of the present invention is to provide a method for fabricating an AMOLED backplane, which is simple in process, can improve production efficiency and save cost.
  • Another object of the present invention is to provide an AMOLED backplane structure, which is simple in structure and easy to use. Produced at a low cost.
  • the present invention provides a method for fabricating an AMOLED backplane, comprising the following steps:
  • Step 1 providing a substrate, the substrate comprising a switching TFT region, a storage capacitor region, and a driving TFT region, and depositing a buffer layer on the substrate;
  • Step 2 depositing an amorphous silicon layer on the buffer layer, and crystallizing the amorphous silicon layer into a polysilicon layer by a crystallization process, and then patterning the polysilicon layer through a mask process, respectively Forming a first polysilicon segment in the region of the switching TFT, a second polysilicon segment in the driving TFT region, and a third polysilicon segment in the storage capacitor region;
  • Step 3 depositing a gate insulating layer on the first polysilicon segment, the second polysilicon segment, the third polysilicon segment, and the buffer layer;
  • Step 4 depositing a first photoresist layer on the gate insulating layer and patterning the first photoresist layer through a mask process to form a photoresist layer; the photoresist layer shielding the first polysilicon a segment, and a middle portion of the second polysilicon segment, not shielding the third polysilicon segment;
  • Step 5 removing the photoresist layer, depositing a first metal layer on the gate insulating layer and patterning the first metal layer through a mask process to form a first gate located in a region of the switching TFT, respectively a second gate driving the TFT region, and a metal electrode located in the storage capacitor region;
  • Step 6 depositing an interlayer insulating layer on the first gate electrode, the second gate electrode, the metal electrode, and the gate insulating layer, and performing the photomask process on the interlayer insulating layer and the gate insulating layer Forming a first via hole above the P-type heavily doped region corresponding to the first polysilicon segment and the second polysilicon segment respectively;
  • Step 7 depositing a conductive film on the interlayer insulating layer, and patterning the conductive film through a mask process to form a first source and a first drain located in the region of the switching TFT, and a portion located in the driving TFT region a second source and a second drain, wherein the second drain extends to a storage capacitor region and serves as an anode of the AMOLED;
  • the first source, the second drain, the second source, and the second drain respectively pass through the first via and the first polysilicon segment and the P at both ends of the second polysilicon segment Type heavily doped regions are in contact;
  • Step 8 sequentially depositing a second photoresist layer and a third photoresist layer on the first source, the first drain, the second source, the second drain, and the interlayer insulating layer, and passing through one and a half
  • the color mask process simultaneously patterns the second photoresist layer and the third photoresist layer to form a pixel defining layer and a photoresist spacer, and the pixel defining layer forms a second via hole to expose the device
  • the second drain is described.
  • the crystallization process in the step 2 is excimer laser annealing treatment, solid phase crystallization, metal induced crystallization, or metal induced lateral crystallization.
  • the gate insulating layer in the step 3 is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the step 5 implants boron ions using an ion implanter to obtain the P-type heavily doped region.
  • the interlayer insulating layer in the step 7 is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the conductive film that is, the first source, the first drain, the second source, and the second drain are configured by sandwiching a metal layer of two conductive oxide layers.
  • the three-layer structure, the material of the conductive oxide layer is indium tin oxide, and the material of the metal layer is silver or aluminum.
  • the present invention also provides an AMOLED backplane structure, including a substrate, a buffer layer disposed on the substrate, a first polysilicon segment disposed on the buffer layer, a second polysilicon segment, and a first a third polysilicon segment, a gate insulating layer disposed on the first polysilicon segment, the second polysilicon segment, the third polysilicon segment, and the buffer layer, disposed on the gate insulating layer a first gate electrode, a second gate electrode, and a metal electrode, an interlayer insulating layer disposed on the first gate electrode, the second gate electrode, the metal electrode, and the gate insulating layer, disposed between the layers a first source, a second drain, a second source, and a second drain on the insulating layer, and the first source, the second drain, the second source, the second drain, and the layer a pixel defining layer on the insulating layer, and a photoresist spacer disposed on the pixel defining layer;
  • a first via hole is disposed on the interlayer insulating layer and the P-type heavily doped region corresponding to the first polysilicon segment and the second polysilicon segment on the gate insulating layer, the first via a source, a first drain, a second source, and a second drain are respectively doped with the P-type at both ends of the first polysilicon segment and the second polysilicon via the first via hole
  • the impurity region is in contact with each other;
  • a second via hole is disposed on the pixel defining layer corresponding to the second drain to expose the second drain;
  • the first polysilicon segment, the first gate and the first source, the first drain constitute a switching TFT; the second polysilicon segment, the second gate and the second source, and the second drain
  • the driving TFT is configured;
  • the third polysilicon segment and the metal electrode constitute a storage capacitor, and the second drain serves as an anode of the AMOLED.
  • the gate insulating layer is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the interlayer insulating layer is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the first source, the second drain, the second source, and the second drain are both conductive oxides
  • the layer is sandwiched by a three-layer structure composed of a metal layer.
  • the material of the conductive oxide layer is indium tin oxide, and the material of the metal layer is silver or aluminum.
  • the present invention also provides an AMOLED backplane structure, including a substrate, a buffer layer disposed on the substrate, a first polysilicon segment disposed on the buffer layer, a second polysilicon segment, and a first a third polysilicon segment, a gate insulating layer disposed on the first polysilicon segment, the second polysilicon segment, the third polysilicon segment, and the buffer layer, disposed on the gate insulating layer a first gate electrode, a second gate electrode, and a metal electrode, an interlayer insulating layer disposed on the first gate electrode, the second gate electrode, the metal electrode, and the gate insulating layer, disposed between the layers a first source, a first drain, a second source, and a second drain on the insulating layer, disposed on the first source, the first drain, the second source, the second drain, and the layer a pixel defining layer on the insulating layer, and a photoresist spacer disposed on the pixel defining layer;
  • a first via hole is disposed on the interlayer insulating layer and the P-type heavily doped region corresponding to the first polysilicon segment and the second polysilicon segment on the gate insulating layer, the first via a source, a first drain, a second source, and a second drain are respectively doped with the P-type at both ends of the first polysilicon segment and the second polysilicon via the first via hole
  • the impurity region is in contact with each other;
  • a second via hole is disposed on the pixel defining layer corresponding to the second drain to expose the second drain;
  • the first polysilicon segment, the first gate and the first source, the first drain constitute a switching TFT;
  • the second polysilicon segment, the second gate and the second source, and the second drain Forming a driving TFT;
  • the third polysilicon segment and the metal electrode constitute a storage capacitor; and the second drain serves as an anode of the AMOLED;
  • the gate insulating layer is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer;
  • the interlayer insulating layer is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer;
  • the first source, the first drain, the second source, and the second drain are three-layer structures in which two conductive oxide layers are sandwiched by a metal layer, and the conductive oxide layer is made of a metal layer.
  • the indium tin oxide is made of silver or aluminum.
  • the method for fabricating the AMOLED backplane of the present invention by using the drain of the driving TFT as the anode of the AMOLED, saves the fabrication process of the flat layer and the anode layer compared with the prior art, and simultaneously passes through one and a half
  • the photomask process forms a pixel defining layer and a photoresist spacer, so that the manufacturing method of the AMOLED backplane of the present invention requires only six mask processes, which saves three mask processes compared with the prior art, thereby simplifying the process and improving the process. Production efficiency and cost savings.
  • the AMOLED backplane structure of the invention has a simple structure, is easy to manufacture, and has low cost.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional AMOLED backplane
  • FIG. 2 is a flow chart of a method for fabricating an AMOLED backplane according to the present invention
  • step 1 is a schematic diagram of step 1 of a method for fabricating an AMOLED backplane according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an AMOLED backplane according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating an AMOLED backplane according to the present invention.
  • FIGS. 6-7 are schematic diagrams showing step 4 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 7 is a schematic diagram of step 7 of a method for fabricating an AMOLED backplane according to the present invention.
  • 11-12 are schematic diagrams showing the step 8 of the method for fabricating an AMOLED backplane according to the present invention.
  • the present invention provides a method for fabricating an AMOLED backplane, including the following steps:
  • a substrate 1 is provided.
  • the substrate 1 includes a switching TFT region, a storage capacitor region, and a driving TFT region, and a buffer layer 2 is deposited on the substrate 1.
  • the buffer layer 2 is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • Step 2 depositing an amorphous silicon layer on the buffer layer 2, and crystallizing the amorphous silicon layer into a polysilicon layer by a crystallization process, and then patterning the polysilicon layer Forming a first polysilicon segment 31 in the region of the switching TFT, a second polysilicon segment 32 in the region of the driving TFT, and a third polysilicon segment 33 in the storage capacitor region, respectively.
  • the third polysilicon segment 33 is located between the first polysilicon segment 31 and the second polysilicon segment 32.
  • the crystallization process may employ excimer laser annealing (ELA), solid phase crystallization (SPC), metal induced crystallization (MIC), or metal induced lateral crystallization (MILC).
  • ELA excimer laser annealing
  • SPC solid phase crystallization
  • MIC metal induced crystallization
  • MILC metal induced lateral crystallization
  • Step 3 As shown in FIG. 5, a gate insulating layer 4 is deposited on the first polysilicon segment 31, the second polysilicon segment 32, the third polysilicon segment 33, and the buffer layer 2.
  • the gate insulating layer 4 is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • Step 4 As shown in FIG. 6, a first photoresist layer is deposited on the gate insulating layer 4, and the first photoresist layer is patterned by a mask process to form a photoresist layer 5.
  • the photoresist layer 5 shields the first polysilicon segment 31 and the middle portion of the second polysilicon segment 32, and does not shield the third polysilicon segment 33, and is defined by the photoresist layer 5 A P-type heavily doped region is performed.
  • the first polysilicon segment 31, the second polysilicon segment 32, and the third polysilicon segment 33 are heavily doped with P by using the photoresist layer 5 as a shielding layer.
  • a P-type heavily doped (P+) region is formed on both sides of the first polysilicon segment 31 and the second polysilicon segment 32, and over the entire third polysilicon segment 33.
  • the P-type heavily doped (P+) region is obtained by implanting boron ions using an ion implanter.
  • Step 5 as shown in FIG. 8, the photoresist layer 5 is removed, a first metal layer is deposited on the gate insulating layer 4, and the first metal layer is patterned by a mask process to form a switching TFT.
  • the first metal layer that is, the material of the first gate 61, the second gate 62 and the metal electrode 63 is molybdenum (Mo).
  • Step 6 depositing an interlayer insulating layer 7 on the first gate 61, the second gate 62, the metal electrode 63, and the gate insulating layer 4, and passing through a mask process
  • a first via 71 is formed on the interlayer insulating layer 7 and the P-type heavily doped region corresponding to the first polysilicon segment 31 and the second polysilicon segment 32 on the gate insulating layer 4.
  • the interlayer insulating layer 7 is a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • Step 7 depositing a conductive film on the interlayer insulating layer 7, and patterning the conductive film through a mask process to form a first source 72 and a first drain in the region of the switching TFT.
  • the pole 73 is located at the second source 74 and the second drain 75 of the driving TFT region, wherein the second drain 75 extends to the storage capacitor region and functions as an anode of the AMOLED.
  • the first source 72, the first drain 73, the second source 74, and the second drain 75 are respectively connected to the first polysilicon segment 31 and the second via the first via 71 P at both ends of the crystalline silicon segment 32 Type heavily doped (P+) regions are in contact.
  • the conductive film that is, the first source 72, the first drain 73, the second source 74, and the second drain 75 are configured by sandwiching a metal layer of two conductive oxide layers.
  • the three-layer structure, the material of the conductive oxide layer is indium tin oxide (ITO), and the material of the metal layer is silver (Ag) or aluminum (Al).
  • the first polysilicon segment 31, the first gate 61 and the first source 72 and the second drain 73 constitute a switching TFT; the second polysilicon segment 32, the second gate 62 and the second source
  • the electrode 74 and the second drain 75 constitute a driving TFT; the third polysilicon segment 33 and the metal electrode 63 constitute a storage capacitor.
  • Step 8 sequentially depositing a second photoresist layer 80 on the first source 72, the first drain 73, the second source 74, the second drain 75, and the interlayer insulating layer 7.
  • a second via 81 is formed on the pixel defining layer 8 to expose the second drain 75.
  • the specific process of the halftone mask process is: first, coating a photoresist layer on the third photoresist layer 90, then exposing and developing the photoresist layer by using the halftone mask 10, and then applying the second
  • the photoresist layer 80 and the third photoresist layer 90 are secondarily etched, and the residual photoresist layer is removed to obtain a patterned pixel defining layer 8 and a photoresist spacer 9.
  • the method for fabricating the above-mentioned AMOLED backplane by using the drain of the driving TFT as the anode of the AMOLED, eliminates the fabrication process of the flat layer and the anode layer compared with the prior art, and forms a pixel definition through a halftone mask process.
  • the layer and the photoresist spacers enable the manufacturing method of the AMOLED backplane of the present invention to require only six mask processes, which saves three mask processes compared with the prior art, which simplifies the process, improves production efficiency, and saves costs.
  • FIG. 12 is a cross-sectional view showing the structure of an AMOLED backplane according to the present invention.
  • the present invention further provides an AMOLED backplane structure including a substrate 1 and a buffer layer 2 disposed on the substrate 1 and disposed in the buffer.
  • the first polysilicon segment 31, the second polysilicon segment 32, and the third polysilicon segment 33 spaced apart from each other on the layer 2 are disposed on the first polysilicon segment 31 and the second polysilicon segment 32.
  • the first drain 73, the second source 74, and the second drain 75 are disposed on the first source 72, the first drain 73, the second source 74, the second drain 75, and the interlayer insulating layer
  • a P-type heavily doped (P+) region is formed on both ends of the first polysilicon segment 31 and the second polysilicon segment 32, and the entire third polysilicon segment 33.
  • the interlayer insulating layer And a first via 71 is disposed above the P-type heavily doped region on the gate insulating layer 4 corresponding to the first polysilicon segment 31 and the second polysilicon segment 32, the first The source 72, the first drain 73, the second source 74, and the second drain 75 are respectively connected to the first polysilicon segment 31 and the second polysilicon segment 32 via the first via 71.
  • the P-type heavily doped (P+) regions at both ends are in contact with each other; a second via 81 is disposed on the prime defining layer 8 corresponding to the second drain 75 to expose the second drain 75.
  • the first polysilicon segment 31, the first gate 61 and the first source 72, the first drain 73 constitute a switching TFT; the second polysilicon segment 32, the second gate 62 and the second source
  • the electrode 74 and the second drain 75 constitute a driving TFT;
  • the third polysilicon segment 33 and the metal electrode 63 constitute a storage capacitor; and
  • the second drain 75 serves as an anode of the AMOLED.
  • the buffer layer 2 may be a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the gate insulating layer 4 may be a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the first gate 61, the second gate 62 and the metal electrode 63 is molybdenum.
  • the interlayer insulating layer 7 may be a silicon oxide layer, a silicon nitride layer, or a multilayer composite structure composed of a silicon oxide layer and a silicon nitride layer.
  • the first source 72, the first drain 73, the second source 74, and the second drain 75 are three-layer structures in which two conductive oxide layers are sandwiched by a metal layer, and the conductive
  • the material of the oxide layer is indium tin oxide, and the material of the metal layer is silver or aluminum.
  • the above AMOLED backplane structure has a simple structure, is easy to manufacture, and has low cost.
  • the method for fabricating the AMOLED backplane of the present invention eliminates the fabrication process of the flat layer and the anode layer by using the drain of the driving TFT as the anode of the AMOLED, and simultaneously eliminates the fabrication process of the flat layer and the anode layer.
  • the photomask process forms a pixel defining layer and a photoresist spacer, so that the manufacturing method of the AMOLED backplane of the present invention requires only six mask processes, and the three mask processes are reduced compared with the prior art, thereby effectively simplifying the process. Increased production efficiency and cost savings.
  • the AMOLED backplane structure of the invention has a simple structure, is easy to manufacture, and has low cost.

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Abstract

本发明提供一种AMOLED背板的制作方法及其结构，该方法通过将驱动TFT的漏极充当AMOLED的阳极，与现有技术相比，省去了平坦层和阳极层的制作过程，同时通过一道半色调光罩制程形成像素定义层与光阻间隔物，使得本发明的AMOLED背板的制作方法只需要6道光罩制程，与现有技术相比节约了3道光罩制程，有效简化了制程，提高了生产效率，节省成本。本发明的AMOLED背板结构，结构简单，易于制作，且成本低。

Description

AMOLED背板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种AMOLED背板的制作方法及其结构。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)。其中，AMOLED通常是由低温多晶硅(Low Temperature Poly-Silicon，LTPS)驱动背板和电激发光层组成自发光组件。低温多晶硅具有较高的电子迁移率，对AMOLED而言，采用低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点。
图1为一种现有AMOLED背板的剖面结构示意图。该AMOLED背板的制作方法主要包括如下步骤：
步骤1、提供基板100，所述基板100包括开关TFT区域、存储电容区域、及驱动TFT区域，在所述基板100上沉积缓冲层200；
步骤2、在所述缓冲层200上沉积非晶硅层，并通过结晶制程使所述非晶硅层结晶、转变为多晶硅层，再通过一道光罩制程对所述多晶硅层进行图案化处理，形成位于开关TFT区域的第一多晶硅段310、位于驱动TFT区域的第二多晶硅段320、及位于存储电容区域的第三多晶硅段330；
步骤3、在所述第一多晶硅段310、第二多晶硅段320、第三多晶硅段330、及缓冲层200上沉积栅极绝缘层400；
步骤4、在所述栅极绝缘层400上沉积第一光阻层并通过一道光罩制程图案化该第一光阻层；
所述第一光阻层遮蔽所述第一多晶硅段310、及第二多晶硅段320的中部，不遮蔽所述第三多晶硅段330；
以所述第一光阻层为遮蔽层，对所述第一多晶硅段310、第二多晶硅段 320、及第三多晶硅段330进行P型重掺杂，从而在所述第一多晶硅段310与第二多晶硅段320的两侧、及整个第三多晶硅段330上形成P型重掺杂区域；
步骤5、除去所述第一光阻层，在所述栅极绝缘层400上沉积第一金属层并通过一道光罩制程图案化该第一金属层，分别形成位于开关TFT区域的第一栅极610、位于驱动TFT区域的第二栅极620、及位于存储电容区域的金属电极630；
步骤6、在所述第一栅极610、第二栅极620、金属电极630、及栅极绝缘层400上沉积层间绝缘层700，并通过一道光罩制程在所述层间绝缘层700、及栅极绝缘层400上分别对应所述第一多晶硅段310、及第二多晶硅段320两端的P型重掺杂区域上方形成第一过孔710；
步骤7、在所述层间绝缘层700上沉积第二金属层并通过一道光罩制程图案化该第二金属层，形成第一源/漏极810、及第二源/漏极820；
所述第一源/漏极810、及第二源/漏极820分别经由所述第一过孔710与所述第一多晶硅段310、及第二多晶硅段320两端的P型重掺杂区域相接触；
步骤8、在所述第一源/漏极810、第二源/漏极820、及层间绝缘层700上形成平坦层830，并通过一道光罩制程在所述平坦层830上对应所述第二源/漏极820上方形成第二过孔840；
步骤9、在所述平坦层830上沉积一导电薄膜并通过一道光罩制程图案化该导电薄膜，形成阳极850；
所述阳极850经由所述第二过孔840与所述第二源/漏极820相接触；
步骤10、在所述阳极850、及平坦层830上沉积第二光阻层，并通过一道光罩制程图案化该第二光阻层，形成像素定义层900；
步骤11、在所述像素定义层900、及阳极850上沉积第三光阻层，并通过一道光罩制程图案化该第三光阻层，形成光阻间隔物910。
但上述制作过程需要9道光罩，制程较为繁琐，生产效率低，成本高。因此有必要提出一种新的AMOLED背板的制作方法及其结构，以解决上述问题。
发明内容
本发明的目的在于提供一种AMOLED背板的制作方法，制程简单，可提高生产效率，节省成本。
本发明的另一目的在于提供一种AMOLED背板结构，结构简单，易于 制作，且成本低。
为实现上述目的，本发明提供一种AMOLED背板的制作方法，包括如下步骤：
步骤1、提供基板，所述基板包括开关TFT区域、存储电容区域、及驱动TFT区域，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积非晶硅层，并通过结晶制程使所述非晶硅层结晶、转变为多晶硅层，再通过一道光罩制程对所述多晶硅层进行图案化处理，分别形成位于开关TFT区域的第一多晶硅段、位于驱动TFT区域的第二多晶硅段、及位于存储电容区域的第三多晶硅段；
步骤3、在所述第一多晶硅段、第二多晶硅段、第三多晶硅段、及缓冲层上沉积栅极绝缘层；
步骤4、在所述栅极绝缘层上沉积第一光阻层并通过一道光罩制程图案化该第一光阻层，形成光阻层；所述光阻层遮蔽所述第一多晶硅段、及第二多晶硅段的中部，不遮蔽所述第三多晶硅段；
以所述光阻层为遮蔽层，对所述第一多晶硅段、第二多晶硅段、及第三多晶硅段进行P型重掺杂，从而在所述第一多晶硅段与第二多晶硅段的两侧、及整个第三多晶硅段上形成P型重掺杂区域；
步骤5、除去所述光阻层，在所述栅极绝缘层上沉积第一金属层并通过一道光罩制程图案化该第一金属层，分别形成位于开关TFT区域的第一栅极、位于驱动TFT区域的第二栅极、及位于存储电容区域的金属电极；
步骤6、在所述第一栅极、第二栅极、金属电极、及栅极绝缘层上沉积层间绝缘层，并通过一道光罩制程在所述层间绝缘层、及栅极绝缘层上分别对应所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域上方形成第一过孔；
步骤7、在所述层间绝缘层上沉积一导电薄膜，并通过一道光罩制程图案化该导电薄膜，形成位于开关TFT区域的第一源极与第一漏极、位于驱动TFT区域的第二源极与第二漏极，其中，所述第二漏极延伸至存储电容区域，并充当AMOLED的阳极；
所述第一源极、第二漏极、第二源极、及第二漏极分别经由所述第一过孔与所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域相接触；
步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上依次沉积第二光阻层与第三光阻层，并通过一道半色调光罩制程同时对该第二光阻层与第三光阻层进行图案化处理，形成像素定义层、及光阻间隔物，所述像素定义层上形成第二过孔，以暴露出所述第二漏极。
所述步骤2中的结晶制程为准分子激光退火处理、固相结晶化、金属诱导结晶、或金属诱导横向结晶。
所述步骤3中的栅极绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
所述步骤5采用离子植入机植入硼离子得到所述P型重掺杂区域。
所述步骤7中的层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
所述步骤8中，所述导电薄膜，也即所述第一源极、第一漏极、第二源极、及第二漏极的结构为两导电氧化物层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化铟锡，所述金属层的材料为银或铝。
本发明还提供一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上相互间隔的第一多晶硅段、第二多晶硅段、及第三多晶硅段、设于所述第一多晶硅段、第二多晶硅段、第三多晶硅段、及缓冲层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、第二栅极、及金属电极、设于所述第一栅极、第二栅极、金属电极、及栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的第一源极、第二漏极、第二源极、及第二漏极、设于所述第一源极、第二漏极、第二源极、第二漏极及层间绝缘层上的像素定义层、及设于所述像素定义层上的光阻间隔物；
所述第一多晶硅段与第二多晶硅段的两端、及整个第三多晶硅段上形成有P型重掺杂区域；
所述层间绝缘层、及栅极绝缘层上对应所述第一多晶硅段、及第二多晶硅段两侧的P型重掺杂区域上方设有第一过孔，所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一过孔与所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域相接触；所述素定义层上对应所述第二漏极上方设有第二过孔，暴露出所述第二漏极；
所述第一多晶硅段、第一栅极与第一源极、第一漏极构成开关TFT；所述第二多晶硅段、第二栅极与第二源极、第二漏极构成驱动TFT；所述第三多晶硅段与金属电极构成存储电容，同时所述第二漏极充当AMOLED的阳极。
所述栅极绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
所述层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
所述第一源极、第二漏极、第二源极、及第二漏极均为两导电氧化物 层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化铟锡，所述金属层的材料为银或铝。
本发明还提供一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上相互间隔的第一多晶硅段、第二多晶硅段、及第三多晶硅段、设于所述第一多晶硅段、第二多晶硅段、第三多晶硅段、及缓冲层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、第二栅极、及金属电极、设于所述第一栅极、第二栅极、金属电极、及栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极及层间绝缘层上的像素定义层、及设于所述像素定义层上的光阻间隔物；
所述第一多晶硅段与第二多晶硅段的两端、及整个第三多晶硅段上形成有P型重掺杂区域；
所述层间绝缘层、及栅极绝缘层上对应所述第一多晶硅段、及第二多晶硅段两侧的P型重掺杂区域上方设有第一过孔，所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一过孔与所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域相接触；所述素定义层上对应所述第二漏极上方设有第二过孔，暴露出所述第二漏极；
所述第一多晶硅段、第一栅极与第一源极、第一漏极构成开关TFT；所述第二多晶硅段、第二栅极与第二源极、第二漏极构成驱动TFT；所述第三多晶硅段与金属电极构成存储电容；同时所述第二漏极充当AMOLED的阳极；
其中，所述栅极绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构；
其中，所述层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构；
其中，所述第一源极、第一漏极、第二源极、及第二漏极均为两导电氧化物层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化铟锡，所述金属层的材料为银或铝。
本发明的有益效果：本发明的AMOLED背板的制作方法，通过驱动TFT的漏极充当AMOLED的阳极，与现有技术相比，省去了平坦层和阳极层的制作过程，同时通过一道半色调光罩制程形成像素定义层与光阻间隔物，使得本发明的AMOLED背板的制作方法只需要6道光罩制程，与现有技术相比节约了3道光罩制程，有效简化了制程，提高了生产效率，节省成本。本发明的AMOLED背板结构，结构简单，易于制作，且成本低。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为一种现有AMOLED背板的剖面结构示意图；
图2为本发明AMOLED背板的制作方法的流程图；
图3为本发明AMOLED背板的制作方法的步骤1的示意图；
图4为本发明AMOLED背板的制作方法的步骤2的示意图；
图5为本发明AMOLED背板的制作方法的步骤3的示意图；
图6-7为本发明AMOLED背板的制作方法的步骤4的示意图；
图8为本发明AMOLED背板的制作方法的步骤5的示意图；
图9为本发明AMOLED背板的制作方法的步骤6的示意图；
图10为本发明AMOLED背板的制作方法的步骤7的示意图；
图11-12为本发明AMOLED背板的制作方法的步骤8的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种AMOLED背板的制作方法，包括如下步骤：
步骤1、如图3所示，提供基板1，所述基板1包括开关TFT区域、存储电容区域、及驱动TFT区域，在所述基板1上沉积缓冲层2。
具体地，所述缓冲层2为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
步骤2、如图4所示，在所述缓冲层2上沉积非晶硅层，并通过结晶制程使所述非晶硅层结晶、转变为多晶硅层，再对所述多晶硅层进行图案化处理，分别形成位于开关TFT区域的第一多晶硅段31、位于驱动TFT区域的第二多晶硅段32、及位于存储电容区域的第三多晶硅段33。
具体地，所述第三多晶硅段33位于所述第一多晶硅段31与第二多晶硅段32之间。
具体地，所述结晶制程可以采用准分子激光退火处理(ELA)、固相结晶化(SPC)、金属诱导结晶(MIC)、或金属诱导横向结晶(MILC)。
步骤3、如图5所示，在所述第一多晶硅段31、第二多晶硅段32、第三多晶硅段33、及缓冲层2上沉积栅极绝缘层4。
具体地，所述栅极绝缘层4为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
步骤4、如图6所示，在所述栅极绝缘层4上沉积第一光阻层，并通过一道光罩制程图案化该第一光阻层，形成光阻层5。
所述光阻层5遮蔽所述第一多晶硅段31、及第二多晶硅段32的中部，不遮蔽所述第三多晶硅段33，通过所述光阻层5定义出将要进行P型重掺杂的区域。
如图7所示，以所述光阻层5为遮蔽层，对所述第一多晶硅段31、第二多晶硅段32、及第三多晶硅段33进行P型重掺杂，从而在所述第一多晶硅段31与第二多晶硅段32的两侧、及整个第三多晶硅段33上形成P型重掺杂(P+)区域。
具体地，采用离子植入机植入硼离子得到所述P型重掺杂(P+)区域。
步骤5、如图8所示，除去所述光阻层5，在所述栅极绝缘层4上沉积第一金属层并通过一道光罩制程图案化该第一金属层，分别形成位于开关TFT区域的第一栅极61、位于驱动TFT区域的第二栅极62、及位于存储电容区域的金属电极63。
具体的，所述第一金属层，也即所述第一栅极61、第二栅极62与金属电极63的材料为钼(Mo)。
步骤6、如图9所示，在所述第一栅极61、第二栅极62、金属电极63、及栅极绝缘层4上沉积层间绝缘层7，并通过一道光罩制程在所述层间绝缘层7、及栅极绝缘层4上对应所述第一多晶硅段31、及第二多晶硅段32两端的P型重掺杂区域上方形成第一过孔71。
具体地，所述层间绝缘层7为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
步骤7、如图10所示，在所述层间绝缘层7上沉积一导电薄膜，并通过一道光罩制程图案化该导电薄膜，形成位于开关TFT区域的第一源极72与第一漏极73、位于驱动TFT区域的第二源极74与第二漏极75，其中，所述第二漏极75延伸至存储电容区域，并充当AMOLED的阳极。
所述第一源极72、第一漏极73、第二源极74、及第二漏极75分别经由所述第一过孔71与所述第一多晶硅段31、及第二多晶硅段32两端的P 型重掺杂(P+)区域相接触。
具体地，所述导电薄膜，也即所述第一源极72、第一漏极73、第二源极74、及第二漏极75的结构为两导电氧化物层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化铟锡(ITO)，所述金属层的材料为银(Ag)或铝(Al)。所述第一多晶硅段31、第一栅极61与第一源极72、第二漏极73构成开关TFT；所述第二多晶硅段32、第二栅极62与第二源极74、第二漏极75构成驱动TFT；所述第三多晶硅段33与金属电极63构成存储电容。
步骤8、如图11-12所示，在第一源极72、第一漏极73、第二源极74、第二漏极75及层间绝缘层7上依次沉积第二光阻层80与第三光阻层90，并通过一道半色调光罩制程同时对该第二光阻层80与第三光阻层90进行图案化处理，形成像素定义层8、及光阻间隔物9，所述像素定义层8上形成第二过孔81，以暴露出所述第二漏极75。
具体的，所述半色调光罩制程的具体过程为：首先在第三光阻层90上涂布光阻层，然后采用半色调光罩10对光阻层进行曝光、显影，之后对第二光阻层80与第三光阻层90进行二次刻蚀，并去除残余的光阻层，得到图案化的像素定义层8、及光阻间隔物9。
上述AMOLED背板的制作方法，通过将驱动TFT的漏极充当AMOLED的阳极，与现有技术相比，省去了平坦层和阳极层的制作过程，同时通过一道半色调光罩制程形成像素定义层与光阻间隔物，使得本发明的AMOLED背板的制作方法只需要6道光罩制程，与现有技术相比节约了3道光罩制程，有效简化了制程，提高了生产效率，节省成本。
请参阅图12，其绘示本发明AMOLED背板结构的剖面示意图，本发明还提供一种AMOLED背板结构，包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上相互间隔的第一多晶硅段31、第二多晶硅段32、及第三多晶硅段33、设于所述第一多晶硅段31、第二多晶硅段32、第三多晶硅段33、及缓冲层2上的栅极绝缘层4、设于所述栅极绝缘层4上的第一栅极61、第二栅极62、及金属电极63、设于所述第一栅极61、第二栅极62、金属电极63、及栅极绝缘层4上的层间绝缘层7、设于所述层间绝缘层7上的第一源极72、第一漏极73、第二源极74、及第二漏极75设于所述第一源极72、第一漏极73、第二源极74、第二漏极75及层间绝缘层7上的像素定义层8、及设于所述像素定义层8上的光阻间隔物9。
具体地，所述第一多晶硅段31与第二多晶硅段32的两端、及整个第三多晶硅段33上形成有P型重掺杂(P+)区域。具体地，所述层间绝缘层 7、及栅极绝缘层4上对应所述第一多晶硅段31、及第二多晶硅段32两侧的P型重掺杂区域上方设有第一过孔71，所述第一源极72、第一漏极73、第二源极74、及第二漏极75分别经由所述第一过孔71与所述第一多晶硅段31、及第二多晶硅段32两端的P型重掺杂(P+)区域相接触；所述素定义层8上对应所述第二漏极75上方设有第二过孔81，暴露出所述第二漏极75。
所述第一多晶硅段31、第一栅极61与第一源极72、第一漏极73构成开关TFT；所述第二多晶硅段32、第二栅极62与第二源极74、及第二漏极75构成驱动TFT；所述第三多晶硅段33与金属电极63构成存储电容；同时所述第二漏极75充当AMOLED的阳极。
具体地，所述缓冲层2可以是氧化硅层、氮化硅层、或者是由氧化硅层与氮化硅层构成的多层复合结构。
具体地，所述栅极绝缘层4可以是氧化硅层、氮化硅层、或者是由氧化硅层与氮化硅层构成的多层复合结构。
具体的，所述第一栅极61、第二栅极62与金属电极63的材料为钼。
具体地，所述层间绝缘层7可以是氧化硅层、氮化硅层、或者是由氧化硅层与氮化硅层构成的多层复合结构。
具体地，所述第一源极72、第一漏极73、第二源极74、及第二漏极75均为两导电氧化物层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化铟锡，所述金属层的材料为银或铝。
上述AMOLED背板结构，结构简单，易于制作，且成本低。
综上所述，本发明的AMOLED背板的制作方法，通过将驱动TFT的漏极充当AMOLED的阳极，与现有技术相比，省去了平坦层和阳极层的制作过程，同时通过一道半色调光罩制程形成像素定义层与光阻间隔物，使得本发明的AMOLED背板的制作方法只需要6道光罩制程，与现有技术相比，减少了3道光罩制程，有效简化了制程，提高了生产效率，节省成本。本发明的AMOLED背板结构，结构简单，易于制作，且成本低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种AMOLED背板的制作方法，包括如下步骤：
    步骤1、提供基板，所述基板包括开关TFT区域、存储电容区域、及驱动TFT区域，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积非晶硅层，并通过结晶制程使所述非晶硅层结晶、转变为多晶硅层，再通过一道光罩制程对所述多晶硅层进行图案化处理，分别形成位于开关TFT区域的第一多晶硅段、位于驱动TFT区域的第二多晶硅段、及位于存储电容区域的第三多晶硅段；
    步骤3、在所述第一多晶硅段、第二多晶硅段、第三多晶硅段、及缓冲层上沉积栅极绝缘层；
    步骤4、在所述栅极绝缘层上沉积第一光阻层，并通过一道光罩制程图案化该第一光阻层，形成光阻层；所述光阻层遮蔽所述第一多晶硅段、及第二多晶硅段的中部，不遮蔽所述第三多晶硅段；
    以所述光阻层为遮蔽层，对所述第一多晶硅段、第二多晶硅段、及第三多晶硅段进行P型重掺杂，从而在所述第一多晶硅段与第二多晶硅段的两侧、及整个第三多晶硅段上形成P型重掺杂区域；
    步骤5、除去所述光阻层，在所述栅极绝缘层上沉积第一金属层并通过一道光罩制程图案化该第一金属层，分别形成位于开关TFT区域的第一栅极、位于驱动TFT区域的第二栅极、及位于存储电容区域的金属电极；
    步骤6、在所述第一栅极、第二栅极、金属电极、及栅极绝缘层上沉积层间绝缘层，并通过一道光罩制程在所述层间绝缘层、及栅极绝缘层上分别对应所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域上方形成第一过孔；
    步骤7、在所述层间绝缘层上沉积一导电薄膜，并通过一道光罩制程图案化该导电薄膜，形成位于开关TFT区域的第一源极与第一漏极、位于驱动TFT区域的第二源极与第二漏极，其中，所述第二漏极延伸至存储电容区域，并充当AMOLED的阳极；
    所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一过孔与所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域相接触；
    步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上依次沉积第二光阻层与第三光阻层，并通过一道半色调光罩制程同时对该第二光阻层与第三光阻层进行图案化处理，形成像素定义层、及光 阻间隔物，所述像素定义层上形成第二过孔，以暴露出所述第二漏极。
  2. 如权利要求1所述的AMOLED背板的制作方法，其中，所述步骤2中的结晶制程为准分子激光退火处理、固相结晶化、金属诱导结晶、或金属诱导横向结晶。
  3. 如权利要求1所述的AMOLED背板的制作方法，其中，所述步骤3中的栅极绝缘层的材料为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
  4. 如权利要求1所述的AMOLED背板的制作方法，其中，所述步骤5采用离子植入机植入硼离子得到所述P型重掺杂区域。
  5. 如权利要求1所述的AMOLED背板的制作方法，其中，所述步骤7中的层间绝缘层的材料为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
  6. 如权利要求1所述的AMOLED背板的制作方法，其中，所述步骤8中，所述导电薄膜，也即所述第一源极、第一漏极、第二源极、及第二漏极的结构为两导电氧化物层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化铟锡，所述金属层的材料为银或铝。
  7. 一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上相互间隔的第一多晶硅段、第二多晶硅段、及第三多晶硅段、设于所述第一多晶硅段、第二多晶硅段、第三多晶硅段、及缓冲层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、第二栅极、及金属电极、设于所述第一栅极、第二栅极、金属电极、及栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极及层间绝缘层上的像素定义层、及设于所述像素定义层上的光阻间隔物；
    所述第一多晶硅段与第二多晶硅段的两端、及整个第三多晶硅段上形成有P型重掺杂区域；
    所述层间绝缘层、及栅极绝缘层上对应所述第一多晶硅段、及第二多晶硅段两侧的P型重掺杂区域上方设有第一过孔，所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一过孔与所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域相接触；所述素定义层上对应所述第二漏极上方设有第二过孔，暴露出所述第二漏极；
    所述第一多晶硅段、第一栅极与第一源极、第一漏极构成开关TFT；所述第二多晶硅段、第二栅极与第二源极、第二漏极构成驱动TFT；所述第三多晶硅段与金属电极构成存储电容；同时所述第二漏极充当AMOLED 的阳极。
  8. 如权利要求7所述的AMOLED背板结构，其中，所述栅极绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
  9. 如权利要求7所述的AMOLED背板结构，其中，所述层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构。
  10. 如权利要求7所述的AMOLED背板结构，其中，所述第一源极、第一漏极、第二源极、及第二漏极均为两导电氧化物层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化铟锡，所述金属层的材料为银或铝。
  11. 一种AMOLED背板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上相互间隔的第一多晶硅段、第二多晶硅段、及第三多晶硅段、设于所述第一多晶硅段、第二多晶硅段、第三多晶硅段、及缓冲层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、第二栅极、及金属电极、设于所述第一栅极、第二栅极、金属电极、及栅极绝缘层上的层间绝缘层、设于所述层间绝缘层上的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极及层间绝缘层上的像素定义层、及设于所述像素定义层上的光阻间隔物；
    所述第一多晶硅段与第二多晶硅段的两端、及整个第三多晶硅段上形成有P型重掺杂区域；
    所述层间绝缘层、及栅极绝缘层上对应所述第一多晶硅段、及第二多晶硅段两侧的P型重掺杂区域上方设有第一过孔，所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一过孔与所述第一多晶硅段、及第二多晶硅段两端的P型重掺杂区域相接触；所述素定义层上对应所述第二漏极上方设有第二过孔，暴露出所述第二漏极；
    所述第一多晶硅段、第一栅极与第一源极、第一漏极构成开关TFT；所述第二多晶硅段、第二栅极与第二源极、第二漏极构成驱动TFT；所述第三多晶硅段与金属电极构成存储电容；同时所述第二漏极充当AMOLED的阳极；
    其中，所述栅极绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构；
    其中，所述层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层构成的多层复合结构；
    其中，所述第一源极、第一漏极、第二源极、及第二漏极均为两导电氧化物层夹合一金属层构成的三层结构，所述导电氧化物层的材料为氧化 铟锡，所述金属层的材料为银或铝。
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