WO2014121562A1 - Tn型阵列基板及其制作方法、显示装置 - Google Patents

Tn型阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2014121562A1
WO2014121562A1 PCT/CN2013/074799 CN2013074799W WO2014121562A1 WO 2014121562 A1 WO2014121562 A1 WO 2014121562A1 CN 2013074799 W CN2013074799 W CN 2013074799W WO 2014121562 A1 WO2014121562 A1 WO 2014121562A1
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Prior art keywords
photoresist
metal layer
transparent conductive
area
layer
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PCT/CN2013/074799
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English (en)
French (fr)
Inventor
吴松
包杰琼
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/368,614 priority Critical patent/US9620535B2/en
Publication of WO2014121562A1 publication Critical patent/WO2014121562A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • Embodiments of the present invention relate to a TN type array substrate, a method of fabricating the same, and a display device. Background technique
  • Exposure using a mask is an important step in the process of manufacturing a display panel. Exposure is not one. But one of the most sophisticated steps in the LCD panel is one of the most expensive steps in equipment investment and operating expenses. Therefore, by reducing the number of times the mask is used and exposure, reducing manufacturing costs and increasing equipment productivity, it is always an exploration of display panel manufacturing.
  • An existing TN (Twist Nematic) type display panel includes an array substrate.
  • the array substrate of the TN-type display panel includes: a transparent substrate 1, a first metal layer sequentially disposed on the transparent substrate 1, a gate insulating layer 7, an active layer 8, and a second metal layer.
  • the first metal layer includes a gate line 2 and a gate electrode 31, and the second metal layer includes a data line 4, a source 32 and a drain 33, and the transparent conductive layer includes the pixel electrode 5.
  • the gate line 2 and the data line 4 are alternately arranged, and a thin film transistor 3 and a pixel electrode 5 are formed in a region surrounded by the gate line 2 and the data line 4.
  • the array substrate further includes a gate line terminal region and a data line terminal region at the edge of the array substrate for connecting the circuit board.
  • the gate line 2 of the gate line terminal region bb' passes through the gate insulating layer 7 thereon and
  • the passivation layer 9 is provided with a via hole connected to the circuit board, and the data line 4 of the data line terminal region cc' is connected to the circuit board through a via hole provided on the passivation layer 9 thereon, and the gate line is controlled by the circuit board.
  • the voltage input of the data line is provided with a via hole connected to the circuit board, and the data line 4 of the data line terminal region cc' is connected to the circuit board through a via hole provided on the passivation layer 9 thereon, and the gate line is controlled by the circuit board.
  • the first metal layer, the passivation layer and the pixel electrode layer are respectively formed by one exposure using a common mask; the active layer and the second metal layer are masked by half gray or halftone
  • the template is formed by one exposure. That is, four exposures are required, and the number of exposures is large, the production cycle is long, and the cost is high. Summary of the invention
  • An embodiment of the present invention provides a method for fabricating a TN-type array substrate, including: forming a first metal layer, a gate insulating layer, an active layer, a second metal layer, and a transparent conductive layer on a substrate.
  • the first metal layer includes a gate
  • the second metal layer includes a data line
  • the transparent conductive layer includes a pixel electrode.
  • the forming the second metal layer and the transparent conductive layer includes: Forming a transparent conductive film and a metal film on the substrate in sequence;
  • the transparent conductive film and the metal film are subjected to a patterning process to form a TFT channel region, a transparent conductive layer, and a second metal layer.
  • the second metal layer includes a data line but does not include a source drain, and the transparent conductive layer includes a pixel electrode, a source and a drain, and a portion under the second metal layer; or
  • the second metal layer includes a data line and a source pattern but does not include a drain, the transparent conductive layer includes a pixel electrode and a drain, and a portion under the second metal layer; or the second metal layer includes a data line and a drain, but not including a source, the transparent conductive layer including a pixel electrode and a source, and a portion under the second metal layer; or, the second metal layer includes a data line and a source and drain
  • the transparent conductive layer includes a pixel electrode and a portion under the second metal layer.
  • the one-time patterning process includes: a halftone mask process and a photoresist reflow process.
  • the photoresist reflow process includes: using a photoresist having reflow characteristics, and subjecting the photoresist to heat treatment to cause the photoresist to reflow.
  • forming the TFT channel region, the transparent conductive layer, and the second metal layer using the one-time patterning process include:
  • a photoresist on a substrate on which a transparent conductive film and a second metal film are formed exposing with a halftone mask, developing the exposed substrate to form a photoresist completely reserved region, and a photoresist semi-reserved a region and a photoresist completely removed region, the photoresist completely removed region corresponding to at least a region where a TFT channel is to be formed, and etching is performed to form a TFT channel region; and a TFT channel region is formed by a photoresist reflow technique
  • the photoresist on the side is reflowed so that the photoresist covers the TFT channel region, and the thickness of the TFT channel region photoresist is controlled by controlling the time and temperature of the reflow so that the photoresist thickness of the TFT channel region is greater than a light scale of the semi-reserved area of the photoresist;
  • the photoresist completely remains at least corresponding to the data line region, and the photoresist semi-retaining portion at least corresponds to the photoresist electrode region, the source/drain region, and other regions of the photoresist is completely removed; or, The photoresist completely rests at least corresponding to the data line region and the source region, and the photoresist semi-retained portion at least corresponds to the pixel electrode region and the drain region, and other regions of the photoresist are completely removed; or, the lithography The photoresist completely retained at least corresponding to the data line region and the drain region, and the photoresist semi-retained portion completely removes at least the photoresist corresponding to the pixel electrode region and the source region, and other regions; or, the photoresist is completely retained At least a portion of the photoresist corresponding to the data line region and the source/drain region and the photoresist half-retaining portion corresponding to the pixel electrode region and other regions is completely removed.
  • the first metal layer, the gate insulating layer, and the active layer are sequentially formed on the substrate before forming the transparent conductive film and the second metal film.
  • the photoresist completely removed region further corresponds to a gate line terminal region, and before the removing the remaining portion of the photoresist, the method further includes: removing the exposed gate insulating film, at least in the gate terminal region The grid lines are exposed.
  • the method further includes: forming a gate insulating layer and a first metal layer on the substrate.
  • Another embodiment of the present invention provides a method of fabricating a TN-type array substrate, including: forming a first metal layer, a gate insulating layer, an active layer, a second metal layer, and a transparent conductive layer on a substrate,
  • the first metal layer includes a gate
  • the second metal layer includes a data line and a data line terminal
  • the transparent conductive layer includes a pixel electrode
  • the transparent conductive layer, the second metal layer, and the The active layer, the gate insulating layer and the first metal layer are sequentially formed on the substrate,
  • forming the first metal layer comprises:
  • the remaining portion corresponds to a region including a region where a gate electrode is to be formed and a region on both sides of the region of the data line terminal, a region where the photoresist completely removes a portion corresponding to the data line terminal, and a photoresist half of other regions. Reserved.
  • the remaining photoresist is removed to expose the data line terminals.
  • a TN-type array substrate including: a substrate, a first metal layer, a gate insulating layer, an active layer, a second metal layer, and a transparent conductive layer disposed on the substrate, wherein The second metal layer and the transparent conductive layer are formed by one patterning process, and the transparent conductive layer includes a portion under the second metal layer and a pixel electrode.
  • the second metal layer includes: a data line but does not include a source drain, the transparent conductive layer includes a source drain; or the second metal layer includes: a data line and a source but not including a drain, the transparent conductive layer includes a drain; or, the second metal layer includes: a data line and a drain but not a source, the transparent conductive layer further includes a source; or the second metal
  • the layers include: a data line and a source drain.
  • the array substrate includes a data line terminal region, wherein at least in the data line terminal region, the data line has no gate insulating layer thereon.
  • the array substrate includes a gate line terminal region
  • the first metal layer includes: a gate, a gate line, and a common electrode line, wherein at least in the gate line terminal region, there is no gate insulation on the gate line Floor.
  • the first metal layer, the gate insulating layer, the active layer, the transparent conductive layer, and the second metal layer are sequentially laminated on the substrate.
  • Still another embodiment of the present invention provides a display device comprising any of the TN type array substrates as described above.
  • FIG. 1 is a partial top plan view of a TN type array substrate in the prior art
  • FIG. 2 is a cross-sectional view of the array substrate shown in FIG.
  • FIG. 3 is a cross-sectional structural view showing a gate line terminal region and a data line terminal region of the array substrate shown in FIG. 1;
  • FIG. 4 is a schematic view showing the photoresist after development in the process of fabricating the TN-type array substrate shown in FIG. 11;
  • FIG. 5 is a metal film and transparent film in which the photoresist is completely removed during the process of fabricating the TN-type array substrate shown in FIG. Schematic diagram after the conductive film;
  • FIG. 6 is a schematic view of the second sub-layer of the channel region in the semiconductor layer during the process of fabricating the TN-type array substrate shown in FIG. 11;
  • FIG. 7 is a schematic view of the photoresist after reflowing in the process of fabricating the TN-type array substrate shown in FIG. 11;
  • FIG. 8 is a schematic view showing the photoresist after ashing in the process of fabricating the TN-type array substrate shown in FIG.
  • FIG. 9 is a schematic view showing the process of removing the metal thin film of the semi-retained portion of the photoresist during the process of fabricating the TN-type array substrate shown in FIG. 11;
  • FIG. 10 is a schematic view showing the process of removing the gate insulating layer in the process of fabricating the TN type array substrate shown in FIG. 11;
  • FIG. 10 is a schematic view showing the process of removing the gate insulating layer in the process of fabricating the TN type array substrate shown in FIG. 11;
  • FIG. 11 is a cross-sectional structural diagram of a TN type array substrate according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a method for fabricating a TN-type array substrate, including: a step of forming a first metal layer, a gate insulating layer, an active layer, a second metal layer, and a transparent conductive layer on a substrate, wherein The first metal layer includes a gate, the second metal layer includes a data line, and the transparent conductive layer includes: a pixel electrode; wherein forming the second metal layer and the transparent conductive layer includes:
  • a TFT channel region, a transparent conductive layer, and a second metal layer are formed by one patterning process.
  • film refers to a film formed by deposition or other process on a substrate using a certain material. If the “film” does not require a patterning process throughout the manufacturing process, the “film” may also be referred to as a “layer”; if the “film” requires a patterning process throughout the manufacturing process, it is referred to as "before the patterning process”.
  • the film “ is called a “layer” after the patterning process.
  • the "layer” after the patterning process contains at least one film "pattern”.
  • the above gate insulating layer may be formed by depositing a SiNx (silicon nitride) film on a transparent substrate.
  • the gate insulating layer generally does not require a patterning process.
  • the semiconductor layer is formed after the semiconductor film is patterned.
  • the first metal layer is formed by a patterning process of the metal film, including a gate, a gate line, and a common electrode line. Among them, the gate, the gate line and the common electrode line are film "patterns".
  • the second metal layer is formed by a metal film after a patterning process, including data lines.
  • the transparent conductive layer is formed by a patterning process of the transparent conductive film, including a pixel electrode.
  • the "patterning process” is a process of forming a film into a layer containing at least one pattern; the patterning process mentioned in the embodiment of the present invention comprises: applying a glue on the film, exposing the photoresist using a mask, The photoresist to be removed is then etched away by the developer, the portion of the film not covered with the photoresist is etched away, and the remaining photoresist is finally stripped.
  • Embodiments of the present invention provide a method for fabricating a TN-type array substrate, which uses a patterning process to form a first metal layer; a primary patterning process to form an active layer; and a patterning process to form a transparent conductive layer and a second metal layer, Without the need for a passivation layer, the number of patterning processes is reduced, the production cycle is shortened, and the cost is reduced.
  • the second metal layer includes a data line but does not include a source drain.
  • the transparent conductive layer includes a pixel electrode, a source and a drain, and a portion located under the second metal layer; There is no drain on the second metal layer, which can increase the pixel aperture ratio.
  • the second metal layer includes a data line and a source but does not include a drain.
  • the transparent conductive layer includes a pixel electrode and a drain, and a portion located below the second metal layer; There is no drain on the two metal layers, which can increase the pixel aperture ratio.
  • the second metal layer includes a data line and a drain but does not include a source.
  • the transparent conductive layer includes a pixel electrode and a source, and a portion below the second metal layer;
  • the conductivity of the metal layer is better than the conductivity of the transparent conductive layer, and the second metal layer includes the source level.
  • the pixel electrode can be turned on faster to achieve display. And there is no drain on the second metal layer, and the pixel aperture ratio can be increased.
  • the second metal layer includes a data line and a source drain.
  • the transparent conductive layer includes a pixel electrode and a portion under the second metal layer.
  • the second metal layer and the transparent conductive layer are all within the protection scope of the present invention, and the embodiment of the present invention includes only the data line and the source of the second metal layer.
  • the transparent conductive layer includes a pixel electrode and a drain, and a portion located under the second metal layer is described in detail as an example.
  • the source 32, the drain 33 and the gate 31 are three electrodes of the thin film transistor 3 on the array substrate, wherein the gate 31 can be located at the source 32 and the drain. Above the pole 33, we call it a top gate type array substrate; the gate 31 can also be located below the source 32 and the drain 33, which we call a bottom gate type array substrate.
  • the manufacturing method of the TN type array substrate provided by the embodiment of the present invention can be applied to these two types, and the two types will be separately described below in detail.
  • forming the TN-type array substrate includes, for example: Step S101: forming a first metal thin film on the transparent substrate, and forming a first metal layer on the transparent substrate by using a patterning process.
  • the material forming the first metal layer is preferably molybdenum.
  • the material for forming the first metal layer is not limited thereto, and the embodiment of the present invention is only described by taking such a material as an example.
  • it may be other conductive metal materials such as chromium, aluminum, and the like.
  • a metal film is formed on the transparent substrate by deposition, and the first metal layer is formed by a patterning process.
  • Step S102 forming a gate insulating layer on the transparent substrate.
  • the material forming the gate insulating layer is preferably SiNx (silicon nitride).
  • the material for forming the gate insulating layer is not limited thereto, and the embodiment of the present invention will be described by taking only such a material as an example. For example, it may be silica or the like.
  • a SiNx film is formed on the substrate by deposition to form a gate insulating layer.
  • Step S103 forming a semiconductor thin film on the transparent substrate, and forming an active layer on the transparent substrate by one patterning process.
  • Step S104 sequentially forming a transparent conductive film and a metal film on the transparent substrate, and forming a TFT channel region, a transparent conductive layer and a second metal layer on the transparent substrate by using a patterning process.
  • the material forming the transparent conductive layer is preferably ITO (Indium tin oxide), and the material forming the second metal layer is preferably molybdenum.
  • the material for forming the transparent conductive layer and the second metal layer is not limited thereto, and the embodiment of the present invention is described by taking only such a material as an example.
  • the transparent conductive film and the second metal film are formed by deposition.
  • the one-time patterning process comprises: a halftone mask process and a photoresist reflow process.
  • the photoresist reflow process comprises: using a photoresist having reflow characteristics, and heat-treating the photoresist to reflow by using a photoresist reflow characteristic.
  • the photoresist reflow process may be to heat a portion of the photoresist to produce a temperature rise reflow.
  • the photoresist of the thin film transistor region may be heat treated to be reflowed to the channel region.
  • Reflow refers to the flow of photoresist under the action of surface tension after melting during heat treatment.
  • the trench t/data lines are relatively narrow, the trenches on both sides of the channel/data lines will completely cover the trenches/data lines after reflow, especially at ⁇ 5um. , easier to fully cover.
  • the heating temperature for reflow generally is about 140, and the time varies depending on the thickness.
  • the embodiments according to the present invention are not limited to these specific numerical conditions, but may be arbitrarily selected depending on the actual situation.
  • step S101 forms a first metal thin film on the transparent substrate, and forming the first metal layer on the transparent substrate by using one patterning process includes, for example, the following steps:
  • Step S1011 a photoresist is coated on the substrate on which the first metal thin film is formed.
  • the photoresist is divided into a positive photoresist and a negative photoresist.
  • Negative glue is formed after the illumination to form an insoluble matter; on the contrary, it is a positive glue after it becomes a soluble substance after illumination.
  • the soluble insoluble is relative to a specific developer.
  • a photoresist is used as a positive photoresist as an example for detailed description.
  • Step S1012 exposing and developing the substrate by using a mask, and developing a photoresist completely remaining portion and a photoresist removing portion after development.
  • the mask is a common mask and is divided into a light transmitting region and an opaque region.
  • a region that is illuminated by the light-transmitting region forms a soluble substance; an unilluminated region forms an insoluble matter.
  • the photoresist can then be developed with a developer, and the lithography that needs to be removed
  • the glue is removed.
  • the developer is used to remove the areas of the photoresist that are illuminated, leaving areas of the photoresist that are not illuminated, i.e., photoresists corresponding to the gate, gate lines, and common electrode lines.
  • Step S1013 removing the metal film not covered with the photoresist.
  • the region where the metal film is not covered with the photoresist may be etched away by using an etching solution. Step S1014, peeling off the remaining photoresist.
  • the photoresist is stripped, and a first metal layer including gate lines, gate electrodes, and common electrode lines is formed on the substrate.
  • step S103 uses a patterning process to form an active layer on the transparent substrate, for example, including the following steps:
  • Step S1031 coating a photoresist on the semiconductor film.
  • Step S1032 exposing and developing the substrate by using a mask, and developing a photoresist completely remaining portion and a photoresist removing portion after development.
  • the exposure and development of the substrate by using a mask can be referred to the description of the above step S1012, and will not be described herein.
  • Step S1033 removing the semiconductor film not covered with the photoresist.
  • the region where the semiconductor film is not covered with the photoresist may be etched away by using an etching solution. Step S1034, peeling off the remaining photoresist.
  • the photoresist is peeled off to form an active layer on the substrate.
  • the above step S104 uses a patterning process to form the TFT channel region, the transparent conductive layer and the second metal layer on the transparent substrate, for example, including the following steps:
  • Step S1041 a photoresist is applied onto the substrate on which the transparent conductive film and the second metal film are formed.
  • Step S1042 exposing with a halftone mask, developing and etching the exposed substrate to form a TFT channel region.
  • Step S1043 using a photoresist reflow technique to cover the TFT channel region with a photoresist.
  • the photoresist is reflowed to the trench, i.e., covers the exposed semiconductor film at the trench, thereby protecting it from the subsequent step S1045.
  • the insulating layers are all non-metal.
  • the plasma-etched gate insulating film also etches the exposed semiconductor film. Therefore, the photoresist is required to further protect the exposed semiconductor film at the channel.
  • the photoresist in the channel region is thicker than the photoresist in the semi-reserved region of the photoresist.
  • Step S1044 Perform an ashing process on the photoresist and form a transparent conductive layer.
  • An ashing process is performed on the completely remaining portion of the photoresist and the semi-reserved portion of the photoresist, the semi-retained portion of the photoresist is removed, and the photoresist of the photoresist is completely retained.
  • the "ashing process” is to thin the photoresist as a whole.
  • the photoresist in the semi-retained portion of the photoresist is removed, and the photoresist remaining in the photoresist is thinned, but remains, as shown in FIG.
  • a second metal film located on the semi-retained portion of the photoresist is preferably removed by etching to expose the formed transparent conductive layer.
  • Step S1045 removing the exposed gate insulating film to expose at least the gate line in the gate terminal region.
  • the gate insulating film is preferably removed by a dry plasma etching method.
  • the exposed gate insulating film may not be removed, and the gate line of the gate terminal region may be connected to the driving circuit by providing a via hole in the gate insulating layer.
  • Step S1046 removing the remaining portion of the photoresist to form a second metal layer.
  • FIG. 11 it is a schematic view of a TN-type array substrate after photoresist stripping.
  • step S1042 is performed by using a halftone mask, and developing and etching the exposed substrate to form a TFT channel region includes, for example:
  • the substrate is exposed and developed by using a halftone mask, and after the development, a photoresist completely reserved portion, a photoresist semi-retained portion, and a photoresist completely removed portion are formed, wherein the photoresist is completely retained.
  • the photoresist semi-retaining portion at least corresponding to the pixel electrode region, the source and drain regions, and other regions of the photoresist are completely removed; or, the photoresist completely retained portion corresponds to at least the data line region and The photoresist region of the source region and the photoresist half-retaining portion corresponding to at least the pixel electrode region and the drain region and the other region is completely removed; or the photoresist completely remaining portion corresponds to at least the data line region and the drain region.
  • the photoresist semi-retaining portion completely removes at least the photoresist corresponding to the pixel electrode region and the source region, and the other regions; or, the photoresist completely remains at least corresponding to the data line region and the source/drain region, and the light Engraved semi-reserved At least a portion of the photoresist corresponding to the pixel electrode region and other regions is completely removed.
  • the photoresist completely reserved portion 101 corresponds to the data line region and the source region
  • the photoresist half-retained portion 102 corresponds to the pixel electrode region and the drain region, and the like.
  • the complete removal of the photoresist in the region is described in detail as an example. As shown in FIG.
  • the region where the photoresist is completely removed includes a channel region and a gate terminal region bb'.
  • the semi-reserved portion of the photoresist means that the thickness of the photoresist is smaller than the completely remaining portion of the photoresist, and is not limited to half of the thickness of the completely remaining portion of the photoresist.
  • the second metal thin film and the transparent conductive film may be removed by using an etching solution.
  • the active layer includes: a first sub-layer and a second sub-layer formed in sequence, wherein the first sub-layer is located below the second sub-layer as a semiconductor layer, and the second sub-layer is a conductor layer.
  • the active layer in the post-production process, in order to reduce the contact resistance between the active layer and the metal thin film layer or the transparent conductive thin film layer, the active layer is doped with a pentavalent element such as phosphorus, thereby forming a second sub-layer, due to the second sub- The layer is a conductor layer, so it is necessary to remove the second sub-layer of the active layer channel region leaving only the first sub-layer, as shown in FIG.
  • Step S201 sequentially forming a transparent conductive film and a second metal film on the transparent substrate, and using a patterning process on the transparent substrate A transparent conductive layer and a second metal layer are formed.
  • a transparent conductive film and a metal thin film are preferably formed on the transparent substrate by deposition.
  • Forming the transparent conductive layer and the second metal layer on the transparent substrate by using a patterning process in sequence includes the above steps S1041, step S1042, step S1043, step S1044, step S1045, and step S1046.
  • Step S202 forming a semiconductor thin film on the transparent substrate, and forming an active layer on the transparent substrate by using a patterning process.
  • a semiconductor thin film is formed on a transparent substrate, and an active layer is formed on the transparent substrate by a patterning process, which can be referred to the above step S103.
  • Step S203 forming a gate insulating layer on the transparent substrate.
  • the step S102 can be referred to by forming the gate insulating layer on the transparent substrate.
  • Step S204 forming a first metal thin film on the transparent substrate, and forming a first metal layer on the transparent substrate by using one patterning process.
  • the forming the first metal layer on the transparent substrate by using one patterning process includes, for example: Step S2031, applying a photoresist on the substrate on which the first metal film is formed.
  • Step S2032 exposing and developing the substrate by using a half gray scale or halftone mask, and forming a photoresist completely remaining portion, a photoresist semi-retaining portion and a photoresist completely removed portion after development, wherein the light
  • the photoresist completely retains a portion of the corresponding gate line, the gate electrode, the common electrode line region, and the region on both sides of the data line terminal region, the photoresist removal portion corresponding to the data line terminal region, and the photoresist of the other regions are semi-retained.
  • Step S2033 removing the first metal thin film and the gate insulating layer located in the terminal region of the data line.
  • Step S2034 performing heat treatment on the photoresist to return the photoresist to the data line terminal region.
  • Step S2035 performing an ashing process on the completely remaining portion of the photoresist and the semi-reserved portion of the photoresist, removing the semi-reserved portion of the photoresist, and the photoresist reflowed to the terminal portion of the data line remains.
  • Step S2036 removing the exposed first metal film.
  • Step S2037 peeling off the remaining photoresist.
  • the gate line on the first metal layer and the second metal layer are not on the data line of the data line terminal area.
  • the embodiment of the present invention provides a TN type array substrate, as shown in FIG. 11, comprising: a substrate 1 disposed at a first metal layer 11, a gate insulating layer 7, an active layer 8, a second metal layer 12, and a transparent conductive layer 13 on the substrate 1, wherein the second metal layer 12 and the transparent conductive layer 13 pass Formed by a patterning process, the transparent conductive layer 13 includes a portion under the second metal layer and a pixel electrode.
  • the second metal layer includes: a data line but does not include a source drain, and the transparent conductive layer further includes a source drain; thus, the second metal layer has no drain, and the pixel aperture ratio can be increased.
  • the second metal layer 12 includes: a data line and a source but no drain, the transparent conductive layer further includes a drain; and the conductive layer of the second metal layer is more transparent than the transparent conductive layer
  • the conductivity is good, and the second metal layer includes a source level, which can turn on the pixel electrode to achieve display. And there is no drain on the second metal layer, and the pixel aperture ratio can be increased.
  • the second metal layer includes: a data line and a drain but not a source, the transparent conductive layer further includes a source; since the conductivity of the second metal layer is better than the conductivity of the transparent conductive layer,
  • the two metal layers include a drain, which can turn on the pixel electrodes for display.
  • the second metal layer comprises: a data line and a source drain. This enables the conduction of the pixel electrode to be realized faster and realizes the display.
  • the data line has no gate insulating layer thereon.
  • the data line is directly connected to the circuit board in the terminal area without using a via hole, reducing the contact resistance between the data line and the circuit board, and reducing power consumption.
  • the first metal layer includes: a gate, a gate line, and a common electrode line, wherein, at least in the gate line terminal region, there is no gate insulating layer on the gate line, and the common electrode line and the transparent layer
  • the conductive layer forms a storage capacitor.
  • a gate for a top gate type TN type array substrate, since the gate line is located at the uppermost layer, the gate line is completely exposed; for the bottom gate type TN type array substrate, as shown in FIG. 11, at least at the gate line terminal The gate line 2 of the region is exposed. In this way, the gate line is directly connected to the circuit board in the terminal area without using a via hole, which reduces the contact resistance between the gate line and the circuit board, and reduces power consumption.
  • the common electrode line and the transparent conductive layer form a storage capacitor, and only between the common electrode line and the transparent conductive layer There is a gate insulating layer, which improves the storage capacitance compared to the prior art; and in the case of the same storage capacitor as in the prior art, the width of the common electrode line can be reduced, thereby increasing the aperture ratio of the pixel.
  • An embodiment of the present invention provides a display device, including any of the TN-type array substrates provided by the embodiments of the present invention.
  • the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital camera, a mobile phone, a tablet computer, or the like.

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Abstract

一种TN型阵列基板及其制作方法、显示装置，该TN型阵列基板的制作方法包括：在基板（1）上形成第一金属层（11）、栅绝缘层（7）、有源层（8）、第二金属层（12）以及透明导电层（13）的步骤，其中所述第一金属层（11）包括栅极（31），所述第二金属层（12）包括数据线（4），所述透明导电层（13）包括像素电极；其中，形成所述第二金属层（12）和所述透明导电层（13）包括：在基板（1）上依次形成透明导电薄膜和金属薄膜；对所述透明导电薄膜和所述金属薄膜进行一次构图工艺，形成TFT沟道区、透明导电层（13）和第二金属层（12）。

Description

TN型阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种 TN型阵列基板及其制作方法、 显示装置。 背景技术
在制造显示面板的过程中， 利用掩模板进行曝光是重要的步骤。 曝光不 但是液晶面板中最精密的步骤之一， 也是设备投资及运营费用最高的步骤之 一。 因此通过减少利用掩模板及曝光的次数， 降低制造成本及提高设备生产 力， 始终是显示面板制造的一种探索。
现有的 TN ( Twist Nematic, 扭曲向列）型显示面板包括阵列基板。 如图 1、 图 2所示， TN型显示面板的阵列基板包括： 透明基板 1、 依次设置在透 明基板 1上的第一金属层、 栅绝缘层 7、 有源层 8、 第二金属层、 钝化层 9 以及透明导电层。 第一金属层包括栅线 2和栅极 31 , 第二金属层包括数据线 4、 源极 32和漏极 33, 透明导电层包括像素电极 5。 如图 1所示， 栅线 2和 数据线 4交叉设置， 在栅线 2和数据线 4围成的区域形成有薄膜晶体管 3和 像素电极 5。 阵列基板还包括位于阵列基板边缘用于连接电路板的栅线端子 区和数据线端子区， 如图 3所示， 栅线端子区 bb' 的栅线 2通过在其上面的 栅绝缘层 7和钝化层 9上设置过孔而与电路板相连， 数据线端子区 cc' 的数 据线 4通过在其上面的钝化层 9上设置过孔而与电路板相连， 通过电路板控 制栅线和数据线的电压输入。
现有技术在制作阵列基板过程中， 第一金属层、 钝化层和像素电极层分 别利用一张普通掩模板经过一次曝光形成； 有源层和第二金属层利用半灰度 或半色调掩模板经过一次曝光形成。 即需要进行四次曝光， 其曝光次数多、 生产周期长、 成本高。 发明内容
本发明的一个实施例提供一种 TN型阵列基板的制作方法， 包括： 在基 板上形成第一金属层、 栅绝缘层、 有源层、 第二金属层以及透明导电层的步 骤， 其中， 所述第一金属层包括栅极， 所述第二金属层包括数据线， 所述透 明导电层包括像素电极；其中，形成所述第二金属层和所述透明导电层包括： 在基板上依次形成透明导电薄膜和金属薄膜；
对所述透明导电薄膜和所述金属薄膜进行一次构图工艺，形成 TFT沟道 区、 透明导电层和第二金属层。
在一个示例中， 所述第二金属层包括数据线但不包括源漏极， 所述透明 导电层包括像素电极、 源漏极， 以及位于所述第二金属层下方的部分； 或者， 所述第二金属层包括数据线和源极图案但不包括漏极， 所述透明导电层包括 像素电极和漏极， 以及位于所述第二金属层下方的部分； 或者， 所述第二金 属层包括数据线和漏极但不包括源极，所述透明导电层包括像素电极和源极， 以及位于所述第二金属层下方的部分； 或者， 所述第二金属层包括数据线和 源漏极， 所述透明导电层包括像素电极， 以及位于所述第二金属层下方的部 分。
在一个示例中， 所述一次构图工艺包括： 半色调掩模板工艺和光刻胶回 流工艺。
在一个示例中，所述光刻胶回流工艺包括：使用具有回流特性的光刻胶， 并对该光刻胶进行热处理， 使光刻胶进行回流。
在一个示例中， 利用所述一次构图工艺， 形成 TFT沟道区域、 透明导电 层和第二金属层包括：
在制作有透明导电薄膜和第二金属薄膜的基板上， 涂布光刻胶； 采用半色调掩模板进行曝光， 对曝光后的基板进行显影以形成光刻胶完 全保留区域、 光刻胶半保留区域和光刻胶完全去除区域， 所述光刻胶完全去 除区域至少对应于要形成 TFT沟道的区域， 进行刻蚀以形成 TFT沟道区域； 采用光刻胶回流技术使 TFT沟道区域两侧的光刻胶回流，使得光刻胶覆 盖所述 TFT沟道区域， 并且通过控制回流的时间和温度来控制 TFT沟道区 域光刻胶的厚度以使得 TFT 沟道区域的光刻胶厚度大于光刻胶半保留区域 的光刻 度；
对光刻胶进行灰化工艺， 以去除光刻胶半保留区域的光刻胶， 并形成透 明导电层；
去除露出的第二金属薄膜， 以形成第二金属层； 去除剩余部分的光刻胶。
在一个示例中， 所述光刻胶完全保留部分至少对应数据线区域、 光刻胶 半保留部分至少对应所述像素电极区域、 源漏极区域、 其他区域的光刻胶完 全去除； 或者， 所述光刻胶完全保留部分至少对应数据线区域和源极区域、 光刻胶半保留部分至少对应所述像素电极区域和漏极区域、 其他区域的光刻 胶完全去除； 或者， 所述光刻胶完全保留部分至少对应数据线区域和漏极区 域、 光刻胶半保留部分至少对应所述像素电极区域和源极区域、 其他区域的 光刻胶完全去除； 或者， 所述光刻胶完全保留部分至少对应数据线区域和源 漏极区域、 光刻胶半保留部分至少对应所述像素电极区域、 其他区域的光刻 胶完全去除。
在一个示例中， 在形成透明导电薄膜和第二金属薄膜之前， 所述第一金 属层、 所述栅绝缘层和所述有源层依次形成在所述基板上。
在一个示例中， 所述光刻胶完全去除区域还对应于栅线端子区， 在所述 去除剩余部分的光刻胶之前， 还包括： 去除露出的栅绝缘薄膜， 至少使位于 栅线端子区的栅线露出。
在一个示例中， 在形成第二金属层后还包括： 在基板上形成栅绝缘层和 第一金属层。
本发明的另一个实施例提供一种 TN型阵列基板的制作方法， 包括： 在 基板上形成第一金属层、 栅绝缘层、 有源层、 第二金属层以及透明导电层的 步骤，
其中， 所述第一金属层包括栅极， 所述第二金属层包括数据线和数据线 端子， 所述透明导电层包括像素电极， 且所述透明导电层、所述第二金属层、 所述有源层、 所述栅绝缘层和所述第一金属层依次形成在所述基板上，
其中， 形成第一金属层包括：
在基板上形成第一金属薄膜；
在所述第一金属薄膜上涂布光刻胶；
利用半灰度或半色调掩模板对所述基板进行曝光和显影， 显影后形成光 刻胶完全保留部分、 光刻胶半保留部分和光刻胶完全去除部分， 其中， 所述 光刻胶完全保留部分对应包括要形成栅极的区域以及数据线端子的区域两侧 的区域、 光刻胶完全去除部分对应数据线端子的区域、 其他区域的光刻胶半 保留。
去除位于数据线端子区域的第一金属薄膜和栅绝缘层；
对光刻胶实施热处理， 使光刻胶回流至数据线端子的区域；
对所述光刻胶完全保留部分和所述光刻胶半保留部分进行灰化工艺， 去 除所述光刻胶半保留部分， 且回流至数据线端子的区域的光刻胶仍然保留； 去除露出的第一金属薄膜， 以形成包括栅极的图形； 以及
将剩下的光刻胶去除， 以露出数据线端子。
本发明的另一个实施例提供一种 TN型阵列基板， 包括： 基板， 设置在 所述基板上的第一金属层、栅绝缘层、有源层、 第二金属层以及透明导电层， 其中， 所述第二金属层和所述透明导电层通过一次构图工艺形成， 所述透明 导电层包括位于第二金属层下方的部分和像素电极。
在一个示例中， 所述第二金属层包括： 数据线但不包括源漏极， 所述透 明导电层包括源漏极； 或者， 所述第二金属层包括： 数据线和源极但不包括 漏极， 所述透明导电层包括漏极； 或者， 所述第二金属层包括： 数据线和漏 极但不包括源极， 所述透明导电层还包括源极； 或者， 所述第二金属层包括： 数据线和源漏极。
在一个示例中， 所述阵列基板包括数据线端子区， 其中， 至少在数据线 端子区， 所述数据线上面无栅绝缘层。
在一个示例中， 所述阵列基板包括栅线端子区， 所述第一金属层包括： 栅极、 栅线和公共电极线， 其中， 至少在栅线端子区， 所述栅线上面无栅绝 缘层。
在一个示例中， 所述第一金属层、 所述栅绝缘层、 所述有源层、 所述透 明导电层以及所述第二金属层依次层叠在所述基板上。
本发明的再一个实施例提供一种显示装置， 包括如上所述任一 TN型阵 列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。 图 1为现有技术中的一种 TN型阵列基板局部俯视结构示意图； 图 2为图 1所示阵列基板的剖视示意图；
图 3为图 1所示阵列基板的栅线端子区和数据线端子区的剖视结构示意 图；
图 4为制作图 11所示 TN型阵列基板过程中 , 光刻胶显影后的示意图； 图 5为制作图 11所示 TN型阵列基板过程中 ,去除光刻胶完全去除部分 的金属薄膜和透明导电薄膜后的示意图；
图 6为制作图 11所示 TN型阵列基板过程中 ,去除半导体层中沟道区第 二子层后的示意图；
图 7为制作图 11所示 TN型阵列基板过程中 , 光刻胶回流后的示意图； 图 8为制作图 11所示 TN型阵列基板过程中 ,对光刻胶进行灰化处理后 的示意图；
图 9为制作图 11所示 TN型阵列基板过程中 ,去除光刻胶半保留部分的 金属薄膜后的示意图；
图 10为制作图 11所示 TN型阵列基板过程中， 去除栅绝缘层后的示意 图；
图 11为本发明实施例提供的一种 TN型阵列基板剖视结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供了一种 TN型阵列基板的制作方法， 包括： 在基板 上形成第一金属层、栅绝缘层、有源层、 第二金属层以及透明导电层的步骤， 其中， 所述第一金属层包括栅极， 所述第二金属层包括数据线， 所述透明导 电层包括： 像素电极； 其中， 形成所述第二金属层和所述透明导电层例如包 括：
在基板上依次形成透明导电薄膜和金属薄膜； 利用一次构图工艺， 形成 TFT沟道区、 透明导电层和第二金属层。
在本发明所有实施例中， 需要阐明 "薄膜" 、 "层" 以及 "图案" 的定 义， 以及之间的关系。 其中， "薄膜" 是指利用某一种材料在基板上利用沉 积或其他工艺制作出的一层薄膜。 若在整个制作过程当中该 "薄膜" 无需构 图工艺， 则该 "薄膜"还可以称为 "层" ； 若在整个制作过程当中该 "薄膜" 还需构图工艺， 则在构图工艺前称为 "薄膜" ， 构图工艺后称为 "层" 。 经 过构图工艺后的 "层" 中包含至少一个薄膜 "图案" 。
示例的， 上述的栅绝缘层可以是在透明基板上沉积 SiNx (氮化硅）薄膜 所制得的。 栅绝缘层一般无需构图工艺。 又示例的， 半导体层是半导体薄膜 经构图工艺后形成的。 第一金属层是金属薄膜经构图工艺后形成的， 包括栅 极、 栅线和公共电极线。 其中， 栅极、 栅线和公共电极线即为薄膜 "图案" 。 第二金属层是金属薄膜经构图工艺后形成的， 包括数据线。 透明导电层是透 明导电薄膜经构图工艺后形成的， 包括像素电极。
所谓 "构图工艺" 是将薄膜形成包含至少一个图案的层的工艺； 本发明 的实施例中所提到的构图工艺包含： 在薄膜上涂胶， 利用掩模板对所述光刻 胶进行曝光， 再利用显影液将需去除的光刻胶沖蚀掉， 再刻蚀掉未覆盖光刻 胶的薄膜部分， 最后将剩下的光刻胶剥离。
本发明实施例提供了一种 TN型阵列基板的制作方法， 利用一次构图工 艺形成第一金属层； 利用一次构图工艺形成有源层； 利用一次构图工艺， 形 成透明导电层和第二金属层， 而无需钝化层， 相对于现有技术， 减少了构图 工艺的次数， 缩短了生产周期、 降低了成本。
可选的， 所述第二金属层包括数据线但不包括源漏极， 相应的， 所述透 明导电层包括像素电极、 源漏极， 以及位于所述第二金属层下方的部分； 这 样， 第二金属层上无漏极， 可以增大像素开口率。
或者， 所述第二金属层包括数据线和源极但不包括漏极， 相应的， 所述 透明导电层包括像素电极和漏极， 以及位于所述第二金属层下方的部分； 这 样， 第二金属层上无漏极， 可以增大像素开口率。
或者， 所述第二金属层包括数据线和漏极但不包括源极， 相应的， 所述 透明导电层包括像素电极和源极， 以及位于所述第二金属层下方的部分； 由 于第二金属层的导电性比透明导电层的导电性好， 则第二金属层包括源级， 可以更快的导通像素电极实现显示。 且第二金属层上无漏极， 可以增大像素 开口率。
或者， 所述第二金属层包括数据线和源漏极， 相应的， 所述透明导电层 包括像素电极， 以及位于所述第二金属层下方的部分。
需要说明的是， 第二金属层和透明导电层为以上四种情况时均在本发明 的保护范围之内， 本发明附图实施例仅以所述第二金属层包括数据线和源极 且不包括漏极， 所述透明导电层包括像素电极和漏极， 以及位于所述第二金 属层下方的部分为例进行详细说明。
需要说明的是， 如图 1、 图 2所示， 源极 32、 漏极 33和栅极 31是阵列 基板上的薄膜晶体管 3的三个电极， 其中， 栅极 31可以位于源极 32和漏极 33的上面， 我们称之为顶栅型阵列基板； 栅极 31也可以位于源极 32和漏极 33的下面， 我们称之为底栅型阵列基板。 本发明实施例提供的 TN型阵列基 板的制作方法可适用于这两种类型， 下面也将对这两种类型分别进行详细说 明。
当栅极位于源漏极的下面， 形成所述 TN型阵列基板例如包括： 步骤 S101、 在透明基板上形成第一金属薄膜， 利用一次构图工艺， 在所 述透明基板上形成第一金属层。
例如， 形成所述第一金属层的材料优选采用钼。 当然形成所述第一金属 层的材料也不局限于此， 本发明实施例仅以这种材料为例进行说明。 例如也 可以是其他导电金属材料， 如铬、 铝等。 并利用沉积的方式在透明基板上形 成一层金属薄膜， 并利用一次构图工艺形成第一金属层。
步骤 S102、 在透明基板上形成栅绝缘层。
例如， 形成所述栅绝缘层的材料优选采用 SiNx (氮化硅）。 当然形成所 述栅绝缘层的材料也不局限于此，本发明实施例仅以这种材料为例进行说明。 例如还可以是二氧化硅等。 并利用沉积的方式在所述基板上形成 SiNx薄膜， 形成栅绝缘层。
步骤 S103、 在透明基板上形成半导体薄膜， 并利用一次构图工艺， 在所 述透明基板上形成有源层。
例如， 在所述基板上利用沉积的方式形成半导体薄膜， 经过一次构图工 艺形成所述有源层。 步骤 S104、在透明基板上依次形成透明导电薄膜和金属薄膜， 并利用一 次构图工艺，在所述透明基板上形成 TFT沟道区、透明导电层和第二金属层。
例如， 形成所述透明导电层的材料优选采用 ITO ( Indium tin oxide, 氧 化铟锡） ， 形成所述第二金属层的材料优选采用钼。 当然， 形成所述透明导 电层和第二金属层的材料也不局限于此， 本发明实施例仅以这种材料为例进 行说明。 且优选采用沉积的方式形成所述透明导电薄膜和第二金属薄膜。
可选的，所述一次构图工艺包括： 半色调掩模板工艺和光刻胶回流工艺。 且所述光刻胶回流工艺包括： 使用具有回流特性的光刻胶， 并对光刻胶进行 加热处理， 利用光刻胶回流特性使其回流。 例如， 光刻胶回流工艺可以是对 光刻胶的局部进行加热， 产生升温回流。 例如可以是对薄膜晶体管区域的光 刻胶进行热处理， 使其回流至沟道区域。 当然， 也可以是对基板上的一层光 刻胶进行热处理。 回流是指光刻胶在热处理过程中熔化后在表面张力的作用 下流动。 虽然基板上所有加热区域都会有回流现象， 但由于沟t/数据线比较 窄， 沟道 /数据线两侧的光刻胶回流后就会将沟 t/数据线完全覆盖， 尤其在 <5um 时， 更容易全覆盖。 在控制温度和时间的情况下， 可以控制回流的光 刻胶厚度，一般进行回流的加热温度在 140左右，时间根据厚度不同而不同。 但根据本发明的实施例不限制于这些具体的数值条件， 而是可以根据实际情 况任意选择。
例如， 上述步骤 S101 在透明基板上形成第一金属薄膜， 利用一次构图 工艺， 在所述透明基板上形成第一金属层例如包括以下步骤：
步骤 S1011、 在制作有第一金属薄膜的基板上涂布光刻胶。
其中， 所述光刻胶分为正性光刻胶和负性光刻胶。 光照后形成不可溶物 质的是负性胶； 反之， 光照后变成可溶物质的即为正性胶。 其中， 所述可溶 不可溶是相对于特定的显影液而言。 本发明实施例中以光刻胶为正性光刻胶 为例进行详细说明。
步骤 S1012、 利用掩模板对所述基板进行曝光和显影， 显影后形成光刻 胶完全保留部分和光刻胶去除部分。
例如， 所述掩模板为普通掩模板， 分为透光区和不透光区。 对于正性光 刻胶而言， 经透光区被光照的区域， 形成可溶性物质； 未被光照的区域， 形 成不可溶型物质。 然后可利用显影液对光刻胶进行显影， 将需要去除的光刻 胶去除掉。 例如， 利用显影液将光刻胶被光照的区域去除掉， 留下光刻胶未 被光照的区域， 即对应栅极、 栅线和公共电极线的光刻胶。
步骤 S1013、 去除未覆盖光刻胶的金属薄膜。
例如， 可以是利用刻蚀液将金属薄膜未覆盖光刻胶的区域刻蚀掉。 步骤 S1014、 将剩下的光刻胶剥离。
将光刻胶剥离， 在村底基板上形成包括栅线、 栅极和公共电极线的第一 金属层。
例如， 上述步骤 S103 利用一次构图工艺， 在所述透明基板上形成有源 层例如包括以下步骤：
步骤 S1031、 在所述半导体薄膜上涂布光刻胶。
对于光刻胶的具体描述， 可参照上述步骤 S1011 , 在这里不作赘述。 步骤 S1032、 利用掩模板对所述基板进行曝光和显影， 显影后形成光刻 胶完全保留部分和光刻胶去除部分。
例如， 利用掩模板对所述基板进行曝光和显影可参照上述步骤 S1012的 描述， 在这里不作赘述。
步骤 S1033、 去除未覆盖光刻胶的半导体薄膜。
例如， 可以是利用刻蚀液将半导体薄膜未覆盖光刻胶的区域刻蚀掉。 步骤 S1034、 将剩下的光刻胶剥离。
将光刻胶剥离， 在所述基板上形成有源层。
例如， 上述步骤 S104利用一次构图工艺， 在透明基板上形成 TFT沟道 区、 透明导电层和第二金属层例如包括以下步骤：
步骤 S1041、 在制作有透明导电薄膜和第二金属薄膜的基板上， 涂布光 刻胶。
其中， 对于光刻胶的描述可参照上述步骤 S1012, 在这里不作赘述。 步骤 S1042、 采用半色调掩模板进行曝光， 对曝光后的基板进行显影和 刻蚀形成 TFT沟道区域。
如图 4-图 5所示， 例如可参照下面步骤 S10421-步骤 S10423。
步骤 S1043、 采用光刻胶回流技术使光刻胶覆盖所述 TFT沟道区域。 如图 7所示， 光刻胶回流至沟道， 即覆盖沟道处露出的半导体薄膜， 进 而对其形成保护， 而不受后面步骤 S1045的影响。 例如， 由于半导体层和栅 绝缘层均为非金属， 采用等离子体刻蚀栅绝缘薄膜也会刻蚀棵露出来的半导 体薄膜， 因此需要光刻胶进一步保护沟道处露出的半导体薄膜。 另外， 通过 控制回流温度和时间， 在回流之后， 沟道区域的光刻胶比光刻胶半保留区域 的光刻胶厚。
步骤 S1044、 对光刻胶进行灰化工艺， 并形成透明导电层。
对光刻胶完全保留部分和光刻胶半保留部分进行灰化工艺， 去除所述光 刻胶半保留部分， 且光刻胶完全保留部分的光刻胶变薄。
例如， 所述 "灰化工艺" ， 即将光刻胶整体打薄。 这样， 光刻胶半保留 部分的光刻胶被去除， 光刻胶完全保留部分的光刻胶变薄， 但仍然保留， 如 图 8所示。
如图 9所示， 在对所述光刻胶进行灰化工艺之后， 优选的采用刻蚀的方 法去除位于光刻胶半保留部分的第二金属薄膜， 露出所形成的透明导电层。
步骤 S1045、 去除露出的栅绝缘薄膜， 至少使位于栅线端子区的栅线露 出。
如图 10所示，优选采用干法等离子体刻蚀的方法去除栅绝缘薄膜。 当然 也可以不去除露出的栅绝缘薄膜， 进而栅线端子区的栅线可以通过在栅绝缘 层设置过孔与驱动电路连接。
步骤 S1046、 去除剩余部分的光刻胶， 形成第二金属层。
如图 11所示， 为光刻胶剥离后的 TN型阵列基板的示意图。
例如， 上述步骤 S1042采用半色调掩模板进行曝光， 对曝光后的基板进 行显影和刻蚀形成 TFT沟道区域例如包括：
S10421、 采用半色调掩模板对所述基板进行曝光和显影， 显影后形成光 刻胶完全保留部分、 光刻胶半保留部分和光刻胶完全去除部分， 其中， 所述 光刻胶完全保留部分至少对应数据线区域、 光刻胶半保留部分至少对应所述 像素电极区域、 源漏极区域、 其他区域的光刻胶完全去除； 或者， 所述光刻 胶完全保留部分至少对应数据线区域和源极区域、 光刻胶半保留部分至少对 应所述像素电极区域和漏极区域、 其他区域的光刻胶完全去除； 或者， 所述 光刻胶完全保留部分至少对应数据线区域和漏极区域、 光刻胶半保留部分至 少对应所述像素电极区域和源极区域、 其他区域的光刻胶完全去除； 或者， 所述光刻胶完全保留部分至少对应数据线区域和源漏极区域、 光刻胶半保留 部分至少对应所述像素电极区域、其他区域的光刻胶完全去除。如图 4所示， 本发明实施例附图以所述光刻胶完全保留部分 101对应数据线区域和源极区 域、 光刻胶半保留部分 102对应所述像素电极区域和漏极区域、 其他区域的 光刻胶完全去除为例进行详细说明， 其中， 如图 4所示， 光刻胶被完全去除 的区域包括沟道区以及栅极端子区 bb' 。 需要说明的是， 本发明实施例中， 光刻胶半保留部分是指光刻胶的厚度小于光刻胶完全保留部分， 而不仅限于 是光刻胶完全保留部分厚度的一半。
510422、 去除位于光刻胶完全去除部分的第二金属薄膜和透明导电薄 膜。
如图 5所示， 例如可以是利用刻蚀液将第二金属薄膜和透明导电薄膜去 除。
510423、 去除沟道区域露出的第二子层。
例如， 所述有源层包括： 依次形成的第一子层和第二子层， 其中， 第一 子层位于第二子层的下面为半导体层， 第二子层为导体层。 例如， 有源层在 后期制作过程中， 为了降低有源层与金属薄膜层或透明导电薄膜层的接触电 阻， 掺杂了磷等五价元素， 因此形成了第二子层， 由于第二子层为导体层， 因此需要将有源层沟道区域的第二子层去除，只留下第一子层，如图 6所示。
当栅极位于源漏极的上面， 形成所述 TN型阵列基板例如包括： 步骤 S201、在透明基板上依次形成透明导电薄膜和第二金属薄膜， 并利 用一次构图工艺， 在所述透明基板上形成透明导电层和第二金属层。
例如，在透明基板上优选采用沉积的方式形成透明导电薄膜和金属薄膜。 利用一次构图工艺， 在所述透明基板上形成透明导电层和第二金属层依次包 括上述步骤 S 1041、 步骤 S1042、 步骤 S1043、 步骤 S1044、 步骤 S 1045和 步骤 S1046。
步骤 S202、 在透明基板上形成半导体薄膜， 并利用一次构图工艺， 在所 述透明基板上形成有源层。
例如， 在透明基板上形成半导体薄膜， 并利用一次构图工艺， 在所述透 明基板上形成有源层可参照上述步骤 S103。
步骤 S203、 在透明基板上形成栅绝缘层。
例如， 在透明基板上形成栅绝缘层可参照上述步骤 S102。 步骤 S204、 在透明基板上形成第一金属薄膜， 利用一次构图工艺， 在所 述透明基板上形成第一金属层。
其中，利用一次构图工艺，在所述透明基板上形成第一金属层例如包括： 步骤 S2031、 在制作有所述第一金属薄膜的基板上涂布光刻胶。
步骤 S2032、 利用半灰度或半色调掩模板对所述基板进行曝光和显影， 显影后形成光刻胶完全保留部分、光刻胶半保留部分和光刻胶完全去除部分， 其中， 所述光刻胶完全保留部分对应栅线、 栅极、 公共电极线区域以及数据 线端子区两侧的区域、 光刻胶去除部分对应数据线端子区、 其他区域的光刻 胶半保留。
步骤 S2033、 去除位于数据线端子区的第一金属薄膜和栅绝缘层。
步骤 S2034、 对光刻胶实施热处理， 使光刻胶回流至数据线端子区。 步骤 S2035、 对所述光刻胶完全保留部分和所述光刻胶半保留部分进行 灰化工艺， 去除所述光刻胶半保留部分， 且回流至数据线端子区的光刻胶仍 然保留。
步骤 S2036、 去除露出的第一金属薄膜。
步骤 S2037、 将剩下的光刻胶剥离。
则第一金属层上的栅线和第二金属层至少数据线端子区的数据线上面无 本发明实施例提供了一种 TN型阵列基板，如图 11所示， 包括： 基板 1 , 设置在所述基板 1上的第一金属层 11、 栅绝缘层 7、 有源层 8、 第二金属层 12以及透明导电层 13,其中，所述第二金属层 12和所述透明导电层 13通过 一次构图工艺形成，所述透明导电层 13包括位于所述第二金属层下方的部分 和像素电极。
例如， 所述第二金属层包括： 数据线但不包括源漏极， 所述透明导电层 还包括源漏极； 这样， 第二金属层上无漏极， 可以增大像素开口率。
或者， 如图 11所示， 所述第二金属层 12包括： 数据线和源极但不包括 漏极， 所述透明导电层还包括漏极； 由于第二金属层的导电性比透明导电层 的导电性好， 则第二金属层包括源级， 可以更快的导通像素电极实现显示。 且第二金属层上无漏极， 可以增大像素开口率。 本发明实施例的附图仅以这 一种为例。 或者， 所述第二金属层包括： 数据线和漏极但不包括源极， 所述透明导 电层还包括源极； 由于第二金属层的导电性比透明导电层的导电性好， 则第 二金属层包括漏极， 可以更快的导通像素电极实现显示。
或者， 所述第二金属层包括： 数据线和源漏极。 这样可以更快的实现像 素电极的导通， 实现显示。
可选的， 至少在数据线端子区， 所述数据线上面无栅绝缘层。 例如， 如 图 11所示， 对于底栅型的 TN型阵列基板， 由于数据线 4位于最上面一层， 则所述数据线 4完全露出； 对于顶栅型的 TN型阵列基板， 至少在数据线端 子区的数据线露出。 这样，数据线在端子区直接与电路板相连， 而无需过孔， 减小数据线与电路板之间的接触电阻， 降低了功耗。
可选的， 所述第一金属层包括： 栅极、 栅线和公共电极线， 其中， 至少 在栅线端子区， 所述栅线上面无栅绝缘层， 所述公共电极线与所述透明导电 层形成存储电容。 例如， 对于顶栅型的 TN型阵列基板， 由于栅线位于最上 面一层，则所述栅线完全露出；对于底栅型的 TN型阵列基板，如图 11所示， 至少在栅线端子区的栅线 2露出。 这样， 栅线在端子区直接与电路板相连， 而无需过孔， 减小了栅线与电路板之间的接触电阻， 降低了功耗。
且无论是底栅型的 TN型阵列基板还是顶栅型的 TN型阵列基板， 所述 公共电极线与所述透明导电层形成存储电容， 且在公共电极线与所述透明导 电层之间只存在栅绝缘层， 相对于现有技术， 提高了存储电容； 且在与现有 技术存储电容相同的情况下， 可以减小公共电极线的宽度， 进而提高像素的 开口率。
本发明的实施例提供了一种显示装置， 包括本发明实施例提供的任一所 述的 TN型阵列基板。 其中， 所述显示装置可以为液晶显示器、 液晶电视、 数码相机、 手机、 平板电脑等任何具有显示功能的产品或者部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种 TN型阵列基板的制作方法， 包括： 在基板上形成第一金属层、 栅绝缘层、 有源层、 第二金属层以及透明导电层的步骤， 其中， 所述第一金 属层包括栅极，所述第二金属层包括数据线，所述透明导电层包括像素电极； 其中， 形成所述第二金属层和所述透明导电层包括：
在基板上依次形成透明导电薄膜和金属薄膜；
对所述透明导电薄膜和所述金属薄膜进行一次构图工艺，形成 TFT沟道 区、 透明导电层和第二金属层。
2、 根据权利要求 1所述的方法， 其中，
所述第二金属层包括数据线但不包括源漏极， 所述透明导电层包括像素 电极、 源漏极， 以及位于所述第二金属层下方的部分； 或者，
所述第二金属层包括数据线和源极图案但不包括漏极， 所述透明导电层 包括像素电极和漏极， 以及位于所述第二金属层下方的部分； 或者，
所述第二金属层包括数据线和漏极但不包括源极， 所述透明导电层包括 像素电极和源极， 以及位于所述第二金属层下方的部分； 或者，
所述第二金属层包括数据线和源漏极， 所述透明导电层包括像素电极， 以及位于所述第二金属层下方的部分。
3、 根据权利要求 1或 2所述的方法， 其中， 所述一次构图工艺包括： 半 色调掩模板工艺和光刻胶回流工艺。
4、 根据权利要求 3所述的方法， 其中， 所述光刻胶回流工艺包括： 使用 具有回流特性的光刻胶， 并对光刻胶进行热处理， 使光刻胶回流。
5、 根据权利要求 3或 4所述的方法， 其中， 利用所述一次构图工艺， 形 成 TFT沟道区域、 透明导电层和第二金属层包括：
在制作有透明导电薄膜和第二金属薄膜的基板上， 涂布光刻胶； 采用半色调掩模板进行曝光， 对曝光后的基板进行显影以形成光刻胶完 全保留区域、 光刻胶半保留区域和光刻胶完全去除区域， 所述光刻胶完全去 除区域至少对应于要形成 TFT沟道的区域， 进行刻蚀以形成 TFT沟道区域； 采用光刻胶回流技术使 TFT沟道区域两侧的光刻胶回流，使得光刻胶覆 盖所述 TFT沟道区域， 并且通过控制回流的时间和温度来控制 TFT沟道区 域光刻胶的厚度以使得 TFT沟道区域的光刻胶厚度大于光刻胶半保留区域 的光刻 度；
对光刻胶进行灰化工艺， 以去除光刻胶半保留区域的光刻胶， 并形成透 明导电层；
去除露出的第二金属薄膜， 以形成第二金属层；
去除剩余部分的光刻胶。
6、 根据权利要求 5所述的方法， 其中，
所述光刻胶完全保留部分至少对应数据线区域、 光刻胶半保留部分至少 对应所述像素电极区域、 源漏极区域、 其他区域的光刻胶完全去除； 或者， 所述光刻胶完全保留部分至少对应数据线区域和源极区域、 光刻胶半保留部 分至少对应所述像素电极区域和漏极区域、 其他区域的光刻胶完全去除； 或 者， 所述光刻胶完全保留部分至少对应数据线区域和漏极区域、 光刻胶半保 留部分至少对应所述像素电极区域和源极区域、其他区域的光刻胶完全去除； 或者， 所述光刻胶完全保留部分至少对应数据线区域和源漏极区域、 光刻胶 半保留部分至少对应所述像素电极区域、 其他区域的光刻胶完全去除。
7、根据权利要求 5所述的方法， 其中， 在形成透明导电薄膜和第二金属 薄膜之前， 所述第一金属层、 所述栅绝缘层和所述有源层依次形成在所述基 板上。
8、根据权利要求 5所述的方法， 其中， 所述光刻胶完全去除区域还对应 于栅线端子区， 在所述去除剩余部分的光刻胶之前， 该方法还包括： 去除露 出的栅绝缘薄膜， 至少使位于栅线端子区的栅线露出。
9、 根据权利要求 5所述的方法， 其中， 在形成第二金属层后还包括： 在 基板上形成栅绝缘层和第一金属层。
10、 一种 TN型阵列基板的制作方法， 包括： 在基板上形成第一金属层、 栅绝缘层、 有源层、 第二金属层以及透明导电层的步骤，
其中， 所述第一金属层包括栅极， 所述第二金属层包括数据线和数据线 端子， 所述透明导电层包括像素电极， 且所述透明导电层、所述第二金属层、 所述有源层、 所述栅绝缘层和所述第一金属层依次形成在所述基板上，
其中， 形成第一金属层包括：
在基板上形成第一金属薄膜； 在所述第一金属薄膜上涂布光刻胶；
利用半灰度或半色调掩模板对所述基板进行曝光和显影， 显影后形成光 刻胶完全保留部分、 光刻胶半保留部分和光刻胶完全去除部分， 其中， 所述 光刻胶完全保留部分对应包括要形成栅极的区域以及数据线端子的区域两侧 的区域、 光刻胶完全去除部分对应数据线端子的区域、 其他区域的光刻胶半 保留。
去除位于数据线端子区域的第一金属薄膜和栅绝缘层；
对光刻胶实施热处理， 使光刻胶回流至数据线端子的区域；
对所述光刻胶完全保留部分和所述光刻胶半保留部分进行灰化工艺， 去 除所述光刻胶半保留部分， 且回流至数据线端子的区域的光刻胶仍然保留； 去除露出的第一金属薄膜， 以形成包括栅极的图形； 以及
将剩下的光刻胶去除， 以露出数据线端子。
11、 一种 TN型阵列基板， 包括： 基板， 设置在所述基板上的第一金属 层、 栅绝缘层、 有源层、 第二金属层以及透明导电层， 其中， 所述第二金属 层和所述透明导电层通过一次构图工艺形成， 所述透明导电层包括位于第二 金属层下方的部分和像素电极。
12、 根据权利要求 11所述的 TN型阵列基板， 其中， 所述第二金属层包 括： 数据线但不包括源漏极， 所述透明导电层包括源漏极； 或者，
所述第二金属层包括： 数据线和源极但不包括漏极， 所述透明导电层包 括漏极； 或者，
所述第二金属层包括： 数据线和漏极但不包括源极， 所述透明导电层还 包括源极； 或者，
所述第二金属层包括： 数据线和源漏极。
13、 根据权利要求 12所述的 TN型阵列基板， 其中， 所述阵列基板包括 数据线端子区， 其中， 至少在数据线端子区， 所述数据线上面无栅绝缘层。
14、 根据权利要求 11-13中任一项所述的 TN型阵列基板， 其中， 所述 阵列基板包括栅线端子区， 所述第一金属层包括： 栅极、栅线和公共电极线， 其中， 至少在栅线端子区， 所述栅线上面无栅绝缘层。
15、 根据权利要求 11-14中任一项所述的 TN型阵列基板， 其中， 所述 第一金属层、 所述栅绝缘层、 所述有源层、 所述透明导电层以及所述第二金 属层依次层叠在所述基板上。
16、 一种显示装置， 包括权利要求 11-15任一项所述的 TN型阵列基板。
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