CN103872139B - 薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

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CN103872139B
CN103872139B CN201410062722.XA CN201410062722A CN103872139B CN 103872139 B CN103872139 B CN 103872139B CN 201410062722 A CN201410062722 A CN 201410062722A CN 103872139 B CN103872139 B CN 103872139B
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张金中
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种薄膜晶体管,该薄膜晶体管的有源层包括交替层叠设置的多层有源半导体子层和的多层绝缘隔离子层,所述薄膜晶体管的源极和漏极与所述多层有源半导体子层导电连接。相应地,本发明还提供一种薄膜晶体管的制作方法,以及一种阵列基板和显示装置。本发明能够有效地增加薄膜晶体管中有源层的沟道电流,能够弥补有源层载流子迁移率较低导致的沟道电流较小的问题。

Description

薄膜晶体管及其制作方法、阵列基板和显示装置
技术领域
本发明涉及显示技术领域,尤其涉及一种薄膜晶体管及其制作方法、阵列基板和显示装置。
背景技术
现有的TFT(Thin Film Transistor,薄膜场效应晶体管)阵列基板中,通常采用氢化非晶硅(A-Si:H)为材料制作薄膜晶体管的有源层。A-Si:H具有均匀性好,可大面积沉积,薄膜稳定性好等优点,然而A-Si:H制成的有源层的载流子迁移率较低。由于A-Si:H中的缺陷数目较多,导致在TFT阵列基板中,栅极所吸引的大部分电荷被攫取在缺陷中而无法提供导电能力,使得有源层的载流子迁移率仅有不到1cm2/(V*s),导致沟道电流较小,难以满足一些高性能显示器件的要求。
现有的方法中,采用低温多晶硅材料或非晶IGZO(indiumgallium zinc oxide,铟镓锌氧化物)制成的有源层可以具有较高的迁移率,但是低温多晶硅的制作工艺复杂,制作成本较高,且低温多晶硅难以达到全面稳定的晶化,均匀性和稳定性较差,而非晶IGZO的制作成本较高,且工艺不够成熟,良率比较低。
发明内容
有鉴于此,本发明的目的在于提供一种薄膜晶体管及其制作方法、阵列基板和显示装置,以增加薄膜晶体管中有源层的沟道电流。
为实现上述目的,本发明提供一种薄膜晶体管,所述薄膜晶体管的有源层包括交替层叠设置的多层有源半导体子层和多层绝缘隔离子层,所述薄膜晶体管的源极和漏极与所述多层有源半导体子层导电连接。
优选地,所述薄膜晶体管包括欧姆接触层,所述欧姆接触层形成在所述有源层上,且所述有源层沿厚度方向上窄下宽,所述欧姆接触层和所述多层有源半导体子层接触,所述源极和所述漏极形成在所述欧姆接触层上。
优选地,有源半导体子层的材料包括非晶硅。
优选地,绝缘隔离子层的材料包括硅的氧化物和/或硅的氮化物。
优选地,每层所述有源半导体子层的厚度为每层所述绝缘隔离子层的厚度为
优选地,所述多层有源半导体子层和绝缘隔离子层的致密性从上至下逐渐增加。
相应地,本发明还提供一种阵列基板,所述阵列基板包括上述本发明所提供的薄膜晶体管。
相应地,本发明还提供一种薄膜晶体管的制作方法,该制作方法包括形成薄膜晶体管的有源层的步骤和形成薄膜晶体管源极和漏极的步骤,所述形成薄膜晶体管的有源层的步骤包括:
交替沉积有源半导体膜层和绝缘隔离膜层;
利用构图工艺形成包括所述有源层的图形,使得所述有源层沿厚度方向上窄下宽。
优选地,交替沉积多层有源半导体膜层和绝缘隔离膜层时,通过控制沉积气压和气体流量使所述多层有源半导体膜层和绝缘隔离膜层的致密性从上至下逐渐增加。
优选地,所述利用构图工艺形成包括所述有源层的图形,使得所述有源层沿厚度方向上窄下宽,具体为:
在交替沉积的且致密性从上至下逐渐增加的有源半导体膜层和绝缘隔离膜层上涂覆光刻胶,并对光刻胶进行曝光和显影,以形成对应于有源层的图形,之后根据该图形进行刻蚀,以形成包括有源层的图形,所述有源层沿厚度方向上窄下宽。
优选地,在所述形成薄膜晶体管的有源层的步骤和所述形成薄膜晶体管的源极和漏极的步骤之间,还包括:
在所述有源层上形成欧姆接触层,且所述欧姆接触层与所述多层有源半导体子层接触;
所述形成薄膜晶体管的源极和漏极的步骤包括:
在所述欧姆接触层上形成所述源极和所述漏极。
相应地,本发明还提供一种显示装置,所述显示装置包括上述本发明所提供的阵列装置。
可以看出,本发明通过在薄膜晶体管中形成包括多层互相交替的有源半导体子层和绝缘隔离子层,能够在薄膜晶体管中形成多个通道,从而能够增加沟道电流,以弥补有源层载流子迁移率较低导致的沟道电流较小的问题。与现有技术相比,本发明工艺复杂度较低,能够有效节约成本。
附图说明
附图是用来提供对本发明的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本发明,但并不构成对本发明的限制。在附图中:
图1为本发明实施例所提供的薄膜晶体管示例图;
图2为图1中a部分示例图;
图3为本发明实施例所提供的薄膜晶体管另一示例图;
图4为本发明实施例所提供的阵列基板示例图;
图5为本发明实施例所提供的有源半导体膜层和绝缘隔离膜层交替沉积的示例图;
图6为本发明实施例所提供的多层有源半导体子层和绝缘隔离子层结构示例图。
附图标记说明
10-有源层;11-有源半导体子层;12-绝缘隔离子层;13-有源半导体膜层;14-绝缘隔离膜层;15-沟道;20-源极;30-漏极;40-栅极;41-栅极绝缘层;50-欧姆接触层;60-基板;71-像素电极;72-钝化层;73-公共电极。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明,并不用于限制本发明。
作为本发明的一个方面,提供一种薄膜晶体管,如图1所示,该薄膜晶体管的有源层10可以包括交替层叠设置的多层有源半导体子层11和多层绝缘隔离子层12,该薄膜晶体管的源极20和漏极30可以与多层有源半导体子层11导电连接。
具体地,如图1所示,该薄膜晶体管可以包括基板60以及在基板60上形成的栅极40和栅极绝缘层41。有源层10可以形成在栅极绝缘层41上,且有源层10可以包括多层有源半导体子层11和与多层有源半导体子层11交替层叠设置的多层绝缘隔离子层12,而源极20和漏极30可以分别和多层有源半导体子层11导电连接。需要说明的是,上述有源层10所包括的多层结构中,最下层或最上层可以为有源半导体子层11,也可以为绝缘隔离子层12。优选地,最下层可以设置为有源半导体子层11,最上层可以设置为绝缘隔离子层12,以保护下方的有源半导体子层11,该有源半导体子层11和绝缘隔离子层12形成的层叠结构只要能形成多个有源半导体子层11的界面即可
现有的薄膜晶体管通常采用单沟道模式,即只设置有一层有源层。在这样的单沟道模式下,产生沟道电流的位置仅在有源层中与栅极绝缘层交界处约左右的范围内,并且沟道电流与有源层缺陷密度相关,而并不会随有源层厚度的增加而增加。而上述本发明实施例所提供的薄膜晶体管中,有源层包括交替形成的多层有源半导体子层和绝缘隔离子层,在栅极作用下,每一层有源半导体子层和绝缘隔离子层的交界处都能产生沟道电流,因此,如图2所示,本发明增加了薄膜晶体管中的沟道15的数量,能够形成多个并列的沟道15,从而能够增加沟道电流,能够解决单沟道模式下有源层载流子迁移率较低导致的沟道电流较小的问题。
更进一步地,如图3所示,本发明实施例所提供的薄膜晶体管可以包括欧姆接触层50,该欧姆接触层50可以形成在有源层10上,并且有源层10可以沿厚度方向上窄下宽,欧姆接触层50可以和多层有源半导体子层11接触,源极20和漏极30可以形成在欧姆接触层50上。设置欧姆接触层50能够改善有源层10与源极20和漏极30之间的导电性,而将有源层10形成为沿厚度方向上窄下宽的结构,能够便于欧姆接触层50与多层有源半导体子层11接触,之后,源极20和漏极30可以形成在欧姆接触层50上以通过欧姆接触层50与多层有源半导体子层11导电连接。优选地,欧姆接触层的材料可以包括N+非晶硅。
可以理解的是,上述仅为本发明所提供的优选实施方式,除上述方式外,还可以采用其它方法使欧姆接触层与多层有源半导体子层接触,或使源极和漏极直接与多层有源半导体子层接触。例如,可以在有源层上设置过孔,该过孔可以贯穿各层有源半导体子层,欧姆接触层或者源极和漏极可以包括设置在该过孔中的部分,以能够和多层有源半导体子层均接触。
更进一步地,有源半导体子层的材料可以包括非晶硅(A-Si)。即,可以用非晶硅材料制成有源半导体子层,优选地,可以采用氢化非晶硅(A-Si:H)制成有源半导体子层。
更进一步地,绝缘隔离子层的材料可以包括硅的氮化物和/或硅的氧化物。即,可以用硅的氮化物,或者硅的氮化物,或者二者的结合制成绝缘隔离子层,优选地,可以采用氮化硅材料(SiNx)制成绝缘隔离子层。
更进一步地,每层有源半导体子层的厚度可以为每层所述绝缘隔离子层的厚度为优选地,每层有源半导体子层的厚度可以在左右,每层绝缘隔离子层的厚度可以在左右。
更进一步地,所述多层有源半导体子层和绝缘隔离子层的致密性从上至下逐渐增加。
作为本发明的另一个方面,提供一种阵列基板,该阵列基板可以包括上述本发明所提供的薄膜晶体管。具体地,该阵列基板中可以包括多个像素单元,其中至少一个像素单元中可以包括上述本发明所提供的薄膜晶体管。
如图4所示,本发明所提供的阵列基板还可以包括与漏极30连接的像素电极71、钝化层72以及形成在钝化层72上的公共电极73。像素电极71、钝化层72以及公共电极73可以形成为现有的结构,在此不过多赘述。可以理解的是,图4所示示例中的薄膜晶体管为底栅结构,而本发明同样适用于顶栅结构的薄膜晶体管。
本领域技术人员应当理解的是,所述阵列基板包括多条栅线和多条数据线,该多条栅线和多条数据线互相交错,将所述阵列基板划分为多个所述像素单元。
相应地,本发明还提供一种薄膜晶体管的制作方法,该制作方法包括形成薄膜晶体管的有源层的步骤和形成薄膜晶体管的源极和漏极的步骤,其中,形成有源层时,所形成的有源层包括交替层叠设置的多层有源半导体子层和多层绝缘隔离子层;形成源极和漏极时,所形成的源极和漏极与多层有源半导体子层导电连接。
更进一步地,在形成有源层时,可以交替沉积有源半导体膜层和绝缘隔离膜层;之后,可以利用构图工艺形成包括有源层的图形,并且使得有源层沿厚度方向上窄下宽。具体地,如图5所示,可以在栅极绝缘层41上交替沉积多层有源半导体膜层13和绝缘隔离膜层14,该步骤可以在CVD(Chemical Vapor Deposition,化学气相沉积)腔室里通过交替改变沉积所用气体来完成。之后,如图6所示,可以利用构图工艺通过刻蚀使得多层有源半导体子层11和绝缘隔离子层12沿厚度方向形成上窄下宽的结构,从而便于源极和漏极和多层有源半导体子层11都导电连接。其中,上述构图工艺具体可以包括:在有源层(即交替沉积的有源半导体膜层和绝缘隔离膜层)上涂覆光刻胶,并对光刻胶进行曝光和显影,以形成对应于有源层的图形,之后根据该图形进行刻蚀,以形成包括有源层的图形,使得所述有源层沿厚度方向上窄下宽。
更进一步地,上述交替沉积多层有源半导体膜层和绝缘隔离膜层时,可以通过控制沉积气压和气体流量使得上述多层有源半导体膜层和绝缘隔离膜层的致密性从上至下逐渐增加。在沉积过程中可以控制沉积气压和气体流量使得多层有源半导体膜层13和绝缘隔离膜层14的致密性从上至下逐渐增加,具体地,可以使多层有源半导体膜层13和绝缘隔离膜层14所形成的整体的致密性从上至下逐渐增加。由于在构图工艺中进行刻蚀时,致密性高的膜层刻蚀速率较慢,因此,通过控制沉积气压和气体流量使得多层有源半导体膜层和绝缘隔离膜层的致密性从上至下逐渐增加,能够便于通过刻蚀使得有源层沿厚度方向形成上窄下宽的结构。
当然为了使得后续形成的源极和漏极与各层有源半导体子层接触的更好,可以优选比有源半导体子层材料的刻蚀速率更高的材料制作绝缘隔离子层,这样在刻蚀时可以在有源半导体子层与绝缘隔离子层的界面的边缘位置形成台阶,使得源极和漏极与各层有源半导体子层接触的更好,从而可以进一步提高载流子迁移率。
可以理解的是,除上述方式外,还可以通过其它构图工艺(例如打印、转印等)形成上述有源层。
更进一步地,形成源极和漏极时,可以先在有源层上形成欧姆接触层,并且使欧姆接触层与多层有源半导体子层接触,之后,在欧姆接触层上形成源极和漏极。具体地,可以在有源层上沉积欧姆接触层膜和源漏金属层膜,之后利用构图工艺通过刻蚀形成包括欧姆接触层、源极和漏极的图形。
上述为对本发明所提供的薄膜晶体管及其制作方法,以及阵列基板进行的描述。可以看出,本发明通过在薄膜晶体管中形成包括多层互相交替的有源半导体子层和绝缘隔离子层,能够在薄膜晶体管中形成多个通道,从而能够增加沟道电流,以弥补有源层载流子迁移率较低导致的沟道电流较小的问题。与现有技术相比,本发明工艺复杂度较低,能够有效节约成本。
作为本发明的再一个方面,提供一种显示装置,该显示装置可以包括上述本发明所提供的阵列基板。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种薄膜晶体管,其特征在于,所述薄膜晶体管的有源层包括交替层叠设置的多层有源半导体子层和多层绝缘隔离子层,所述薄膜晶体管的源极和漏极与所述多层有源半导体子层导电连接,所述多层有源半导体子层和绝缘隔离子层的致密性从上至下逐渐增加。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述薄膜晶体管包括欧姆接触层,所述欧姆接触层形成在所述有源层上,且所述有源层沿厚度方向上窄下宽,所述欧姆接触层和所述多层有源半导体子层接触,所述源极和所述漏极形成在所述欧姆接触层上。
3.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述有源半导体子层的材料包括非晶硅。
4.根据权利要求1或2所述的薄膜晶体管,其特征在于,所述绝缘隔离子层的材料包括硅的氧化物和/或硅的氮化物。
5.根据权利要求1或2所述的薄膜晶体管,其特征在于,每层所述有源半导体子层的厚度为每层所述绝缘隔离子层的厚度为
6.一种阵列基板,其特征在于,所述阵列基板包括权利要求1至5中任意一项所述的薄膜晶体管。
7.一种薄膜晶体管的制作方法,该制作方法包括形成薄膜晶体管的有源层的步骤和形成薄膜晶体管源极和漏极的步骤,其特征在于,所述形成薄膜晶体管的有源层的步骤包括:
交替沉积有源半导体膜层和绝缘隔离膜层;
利用构图工艺形成包括所述有源层的图形,使得所述有源层沿厚度方向上窄下宽,在交替沉积的且致密性从上至下逐渐增加的有源半导体膜层和绝缘隔离膜层上涂覆光刻胶,并对光刻胶进行曝光和显影,以形成对应于有源层的图形,之后根据该图形进行刻蚀,以形成包括有源层的图形,使得所述有源层沿厚度方向上窄下宽。
8.根据权利要求7所述的薄膜晶体管的制作方法,其特征在于,交替沉积多层有源半导体膜层和绝缘隔离膜层时,通过控制沉积气压和气体流量使所述多层有源半导体膜层和绝缘隔离膜层的致密性从上至下逐渐增加。
9.根据权利要求8中所述的薄膜晶体管的制作方法,其特征在于,在所述形成薄膜晶体管的有源层的步骤和所述形成薄膜晶体管的源极和漏极的步骤之间,还包括:
在所述有源层上形成欧姆接触层,且所述欧姆接触层与所述多层有源半导体膜层接触;
所述形成薄膜晶体管的源极和漏极的步骤包括:
在所述欧姆接触层上形成所述源极和所述漏极。
10.一种显示装置,其特征在于,所述显示装置包括权利要求6所述的阵列基板。
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