CN107482064A - 薄膜晶体管及其制作方法以及阵列基板 - Google Patents

薄膜晶体管及其制作方法以及阵列基板 Download PDF

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CN107482064A
CN107482064A CN201710752796.XA CN201710752796A CN107482064A CN 107482064 A CN107482064 A CN 107482064A CN 201710752796 A CN201710752796 A CN 201710752796A CN 107482064 A CN107482064 A CN 107482064A
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tft
thin film
film transistor
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CN107482064B (zh
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卜呈浩
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/569,388 priority patent/US10483401B2/en
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Abstract

本发明提供一种薄膜晶体管及其制作方法以及阵列基板。该薄膜晶体管在源极(4)与漏极(6)之间设置间隔层(5)，在所述间隔层(5)与漏极(6)一侧设置接触部分漏极(6)上表面、漏极(6)与有机物间隔层(5)的侧面、及部分源极(4)上表面的氧化物半导体沟道层(7)作垂直沟道，沟道长度即间隔层(5)的厚度，可通过改变间隔层的厚度将垂直沟道的长度降到亚微米量级，能够大幅减小薄膜晶体管的尺寸，减小像素面积；垂直沟道不会发生短沟道效应，有助于提高薄膜晶体管的电性；采用多层的六方氮化硼薄膜作水氧阻隔层(2)，采用双层石墨烯薄膜作源极(4)与漏极(6)，能够显著提高薄膜晶体管的耐弯折性。

Description

薄膜晶体管及其制作方法以及阵列基板
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制作方法以及阵列基板。
背景技术
在显示技术领域，液晶显示屏(Liquid Crystal Display，LCD)与有机发光二极管显示屏(Organic Light Emitting Diode，OLED)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示屏。
目前，主流的LCD是由薄膜晶体管阵列基板(Thin Film Transistor ArraySubstrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)贴合而成，且在阵列基板与彩色滤光片基板之间灌入液晶，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽、可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。OLED同样需要阵列基板，以阵列基板上的薄膜晶体管作为开关部件和驱动部件。
如今，如何设计与制备高性能、小尺寸的薄膜晶体管已经成为实现下一代显示技术的核心内容，尤其对于柔性高解析度的手机显示屏、虚拟现实 (Virtual Reality，VR)显示屏、增强现实(Augmented Reality，AR)显示屏以及正在开发的全息显示屏来说，如何减小像素面积和薄膜晶体管的尺寸是首先需要考虑的问题。
发明内容
本发明的目的在于提供一种薄膜晶体管，能够大幅减小薄膜晶体管的尺寸，减小像素面积，更适合应用在柔性高解析度的显示器中。
本发明的另一目的在于提供一种薄膜晶体管的制作方法，能够大幅减小薄膜晶体管的尺寸，减小像素面积，且制程复杂性较低。
本发明的目的还在于提供一种阵列基板，其内的薄膜晶体管的尺寸较小，像素面积较小。
为实现上述目的，本发明首先提供一种薄膜晶体管，包括：
柔性衬底；
设置在所述柔性衬底上的水氧阻隔层；
设置在所述水氧阻隔层上的缓冲层；
设置在所述缓冲层上的源极；
设置在所述源极上并至少暴露出源极一侧的间隔层；
设置在所述间隔层上的漏极；
在所述间隔层与漏极一侧设置的接触部分漏极上表面、漏极与有机物间隔层的侧面、及部分源极上表面的氧化物半导体沟道层；
设置在所述氧化物半导体沟道层上的栅极绝缘层；
以及设置在所述栅极绝缘层上的栅极。
所述水氧阻隔层为多层的六方氮化硼薄膜，所述源极与漏极均为双层石墨烯薄膜，所述氧化物半导体沟道层的材料为氧化铟、铟镓锌氧化物、或氧化锌。
所述间隔层暴露出源极的两侧，所述源极远离氧化物半导体沟道层的一侧上设置源极接触电极，所述漏极远离氧化物半导体沟道层的一侧上设置漏极接触电极。
所述薄膜晶体管还包括覆盖所述缓冲层、源极、源极接触电极、漏极、漏极接触电极、与栅极的平坦层。
所述有机物间隔层的材料为聚酰亚胺，厚度为400nm～800nm。
所述源极接触电极与漏极接触电极的材料为金；所述栅极的材料为掺铝氧化锌。
本发明还提供一种薄膜晶体管的制作方法，包括如下步骤：
步骤S1、提供玻璃基板，在所述玻璃基板上形成柔性衬底；
步骤S2、形成覆盖所述柔性衬底的水氧阻隔层；
步骤S3、形成覆盖所述水氧阻隔层的缓冲层；
步骤S4、形成层叠在所述缓冲层上的源极；
步骤S5、形成层叠在所述源极上并至少暴露出源极一侧的间隔层；
步骤S6、形成覆盖所述间隔层的漏极；
步骤S7、形成氧化物半导体沟道层、栅极绝缘层、与栅极；
所述氧化物半导体沟道层位于所述有机物间隔层与漏极的一侧，并接触部分漏极上表面、漏极与有机物间隔层的侧面、及部分源极上表面；所述栅极绝缘层设在氧化物半导体沟道层上，所述栅极设置在所述栅极绝缘层上。
所述步骤S2的具体过程为：先在铜箔上生长六方氮化硼薄膜，再将生长好的六方氮化硼薄膜转移到柔性衬底上，重复多次形成所述水氧阻隔层；
所述步骤S4的具体过程为：先在铜箔上生长单层石墨烯薄膜，再将单层石墨烯薄膜转移到所述缓冲层上，重复两次，得到双层石墨烯薄膜，然后对双层石墨烯薄膜进行图案化处理，形成所述源极；
所述步骤S6的具体过程为：先在铜箔上生长单层石墨烯薄膜，再将单层石墨烯薄膜转移到所述间隔层上，重复两次，得到双层石墨烯薄膜，然后对双层石墨烯薄膜进行图案化处理，形成所述漏极。
所述步骤S7的具体过程为：先在步骤S6完成之后的各膜层上依次沉积氧化物半导体薄膜、绝缘材料薄膜、与金属薄膜，再使用同一张光罩对所述氧化物半导体薄膜、绝缘材料薄膜、与金属薄膜同时进行图案化处理，形成形状相同的氧化物半导体沟道层、栅极绝缘层、与栅极。
所述薄膜晶体管的制作方法还包括：
在所述步骤S4与步骤S5之间进行的步骤S45、在所述源极的一侧边缘上蒸镀出源极接触电极；
在所述步骤S6与步骤S7之间进行的步骤S67、在所述漏极的一侧边缘上蒸镀出漏极接触电极；
以及步骤S8、在步骤S7完成之后的各膜层上沉积平坦层，并将玻璃基板与柔性衬底分离。
本发明还提供一种阵列基板，包括多个呈阵列式排布的上述薄膜晶体管。
本发明的有益效果：本发明提供的一种薄膜晶体管，在源极与漏极之间设置间隔层，在所述间隔层与漏极一侧设置接触部分漏极上表面、漏极与有机物间隔层的侧面、及部分源极上表面的氧化物半导体沟道层作垂直沟道，沟道长度即间隔层的厚度，可通过改变间隔层的厚度将垂直沟道的长度降到亚微米量级，能够大幅减小薄膜晶体管的尺寸；由于垂直沟道与数据线及扫描线的交叠面积非常小，能够减小像素面积；垂直沟道不会发生短沟道效应，有助于提高薄膜晶体管的电性；采用多层的六方氮化硼薄膜作水氧阻隔层，采用双层石墨烯薄膜作源极与漏极，能够显著提高薄膜晶体管的耐弯折性。本发明提供的一种薄膜晶体管的制作方法，能够制作出上述垂直沟道型薄膜晶体管，从而能够大幅减小薄膜晶体管的尺寸，减小像素面积，提高薄膜晶体管的电性和耐弯折性，且使用同一张光罩同时制作出氧化物半导体沟道层、栅极绝缘层、与栅极，降低了制程复杂性。本发明提供的一种阵列基板，包括多个呈阵列式排布的上述垂直沟道型薄膜晶体管，薄膜晶体管的尺寸较小，像素面积较小。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的薄膜晶体管在弯折状态下的剖面结构示意图；
图2为本发明的薄膜晶体管在平板状态下的剖面结构示意图；
图3为本发明的薄膜晶体管能够减小像素面积的示意图；
图4为本发明的薄膜晶体管的制作方法的流程图；
图5为本发明的薄膜晶体管的制作方法的步骤S2的示意图；
图6为本发明的薄膜晶体管的制作方法的步骤S3的示意图；
图7为本发明的薄膜晶体管的制作方法的步骤S4与S45的示意图；
图8为本发明的薄膜晶体管的制作方法的步骤S5的示意图；
图9为本发明的薄膜晶体管的制作方法的步骤S6与S67的示意图；
图10与图11为本发明的薄膜晶体管的制作方法的步骤S7的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图1与图2，本发明首先提供一种薄膜晶体管，包括：
柔性衬底1；
设置在所述柔性衬底1上的水氧阻隔层2；
设置在所述水氧阻隔层2上的缓冲层3；
设置在所述缓冲层3上的源极4；
设置在所述源极4上并至少暴露出源极4一侧的间隔层5；
设置在所述间隔层5上的漏极6；
在所述间隔层5与漏极6一侧设置的连续接触部分漏极6上表面、漏极 6与有机物间隔层5的侧面、及部分源极4上表面的氧化物半导体沟道层7；
设置在所述氧化物半导体沟道层7并与氧化物半导体沟道层7形状相同的栅极绝缘层8；
设置在所述栅极绝缘层8上并与氧化物半导体沟道层7形状相同的栅极 9；
以及覆盖所述缓冲层3、源极4、漏极6与栅极9的平坦层10。
具体地：
所述柔性衬底1的材料优选聚酰亚胺(Polyimide，PI)；
所述水氧阻隔层2采用多层的二维平面原子层材料：六方氮化硼薄膜 (h-BN)的叠层结构，h-BN薄膜自身具有优异的柔性，多层的h-BN薄膜之间相互补充点缺陷，形成致密的多层薄膜结构，使得所述水氧阻隔层2的耐弯折性和水氧阻隔性都大幅度提高；
所述缓冲层3的材料为氧化铝(Al2O3)；
所述源极4优选为双层石墨烯薄膜；
所述间隔层5的材料可选择PI等有机高分子聚合物,厚度可为400nm～ 800nm；进一步地，所述间隔层5的面积小于源极4的面积，所述间隔层5不足以完全覆盖源极4，而至少暴露出源极4的一侧；
所述漏极6亦优选为双层石墨烯薄膜；
所述氧化物半导体沟道层7的材料为氧化铟(InOx)、铟镓锌氧化物(IGZO)、或氧化锌(ZnO)；氧化物半导体沟道层7相比现有的有机半导体沟道层具有更高的电子迁移率、大面积的均一稳定性、及优良的表面平坦性，与非晶硅制程相容性更高，即使沟道长度即间隔层5的厚度缩短到亚微米级别也不会发生短沟道效应；
所述栅极绝缘层8的材料为Al2O3；
所述栅极9的材料为掺铝氧化锌(AZO)；
所述平坦层10的材料为二氧化硅(SiO2)。
值得注意的是：采用双层石墨烯薄膜来作源极4与漏极6时，石墨烯具有优异的导电性和耐弯折性，能够进一步提高薄膜晶体管的可弯折性和电性，但是由于石墨烯厚度极薄、材质较软而不易与其它的金属信号线形成欧姆接触，所以需要所述间隔层5暴露出源极4的两侧，在所述源极4远离氧化物半导体沟道层7的一侧上设置金属材质如金(Au)的源极接触电极41，在所述漏极6远离氧化物半导体沟道层7的一侧上设置金属材质如Au的漏极接触电极61，通过所述源极接触电极41与漏极接触电极61进行欧姆接触。当然，所述源极4与漏极6也可以直接采用金属薄膜，这种情况下便可以省去源极接触电极41与漏极接触电极61的设置。
本发明的薄膜晶体管在源极4与漏极6之间设置间隔层5，在所述间隔层5与漏极6一侧设置连续接触部分漏极6上表面、漏极6与有机物间隔层 5的侧面、及部分源极4上表面的氧化物半导体沟道层7作垂直沟道，沟道长度即间隔层5的厚度，可进行精确控制，所以通过改变间隔层5的厚度能够将垂直沟道的长度降到亚微米量级，一方面能够大幅减小薄膜晶体管的尺寸，另一方面精确且极小的沟道长度既能够使得薄膜晶体管获得更高、更稳定的开态电流，又能承受更大的弯曲应力，这些优点使得本发明的薄膜晶体管更适合应用在超高解析度的柔性显示屏中。如图3所示，利用本发明的薄膜晶体管做成驱动阵列后，由于氧化物半导体沟道层7即垂直沟道与扫描线 200及数据线400的交叠面积非常小而显著减小像素P的面积，同时用作垂直沟道的氧化物半导体沟道层7不会发生短沟道效应，有助于提高薄膜晶体管的电性。
本发明还提供一种阵列基板，包括多个呈阵列式排布的上述垂直沟道型的薄膜晶体管，所以薄膜晶体管的尺寸较小，像素面积较小，此处不再对所述薄膜晶体管进行重复性描述。当然，所述阵列基板上还设置有扫描线、数据线、像素电极等，这与现有技术无异，此处不进行展开叙述。
请参阅图4，本发明也提供一种薄膜晶体管的制作方法，包括如下步骤：
步骤S1、请参阅图5，提供玻璃基板1’，在所述玻璃基板1’上形成柔性衬底1。
具体地，该步骤S1通过在玻璃基板1’上涂布、固化PI材料形成柔性衬底1。
步骤S2、如图5所示，先采用化学气相沉积法(Chemical Vapor Deposition，CVD)在铜箔上生长h-BN薄膜，再采用湿法转移技术将生长好的h-BN薄膜转移到柔性衬底1上，重复多次，形成覆盖所述柔性衬底1的多层水氧阻隔层2。
具体地，h-BN薄膜自身具有优异的柔性，多层的h-BN薄膜之间相互补充点缺陷，形成致密的多层薄膜结构，所以所述水氧阻隔层2的耐弯折性和水氧阻隔性都有大幅度地提高。
步骤S3、如图6所示，使用原子层沉积技术将Al2O3薄膜沉积在水氧阻隔层2上形成覆盖所述水氧阻隔层2的缓冲层3。
步骤S4、如图7所示，先采用CVD法在铜箔上生长单层石墨烯薄膜，再采用湿法转移技术将单层石墨烯薄膜转移到所述缓冲层3上，重复两次，得到双层石墨烯薄膜，然后采用激光直写技术对双层石墨烯薄膜进行图案化处理，形成层叠在所述缓冲层3上的源极4。
由于石墨烯高度透明，具有优异的导电性和耐弯折性，由双层石墨烯薄膜制得的源极4的可弯折性和导电性非常好，但是由于石墨烯厚度极薄、材质较软而不易与其它的金属信号线形成欧姆接触，所以还需要实施步骤 S45、在所述源极4的一侧边缘上蒸镀出源极接触电极41，以通过所述源极接触电极41进行欧姆接触。
具体地，所述源极接触电极41的材料为Au。
当然，若所述源极4直接采用金属薄膜，则可以省去步骤S45。
接下来进行步骤S5、如图8所示，采用旋涂(Spin Coating)的方式将 PI溶胶涂布在步骤S5完成之后的各膜层上，在150℃下烘干、曝光、显影后使用氧等离子体(O2Plasma)进行刻蚀制程，形成层叠在所述源极4上并暴露出源极4两侧的间隔层5。
具体地，所述间隔层5的厚度可为400～800nm，优选600nm。
步骤S6、如图9所示，采用CVD法在铜箔上生长单层石墨烯薄膜，再采用湿法转移技术将单层石墨烯薄膜转移到所述间隔层5上，重复两次，得到双层石墨烯薄膜，然后采用激光直写技术对双层石墨烯薄膜进行图案化处理，形成覆盖所述间隔层5且与该间隔层5面积一致的漏极6。
由于石墨烯高度透明，具有优异的导电性和耐弯折性，由双层石墨烯薄膜制得的漏极6的可弯折性和导电性非常好,但是由于石墨烯厚度极薄、材质较软而不易与其它的金属信号线形成欧姆接触，所以还需要实施步骤S67、在所述漏极6的一侧边缘上蒸镀出漏极接触电极61，以通过所述漏极接触电极61进行欧姆接触。
具体地，所述漏极接触电极61的材料为Au。
当然，若所述漏极6直接采用金属薄膜，则可以省去步骤S67。
接下来进行步骤S7、如图10、与图11所示，先采用等离子增强原子层沉积(PEALD)法在步骤S6完成之后的各膜层上依次沉积氧化物半导体薄膜 7’、绝缘材料薄膜8’、与金属薄膜9’；再使用同一张光罩对所述氧化物半导体薄膜7’、绝缘材料薄膜8’、与金属薄膜9’同时进行图案化处理，形成氧化物半导体沟道层7、栅极绝缘层8、与栅极9。
具体地，所述氧化物半导体薄膜7’的材料为InOx、IGZO、或ZnO，所述绝缘材料薄膜8’的材料为Al2O3，所述金属薄膜9’的材料为AZO；
所述氧化物半导体沟道层7位于所述有机物间隔层5与漏极6的一侧，并连续接触部分漏极6上表面、漏极6与有机物间隔层5的侧面、及部分源极4上表面；所述栅极绝缘层8覆盖所述氧化物半导体沟道层7并与氧化物半导体沟道层7的形状相同；所述栅极9覆盖所述栅极绝缘层8并与氧化物半导体沟道层7形状相同。
值得注意的是，由于该步骤S7采用PEALD法沉积氧化物半导体薄膜 7’、绝缘材料薄膜8’、与金属薄膜9’,所述氧化物半导体沟道层7、栅极绝缘层8、与栅极9的台阶覆盖性较好，氧化物半导体沟道层7为垂直沟道，其沟道长度即为有机物间隔层5的厚度，可进行精确控制，且氧化物半导体沟道层7相比现有的有机半导体沟道层具有更高的电子迁移率、大面积的均一稳定性、及优良的表面平坦性，与非晶硅制程相容性更高，即使沟道长度即有机物间隔层5的厚度缩短到亚微米级别也不会发生短沟道效应，一方面能够大幅减小最终制得的薄膜晶体管的尺寸，进而显著减小像素面积，另一方面可以显著提高薄膜晶体管的电性。
以及步骤S8、请参阅图2，在步骤S7完成之后的各膜层上沉积平坦层 10，并采用激光剥离技术将玻璃基板1’与柔性衬底1分离，得到柔性自支撑的垂直沟道型薄膜晶体管。
通过上述薄膜晶体管的制作方法能够制得垂直沟道型薄膜晶体管，从而能够大幅减小薄膜晶体管的尺寸，减小像素面积，提高薄膜晶体管的电性和耐弯折性，且使用同一张光罩同时制作出氧化物半导体沟道层7、栅极绝缘层8、与栅极9，降低了制程复杂性。
综上所述，本发明的薄膜晶体管，在源极与漏极之间设置间隔层，在所述间隔层与漏极一侧设置接触部分漏极上表面、漏极与有机物间隔层的侧面、及部分源极上表面的氧化物半导体沟道层作垂直沟道，沟道长度即间隔层的厚度，可通过改变间隔层的厚度将垂直沟道的长度降到亚微米量级，能够大幅减小薄膜晶体管的尺寸；由于垂直沟道与数据线及扫描线的交叠面积非常小，能够减小像素面积；垂直沟道不会发生短沟道效应，有助于提高薄膜晶体管的电性；采用多层的六方氮化硼薄膜作水氧阻隔层，采用双层石墨烯薄膜作源极与漏极，能够显著提高薄膜晶体管的耐弯折性。本发明的薄膜晶体管的制作方法，能够制作出上述垂直沟道型薄膜晶体管，从而能够大幅减小薄膜晶体管的尺寸，减小像素面积，提高薄膜晶体管的电性和耐弯折性，且使用同一张光罩同时制作出氧化物半导体沟道层、栅极绝缘层、与栅极，降低了制程复杂性。本发明的阵列基板，包括多个呈阵列式排布的上述垂直沟道型薄膜晶体管，薄膜晶体管的尺寸较小，像素面积较小。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (11)

1.一种薄膜晶体管，其特征在于，包括：
柔性衬底(1)；
设置在所述柔性衬底(1)上的水氧阻隔层(2)；
设置在所述水氧阻隔层(2)上的缓冲层(3)；
设置在所述缓冲层(3)上的源极(4)；
设置在所述源极(4)上并至少暴露出源极(4)一侧的间隔层(5)；
设置在所述间隔层(5)上的漏极(6)；
在所述间隔层(5)与漏极(6)一侧设置的接触部分漏极(6)上表面、漏极(6)与有机物间隔层(5)的侧面、及部分源极(4)上表面的氧化物半导体沟道层(7)；
设置在所述氧化物半导体沟道层(7)上的栅极绝缘层(8)；
以及设置在所述栅极绝缘层(8)上的栅极(9)。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述水氧阻隔层(2)为多层的六方氮化硼薄膜，所述源极(4)与漏极(6)均为双层石墨烯薄膜，所述氧化物半导体沟道层(7)的材料为氧化铟、铟镓锌氧化物、或氧化锌。
3.如权利要求2所述的薄膜晶体管，其特征在于，所述间隔层(5)暴露出源极(4)的两侧，所述源极(4)远离氧化物半导体沟道层(7)的一侧上设置源极接触电极(41)，所述漏极(6)远离氧化物半导体沟道层(7)的一侧上设置漏极接触电极(61)。
4.如权利要求3所述的薄膜晶体管，其特征在于，还包括覆盖所述缓冲层(3)、源极(4)、源极接触电极(41)、漏极(6)、漏极接触电极(61)、与栅极(9)的平坦层(10)。
5.如权利要求2所述的薄膜晶体管，其特征在于，所述间隔层(5)的材料为聚酰亚胺，厚度为400nm～800nm。
6.如权利要求3所述的薄膜晶体管，其特征在于，所述源极接触电极(41)与漏极接触电极(61)的材料为金；所述栅极(9)的材料为掺铝氧化锌。
7.一种薄膜晶体管的制作方法，其特征在于，包括如下步骤：
步骤S1、提供玻璃基板(1’)，在所述玻璃基板(1’)上形成柔性衬底(1)；
步骤S2、形成覆盖所述柔性衬底(1)的水氧阻隔层(2)；
步骤S3、形成覆盖所述水氧阻隔层(2)的缓冲层(3)；
步骤S4、形成层叠在所述缓冲层(3)上的源极(4)；
步骤S5、形成层叠在所述源极(4)上并至少暴露出源极(4)一侧的间隔层(5)；
步骤S6、形成覆盖所述间隔层(5)的漏极(6)；
步骤S7、形成氧化物半导体沟道层(7)、栅极绝缘层(8)、与栅极(9)；
所述氧化物半导体沟道层(7)位于所述有机物间隔层(5)与漏极(6)的一侧，并接触部分漏极(6)上表面、漏极(6)与有机物间隔层(5)的侧面、及部分源极(4)上表面；所述栅极绝缘层(8)设在氧化物半导体沟道层(7)上，所述栅极(9)设置在所述栅极绝缘层(8)上。
8.如权利要求7所述的薄膜晶体管的制作方法，其特征在于，
所述步骤S2的具体过程为：先在铜箔上生长六方氮化硼薄膜，再将生长好的六方氮化硼薄膜转移到柔性衬底(1)上，重复多次形成所述水氧阻隔层(2)；
所述步骤S4的具体过程为：先在铜箔上生长单层石墨烯薄膜，再将单层石墨烯薄膜转移到所述缓冲层(3)上，重复两次，得到双层石墨烯薄膜，然后对双层石墨烯薄膜进行图案化处理，形成所述源极(4)；
所述步骤S6的具体过程为：先在铜箔上生长单层石墨烯薄膜，再将单层石墨烯薄膜转移到所述间隔层(5)上，重复两次，得到双层石墨烯薄膜，然后对双层石墨烯薄膜进行图案化处理，形成所述漏极(6)。
9.如权利要求7所述的薄膜晶体管的制作方法，其特征在于，
所述步骤S7的具体过程为：先在步骤S6完成之后的各膜层上依次沉积氧化物半导体薄膜(7’)、绝缘材料薄膜(8’)、与金属薄膜(9’)，再使用同一张光罩对所述氧化物半导体薄膜(7’)、绝缘材料薄膜(8’)、与金属薄膜(9’)同时进行图案化处理，形成形状相同的氧化物半导体沟道层(7)、栅极绝缘层(8)、与栅极(9)。
10.如权利要求8所述的薄膜晶体管的制作方法，其特征在于，还包括：
在所述步骤S4与步骤S5之间进行的步骤S45、在所述源极(4)的一侧边缘上蒸镀出源极接触电极(41)；
在所述步骤S6与步骤S7之间进行的步骤S67、在所述漏极(6)的一侧边缘上蒸镀出漏极接触电极(61)；
以及步骤S8、在步骤S7完成之后的各膜层上沉积平坦层(10)，并将玻璃基板(1’)与柔性衬底(1)分离。
11.一种阵列基板，其特征在于，包括多个呈阵列式排布的如权利要求1至6任一项所述的薄膜晶体管。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108054209A (zh) * 2017-12-14 2018-05-18 北京华碳科技有限责任公司 场效应晶体管、制造场效应晶体管的方法及电子器件
CN108428666A (zh) * 2018-03-29 2018-08-21 深圳市华星光电半导体显示技术有限公司 柔性tft背板的制作方法及柔性tft背板
WO2019148327A1 (zh) * 2018-01-30 2019-08-08 深圳市柔宇科技有限公司 薄膜晶体管及其制造方法、栅极驱动电路、平板显示器
CN110718556A (zh) * 2019-08-29 2020-01-21 福建华佳彩有限公司 一种柔性阵列基板及制造方法
CN112259602A (zh) * 2020-10-10 2021-01-22 武汉华星光电半导体显示技术有限公司 一种小尺寸tft及显示面板
CN112701084A (zh) * 2020-12-29 2021-04-23 北京大学深圳研究生院 柔性薄膜晶体管阵列的结构及其制造方法
WO2021184910A1 (zh) * 2020-03-18 2021-09-23 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置
US11251036B2 (en) 2018-12-28 2022-02-15 Imec Vzw Semiconductor devices and methods of manufacturing semiconductor devices
CN116334581A (zh) * 2023-03-24 2023-06-27 深圳市金广利薄膜材料有限公司 一种新材料薄膜及其制备方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110854203B (zh) * 2019-11-21 2023-10-03 京东方科技集团股份有限公司 薄膜晶体管、阵列基板、显示面板及显示装置
US11832486B2 (en) 2021-09-14 2023-11-28 Electronics And Telecommunications Research Institute Semiconductor device, display panel, and display device including the same
CN114122145B (zh) * 2021-11-15 2023-11-28 武汉华星光电半导体显示技术有限公司 薄膜晶体管、电子装置及其制备方法及显示装置
EP4350779A1 (en) * 2022-10-06 2024-04-10 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175609A1 (en) * 2004-05-20 2006-08-10 Chan Isaac W T Vertical thin film transistor with short-channel effect suppression
US20130161732A1 (en) * 2011-12-27 2013-06-27 Electronics And Telecommunications Research Institute Vertical channel thin film transistor
CN103545463A (zh) * 2013-09-27 2014-01-29 Tcl集团股份有限公司 一种柔性显示器件及其制作方法
CN106684251A (zh) * 2016-12-09 2017-05-17 武汉华星光电技术有限公司 柔性垂直沟道有机薄膜晶体管及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208783A (ja) * 1983-05-12 1984-11-27 Seiko Instr & Electronics Ltd 薄膜トランジスタ
KR102036110B1 (ko) * 2013-02-22 2019-10-24 엘지전자 주식회사 성장 기판, 질화물 반도체 소자 및 그 제조 방법
JP6311899B2 (ja) * 2014-05-09 2018-04-18 株式会社Ｊｏｌｅｄ 薄膜トランジスタ基板及びその製造方法
WO2017101109A1 (en) * 2015-12-18 2017-06-22 Boe Technology Group Co., Ltd. Thin film transistor, array substrate, and display apparatus, and their fabrication methods
CN106252217B (zh) * 2016-08-25 2019-05-24 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN107068613A (zh) * 2016-12-30 2017-08-18 深圳市华星光电技术有限公司 Oled显示装置的阵列基板及其制作方法
US20180315860A1 (en) * 2017-04-28 2018-11-01 The Hong Kong University Of Science And Technology Vertical thin-film transistor with multiple-junction channel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175609A1 (en) * 2004-05-20 2006-08-10 Chan Isaac W T Vertical thin film transistor with short-channel effect suppression
US20130161732A1 (en) * 2011-12-27 2013-06-27 Electronics And Telecommunications Research Institute Vertical channel thin film transistor
CN103545463A (zh) * 2013-09-27 2014-01-29 Tcl集团股份有限公司 一种柔性显示器件及其制作方法
CN106684251A (zh) * 2016-12-09 2017-05-17 武汉华星光电技术有限公司 柔性垂直沟道有机薄膜晶体管及其制作方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108054209A (zh) * 2017-12-14 2018-05-18 北京华碳科技有限责任公司 场效应晶体管、制造场效应晶体管的方法及电子器件
CN108054209B (zh) * 2017-12-14 2020-08-11 北京华碳科技有限责任公司 场效应晶体管、制造场效应晶体管的方法及电子器件
WO2019148327A1 (zh) * 2018-01-30 2019-08-08 深圳市柔宇科技有限公司 薄膜晶体管及其制造方法、栅极驱动电路、平板显示器
CN111742413A (zh) * 2018-01-30 2020-10-02 深圳市柔宇科技股份有限公司 薄膜晶体管及其制造方法、栅极驱动电路、平板显示器
CN108428666A (zh) * 2018-03-29 2018-08-21 深圳市华星光电半导体显示技术有限公司 柔性tft背板的制作方法及柔性tft背板
CN108428666B (zh) * 2018-03-29 2020-07-28 深圳市华星光电半导体显示技术有限公司 柔性tft背板的制作方法及柔性tft背板
US11251036B2 (en) 2018-12-28 2022-02-15 Imec Vzw Semiconductor devices and methods of manufacturing semiconductor devices
CN110718556A (zh) * 2019-08-29 2020-01-21 福建华佳彩有限公司 一种柔性阵列基板及制造方法
WO2021184910A1 (zh) * 2020-03-18 2021-09-23 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置
CN112259602A (zh) * 2020-10-10 2021-01-22 武汉华星光电半导体显示技术有限公司 一种小尺寸tft及显示面板
CN112701084A (zh) * 2020-12-29 2021-04-23 北京大学深圳研究生院 柔性薄膜晶体管阵列的结构及其制造方法
CN116334581A (zh) * 2023-03-24 2023-06-27 深圳市金广利薄膜材料有限公司 一种新材料薄膜及其制备方法

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