WO2014083647A1 - 樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置 Download PDF

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WO2014083647A1
WO2014083647A1 PCT/JP2012/080796 JP2012080796W WO2014083647A1 WO 2014083647 A1 WO2014083647 A1 WO 2014083647A1 JP 2012080796 W JP2012080796 W JP 2012080796W WO 2014083647 A1 WO2014083647 A1 WO 2014083647A1
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Prior art keywords
resin
glass composition
layer
semiconductor device
lead
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PCT/JP2012/080796
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English (en)
French (fr)
Japanese (ja)
Inventor
小笠原　淳
浩二 伊東
広野 六鎗
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新電元工業株式会社
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Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to JP2013505243A priority Critical patent/JP5308595B1/ja
Priority to CN201280033933.XA priority patent/CN103975422B/zh
Priority to PCT/JP2012/080796 priority patent/WO2014083647A1/ja
Priority to TW102123956A priority patent/TWI556330B/zh
Publication of WO2014083647A1 publication Critical patent/WO2014083647A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66121—Multilayer diodes, e.g. PNPN diodes
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/102—Glass compositions containing silica with 40% to 90% silica, by weight containing lead
    • C03C3/105—Glass compositions containing silica with 40% to 90% silica, by weight containing lead containing aluminium
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
    • C03C8/24—Fusion seal compositions being frit compositions having non-frit additions, i.e. for use as seals between dissimilar materials, e.g. glass and metal; Glass solders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method for manufacturing a resin-encapsulated semiconductor device and a resin-encapsulated semiconductor device.
  • FIG. 10 is a view for explaining a conventional mesa type semiconductor device 900.
  • a conventional mesa semiconductor device 900 includes a mesa semiconductor substrate 908 having a pn junction exposed portion C in an outer peripheral taper region B surrounding the mesa region A, and a glass layer 924 covering the outer peripheral taper region B. And have.
  • the glass layer 924 is a glass layer for passivation.
  • reference numeral 910 denotes an n ⁇ type semiconductor layer
  • reference numeral 912 denotes a p + type semiconductor layer
  • reference numeral 914 denotes an n + semiconductor layer
  • reference numeral 916a denotes a silicon oxide film
  • reference numeral 934 denotes An anode electrode layer is shown
  • a reference numeral 936 denotes a cathode electrode layer.
  • the conventional mesa type semiconductor element 900 it is possible to configure a semiconductor device having a higher breakdown voltage than a planar type semiconductor element.
  • the conventional mesa semiconductor element 900 has a high temperature when it is molded with resin to form a resin-encapsulated semiconductor device (conventional resin-encapsulated semiconductor device). It has become clear that there is a problem that the reverse bias tolerance is low and it is difficult to use it in applications that are used under severe conditions.
  • the present invention has been made to solve the above-described problems, and is a resin-encapsulated semiconductor device manufactured by molding a mesa-type semiconductor element with a resin, which is a conventional resin-encapsulated semiconductor device.
  • An object of the present invention is to provide a resin-encapsulated semiconductor device having a higher high-temperature reverse bias tolerance. Moreover, it aims at providing the manufacturing method of the resin sealing type
  • a method for manufacturing a resin-encapsulated semiconductor device includes a semiconductor substrate preparation step of preparing a semiconductor substrate having a pn junction parallel to a main surface, and the pn junction is exceeded from one surface of the semiconductor substrate.
  • a groove forming step for forming a groove having a depth, a glass layer forming step for forming a lead-based glass layer so as to cover an inner surface of the groove, and a mesa mold by cutting the semiconductor substrate along the groove A method for producing a resin-encapsulated semiconductor device, comprising: a semiconductor substrate cutting step for producing a semiconductor element; and a resin encapsulation step for encapsulating the mesa semiconductor element with a molding resin in this order, the glass layer
  • the forming step includes a base oxide layer forming step in which an inner surface of the groove is oxidized to form a base oxide layer, and a glass composition made of a lead-based glass composition so as to cover the inner surface of the groove through the base oxide layer.
  • Form a material layer A glass composition layer forming step that, characterized in that it comprises a firing step of firing the glass composition layer at a temperature ⁇ point Tf of the lead-based glass composition.
  • the melting point Tf means the temperature of the shoulder of the first heat generating portion of the DTA curve in the lead-based glass composition (see FIG. 5 described later).
  • the temperature of the shoulder of the 1st heat absorption part of the DTA curve in a lead-type glass composition is a glass transition point Tg.
  • the firing step it is preferable to fire the glass composition layer at a temperature equal to or higher than the softening point Ts of the lead-based glass composition.
  • the glass composition layer is baked in a wet oxygen gas atmosphere.
  • the base oxide layer having a thickness of 10 nm to 100 nm is formed in the base oxide layer forming step.
  • the base oxide layer is formed at a temperature within a range of 950 ° C. to 1150 ° C. in the base oxide layer forming step.
  • a resin-encapsulated semiconductor device of the present invention is a mesa semiconductor device having a mesa semiconductor substrate having a pn junction exposed portion in an outer peripheral taper region surrounding a mesa region and a lead-based glass layer covering the outer peripheral taper region.
  • a molding resin for sealing the mesa semiconductor element wherein the glass layer forms a base oxide layer by oxidizing the inner surface of the groove to form a base oxide layer
  • the glass composition layer is formed by performing a firing step of firing the glass composition layer at a temperature equal to or lower than the point Tf.
  • the lead-based glass layer oxidizes the inner surface of the groove.
  • a base oxide layer forming step of forming a base oxide layer, and a glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition so as to cover the inner surface of the groove via the base oxide layer Since it is formed by carrying out a firing step of firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 described later, It becomes possible to change the charge density of the glass layer from minus to plus.
  • the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention) is similar to the conventional resin-encapsulated semiconductor device. While having a structure in which a mesa semiconductor element is molded with resin, a resin-encapsulated semiconductor device having a higher high-temperature reverse bias tolerance than a conventional resin-encapsulated semiconductor device is obtained. That is, the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention) is manufactured by molding a mesa semiconductor element with resin.
  • the resin-encapsulated semiconductor device is a resin-encapsulated semiconductor device having higher high-temperature reverse bias tolerance than the conventional resin-encapsulated semiconductor device.
  • the glass composition layer is usually fired at a temperature exceeding the melting point Tf of the lead-based glass composition for the purpose of easily removing bubbles generated in the glass layer during firing. As a result, lead-based glass is formed.
  • the charge density of the glass layer is changed from minus to plus. It is still unclear why this is possible.
  • the glass composition layer was fired at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 and FIG. This is because when the glass composition layer is fired at a temperature exceeding the melting point Tf of the glass composition (870 ° C. in this case), the charge density of the glass layer cannot be changed from minus to plus.
  • a method of forming a wide groove (mesa groove) in the process of manufacturing a mesa semiconductor element, and (2) a mesa semiconductor element A method of forming a deep groove (mesa groove) by using a diffusion wafer in the manufacturing process, (3) a method of using a wafer having a low specific resistance, and (4) a method of forming a lead-based glass layer thick are also conceivable.
  • the method (1) has a problem that the manufacturing cost of the product increases due to the increase in the chip area.
  • the use of a diffusion wafer increases the manufacturing cost of the product due to the fact that the process becomes difficult due to the high price of the wafer and the necessity of deep groove formation. There is a problem of end. Further, the method (3) has a problem that it is difficult to ensure a withstand voltage. The method (4) has a problem that the wafer is warped or easily broken during the process. On the other hand, according to the method for manufacturing a resin-encapsulated semiconductor device and the resin-encapsulated semiconductor device of the present invention, it is possible to increase the high temperature reverse bias tolerance without causing the above-described problems.
  • a “glass composition mainly composed of lead silicate” that has been widely used in the past is suitable as the lead-based glass composition. Can be used.
  • FIG. 1 is a view for explaining a resin encapsulated semiconductor device 10 according to the embodiment.
  • FIG. 1A is a perspective view of the resin-encapsulated semiconductor device 10
  • FIG. 1B is a plan view of the resin-encapsulated semiconductor device 10 with the resin removed
  • FIG. 3 is a side view of the sealed semiconductor device 10 with a resin removed.
  • FIG. FIG. 2 is a view for explaining the mesa semiconductor device 100 according to the embodiment.
  • the resin-encapsulated semiconductor device 10 includes a mesa semiconductor element 100 and a molding resin 40 that encapsulates the mesa semiconductor element 100.
  • the mesa semiconductor element 100 is placed on the die pad 23 in the lead frame 20 including the lead 21, the lead 22, and the die pad 23.
  • One electrode of the mesa semiconductor element 100 is connected to the lead 21 via the die pad 23, and the other electrode of the mesa semiconductor element 100 is connected to the lead 22 via the gold wire 30.
  • the mesa semiconductor element 100 includes a mesa semiconductor substrate 108 having a pn junction exposed portion C in an outer peripheral tapered region B surrounding the mesa region A and a lead-based glass layer 124 covering at least the outer peripheral tapered region B.
  • the outer peripheral taper region B is covered with the lead-based glass layer 124 through the base oxide layer 211.
  • the lead-based glass layer 124 is a glass containing lead silicate as a main component (for example, glass containing SiO 2 : 75.0%, PbO: 20.0%, Al 2 O 3 : 5.0% in a molar ratio). Consists of.
  • the mesa type semiconductor substrate 108 includes an n ⁇ type semiconductor layer (n ⁇ type silicon substrate) 110, a p + type semiconductor layer 112 formed by diffusion of p type impurities from one surface of the n ⁇ type semiconductor layer 110, and , An n + type semiconductor layer 114 formed by diffusion of an n type impurity from the other surface of the n ⁇ type semiconductor layer 110.
  • the mesa semiconductor device 100 is a pn diode.
  • reference numeral 134 denotes an anode electrode layer
  • reference numeral 136 denotes a cathode electrode layer.
  • the lead-based glass layer 124 includes a base oxide layer forming step of forming the base oxide layer by oxidizing the inner surface of the groove, and the base oxide layer on the inner surface of the groove.
  • the resin sealed semiconductor device 10 according to the embodiment can be manufactured by the following method (the manufacturing method of the resin sealed semiconductor device according to the embodiment).
  • 3 and 4 are views for explaining the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment.
  • 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (d) are process diagrams.
  • FIG. 5 is a diagram showing a DTA (differential thermal analysis) curve of the glass composition.
  • the method for manufacturing a resin-encapsulated semiconductor device includes a “semiconductor substrate forming step”, a “groove forming step”, a “underlying oxide layer forming step”, and “lead-based glass”.
  • “Layer formation process” “Photoresist formation process”, “Oxide film removal process”, “Roughened area formation process”, “Electrode formation process”, “Semiconductor substrate cutting process” and “Resin sealing process” in this order To implement.
  • the manufacturing method of the resin-encapsulated semiconductor device according to the embodiment will be described in the order of steps.
  • n + type semiconductor layer 112 is diffused from one surface of n ⁇ type semiconductor substrate (n ⁇ type silicon substrate) 110, and n type impurities from the other surface are diffused.
  • An n + type semiconductor layer 114 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed.
  • oxide films 116 and 118 are formed on the surfaces of the p + type semiconductor layer 112 and the n + type semiconductor layer 114 by thermal oxidation.
  • a base oxide layer 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (see FIG. 3B). ).
  • the thickness of the base oxide layer 121 is in the range of 10 nm to 100 nm (for example, 20 nm).
  • the formation of the base oxide layer 121 is performed by placing the semiconductor substrate in a diffusion furnace and then treating the substrate at a temperature in the range of 950 ° C. to 1050 ° C. for 5 minutes to 30 minutes while flowing oxygen gas. If the thickness of the underlying oxide layer 121 is less than 10 nm, the reverse current reduction effect may not be obtained. On the other hand, if the thickness of the base oxide layer 121 exceeds 100 nm, a layer made of a glass composition may not be formed by electrophoresis in the next glass layer forming step.
  • the glass composition is a glass composition containing lead silicate as a main component (for example, a glass composition containing SiO 2 : 75.0%, PbO: 20.0%, Al 2 O 3 : 5.0% in molar ratio). ) Is used.
  • the glass composition layer is formed so as to cover the inner surface of the groove 120 via the base oxide layer 121. Therefore, the exposed pn junction in the trench 120 is covered with the lead-based glass layer 124 via the base oxide layer 121.
  • Calcination of the glass composition layer is performed by firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition (see FIG. 5).
  • the firing step it is preferable to fire the glass composition layer at a temperature equal to or higher than the softening point Ts of the lead-based glass composition (see FIG. 5).
  • the temperature exceeds the predetermined temperature Tp at the point where the DTA curve intersects. It is even more preferable to fire the glass composition layer at a temperature (see FIG. 5).
  • the glass composition layer is preferably fired in a wet oxygen gas atmosphere.
  • (G) Roughened region forming step Next, a roughened surface is formed to increase the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the portion 130 where the Ni-plated electrode film is formed.
  • the formation region 132 is formed (see FIG. 4B).
  • Electrode Formation Step Ni plating is performed on the semiconductor substrate to form the anode electrode 134 on the roughened region 132, and the cathode electrode 136 is formed on the other surface of the semiconductor substrate (FIG. 4C). )reference.).
  • Each electrode is annealed at a temperature of 600 ° C. to 800 ° C. in a nitrogen atmosphere.
  • the mesa semiconductor element (pn diode) 102 is manufactured by cutting the semiconductor substrate at the center of the lead-based glass layer 124 by dicing or the like to chip the semiconductor substrate (see FIG. 4 (d).)
  • the resin-encapsulated semiconductor device 10 according to the embodiment can be manufactured.
  • FIG. 6 is a diagram for explaining the effect of the resin-encapsulated semiconductor device 10 according to the embodiment.
  • FIG. 6A is a diagram illustrating a state when a reverse voltage is applied to the resin-encapsulated semiconductor device 10 according to the embodiment
  • FIG. 6B illustrates the resin-encapsulated semiconductor device according to the comparative example. It is a figure which shows a mode when a reverse direction voltage is applied. In FIG. 6, the broken line indicates the tip of the depletion layer.
  • a resin-encapsulated semiconductor device according to a comparative example is obtained by molding a conventional mesa-type semiconductor element 900 (no base oxide layer, glass composition is baked at 870 ° C. in a wet oxygen atmosphere) with resin, and encapsulating the resin. This is a stationary semiconductor device.
  • the BT test in FIG. 6 is a high temperature reverse bias test.
  • the lead-based glass layer has a groove A glass composition for forming a glass composition layer composed of a lead-based glass composition so as to coat a base oxide layer by oxidizing the inner surface to form a base oxide layer, and to cover the inner surface of the groove via the base oxide layer Since it is formed by implementing a layer formation process and the baking process which bakes a glass composition layer at the temperature below melting point Tf of a lead-type glass composition, from Test Example 1 mentioned later As can be seen, the charge density of the lead-based glass layer can be changed from minus to plus. As a result, it is possible to suppress the depletion layer from extending toward the end of the outer peripheral taper region during the high temperature reverse bias test (see FIG. 6). The leakage current that increases during the bias test can be reduced as compared with the conventional case.
  • the resin-encapsulated semiconductor device according to the embodiment (and the resin-encapsulated semiconductor device manufactured by the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment) is a conventional resin-encapsulated semiconductor device.
  • a resin-encapsulated semiconductor device having a high temperature reverse bias tolerance higher than that of a conventional resin-encapsulated semiconductor device while having a structure in which a mesa-type semiconductor element is molded with resin is obtained by molding a mesa semiconductor element with a resin.
  • the manufactured resin-encapsulated semiconductor device is a resin-encapsulated semiconductor device having a high temperature reverse bias tolerance higher than that of a conventional resin-encapsulated semiconductor device.
  • the glass composition layer was fired at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 and FIG. This is because when the glass composition layer is fired at a temperature exceeding the melting point Tf of the glass composition, the charge density of the lead-based glass layer cannot be changed from minus to plus.
  • the glass composition layer is fired at a temperature equal to or higher than the softening point Ts of the lead-based glass composition because the glass composition layer is heated at a temperature lower than the softening point Ts of the lead-based glass composition. This is because when fired, the glass composition layer cannot be sufficiently fired, and only a glass layer having many defects can be obtained.
  • the glass composition layer when a glass composition mainly composed of lead silicate is used, it is preferable to fire the glass composition layer at a temperature in the range of 760 ° C. to 840 ° C., and in the range of 800 ° C. to 840 ° C. More preferably, the glass composition layer is fired at a temperature.
  • the glass composition layer is fired in a wet oxygen gas atmosphere, as can be seen from Test Example 1 described later, when the glass composition layer is fired in a dry oxygen gas atmosphere. This is because the charge density of the lead-based glass layer cannot be changed from minus to plus.
  • the base oxide layer is formed at a temperature within the range of 950 ° C. to 1150 ° C. when the glass composition layer is fired at a temperature of less than 950 ° C. This is because the charge density of the system glass layer cannot be changed from minus to plus. On the other hand, when the glass composition layer is baked at a temperature exceeding 1050 ° C., the electrical characteristics of the semiconductor element may be affected.
  • FIG. 7 is a chart showing the conditions and results of Test Example 1. Twenty-four samples were produced as follows. Of these 20 samples (Samples 2-6, 8-12, 14-18, 20-24), one surface of the n ⁇ -type silicon substrate under a predetermined temperature condition (850 ° C. to 1050 ° C.) Is oxidized to form a base oxide layer having a predetermined thickness (requires confirmation of 20 nm), and thereafter a glass composition layer having a predetermined thickness (20 ⁇ m to 30 ⁇ m) is formed by electrophoresis, followed by a predetermined temperature condition ( 820 ° C.
  • a predetermined temperature condition 820 ° C.
  • a glass composition layer having a predetermined thickness was formed on one surface of the n ⁇ -type silicon substrate without forming a base oxide layer. Then, under a predetermined temperature condition (820 ° C. or 870 ° C.) and a predetermined atmosphere condition (pressure: normal pressure, flow rate: 3 to 9 L / min, atmosphere: dry pure oxygen condition or wet pure oxygen condition), 15 The glass composition layer was baked for a minute. Thereafter, platinum electrodes were formed on the other surface of the n ⁇ -type silicon substrate and the surface of the glass layer.
  • Samples 2, 8, 14, and 20 form a base oxide layer at 850 ° C.
  • Samples 3, 9, 15, and 21 form a base oxide layer at 900 ° C.
  • Samples 4, 10, 16, and 22 Forms a base oxide layer at 950 ° C.
  • samples 5, 11, 17, and 23 form a base oxide layer at 1000 ° C.
  • samples 6, 12, 18, and 24 form a base oxide layer at 1050 ° C. did.
  • Samples 1 to 12 fired the glass composition layer in a dry oxygen atmosphere
  • samples 13 to 24 fired the glass composition layer in a wet oxygen gas atmosphere.
  • the glass composition layer was fired at 820 ° C.
  • the glass composition layer was sintered at 870 ° C.
  • the charge density Nss takes a positive value even when the glass composition layer is fired at 840 ° C. Furthermore, it has been found by subsequent experiments that when the glass composition layer is fired at a temperature equal to or lower than the melting point Tf, the charge density Nss takes a positive value.
  • a temperature equal to or higher than the softening point Ts preferably, when a line parallel to the horizontal axis is drawn on the high temperature side from a point indicating the glass transition point Tg in the DTA curve of the glass composition. It has been found that when the glass composition layer is baked at a temperature that is equal to or higher than a predetermined temperature Tp at the intersecting point, the baking of the glass composition layer can be completed in a relatively short time (for example, 30 minutes or less). .
  • Test Example 2 A resin-encapsulated semiconductor device (withstand voltage of 600 V) was fabricated and used as a sample by the same method as the method for producing the resin-encapsulated semiconductor device according to the embodiment.
  • Sample 25 Example
  • Sample 26 Comparative Example
  • Sample 25 was obtained by forming the base oxide layer at a temperature of 1000 ° C. and firing the glass composition layer at a temperature of 820 ° C. and a wet oxygen atmosphere.
  • Sample 26 Comparative Example
  • the high temperature reverse bias tolerance is a state in which each sample is put into a constant temperature bath / high temperature reverse bias tester set at a temperature of 150 ° C., and a voltage of 480 V (80% of the withstand voltage) is applied between the anode electrode and the cathode electrode. The reverse current was measured every 10 minutes for 1000 hours.
  • FIG. 8 is a diagram showing the results of the high-temperature reverse bias test in Test Example 2.
  • the solid line indicates the reverse current for the sample 25 (Example), and the broken line indicates the reverse current for the sample 26 (Comparative Example).
  • the leak current (reverse current) continues to increase even after the leak current (reverse current) increases as the temperature rises immediately after the start of the high temperature reverse bias test. I understood that. It was confirmed that the leak current (reverse current) after 100 hours increased to about 10 times the initial leak current (reverse current).
  • the resin-encapsulated semiconductor device and the method for producing the resin-encapsulated semiconductor device of the present invention have been described based on the above embodiment, but the present invention is not limited to this and does not depart from the gist thereof. For example, the following modifications are possible.
  • the base oxide layer is formed by the thermal oxidation method using dry oxygen (DryO 2 ), but the present invention is not limited to this.
  • the insulating layer may be formed by a thermal oxidation method using dry oxygen and nitrogen (DryO 2 + N 2 ), or may be formed by a thermal oxidation method using wet oxygen (WetO 2 ). Then, the insulating layer may be formed by a thermal oxidation method using wet oxygen and nitrogen (WetO 2 + N 2 ).
  • the mesa type semiconductor element composed of a diode (pn diode) is used.
  • the present invention is not limited to this.
  • a mesa semiconductor element made of thyristor may be used.
  • the present invention can be applied to all semiconductor devices (for example, power MOSFET, IGBT, etc.) in which a pn junction is exposed.
  • FIG. 9 is a diagram for explaining a mesa semiconductor device 200 according to a modification.
  • a resin-encapsulated semiconductor device 14 (not shown) according to the modification basically has the same configuration as the resin-encapsulated semiconductor device 10 according to the embodiment, but a mesa-type semiconductor element made of a thyristor is used. The point of using is different from the case of the resin-encapsulated semiconductor device 10 according to the embodiment.
  • the resin-encapsulated semiconductor device 14 has a mesa type having a mesa type semiconductor substrate having a pn junction exposed portion in an outer peripheral tapered region surrounding the mesa region and a lead-based glass layer 224 covering at least the outer peripheral tapered region.
  • the lead-based glass layer 224 oxidizes the inner surface of the groove to form a base oxide layer.
  • the mesa semiconductor element 200 in the modification is a thyristor, and as shown in FIG. 8, an n ⁇ type semiconductor layer 210 and a first p + type semiconductor layer disposed in contact with the n ⁇ type semiconductor layer 210. 212, a second p + type semiconductor layer 214 disposed in contact with the n ⁇ type semiconductor layer 210, an n + type semiconductor region 216 formed on the surface of the second p + type semiconductor layer 214, An anode electrode 234 connected to one p + type semiconductor layer 212, a cathode electrode 236 connected to an n + type semiconductor region 216, and a gate electrode 238 connected to the second p + type semiconductor layer 214. Prepare.
  • the resin-encapsulated semiconductor device 14 according to the modification is different from the resin-encapsulated semiconductor device 10 according to the embodiment in that the mesa-type semiconductor element made of thyristor is used.
  • the lead-based glass layer coats the inner surface of the groove with the base oxide layer by oxidizing the inner surface of the groove to form the base oxide layer.
  • the resin-encapsulated semiconductor according to the embodiment has a structure in which a mesa-type semiconductor element is molded with resin in the same manner as a conventional resin-encapsulated semiconductor device because it is formed by implementation.
  • Device 1 As in the case of, the resin-sealed-type semiconductor device having a high high-temperature reverse bias capability than conventional resin-sealed semiconductor device. That is, the resin-encapsulated semiconductor device 14 according to the modification is a resin-encapsulated semiconductor device manufactured by molding a mesa-type semiconductor element with resin and has a higher temperature than that of a conventional resin-encapsulated semiconductor device. A resin-encapsulated semiconductor device having a reverse bias tolerance is obtained.
  • the glass layer is formed using the glass composition containing lead silicate as a main component, but the present invention is not limited to this. For example, you may form a glass layer using the glass composition which does not contain lead substantially.
  • SYMBOLS 10 Resin sealing type semiconductor device, 20 ... Lead frame, 21, 22 ... Lead, 23 ... Die pad, 30 ... Gold wire, 40 ... Resin, 100, 200 ... Mesa type semiconductor element, 110, 910 ... n ⁇ - > type semiconductor Layer 112,912 ... p + type semiconductor layer 114,914 ... n - type semiconductor layer 116,118,916,918 ... oxide film 120,920 ... groove 121,221 ... underlying oxide layer 124,924 ... Glass layer, 126,926 ... Photoresist, 130,930 ... Ni plating electrode film forming part, 132,932 ...

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PCT/JP2012/080796 2012-11-28 2012-11-28 樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置 WO2014083647A1 (ja)

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JP2013505243A JP5308595B1 (ja) 2012-11-28 2012-11-28 樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置
CN201280033933.XA CN103975422B (zh) 2012-11-28 2012-11-28 树脂封装型半导体装置的制造方法以及树脂封装型半导体装置
PCT/JP2012/080796 WO2014083647A1 (ja) 2012-11-28 2012-11-28 樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置
TW102123956A TWI556330B (zh) 2012-11-28 2013-07-04 Resin Package Type semiconductor device, and a resin Package Type semiconductor device

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CN104952909A (zh) * 2014-09-03 2015-09-30 安徽省祁门县黄山电器有限责任公司 一种二极管芯片的结终端结构
CN104599963B (zh) * 2015-01-15 2017-12-19 苏州启澜功率电子有限公司 一种台面芯片双面电泳玻璃钝化工艺
CN107293601B (zh) * 2016-04-12 2021-10-22 朱江 一种肖特基半导体装置及其制备方法
CN105932070A (zh) * 2016-06-17 2016-09-07 山东芯诺电子科技有限公司 一种低功耗高浪涌能力的二极管整流芯片及其生产工艺
CN112444717A (zh) * 2019-08-29 2021-03-05 珠海格力电器股份有限公司 一种塑封料与芯片匹配度的验证方法
CN112103197B (zh) * 2020-11-09 2021-02-09 浙江里阳半导体有限公司 半导体分立器件的制造方法及其钝化装置
CN114171416B (zh) * 2022-02-14 2022-06-03 浙江里阳半导体有限公司 一种tvs芯片及其玻璃钝化方法、制造方法

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