WO2014083647A1 - Method for manufacturing resin-sealed semiconductor device, and resin-sealed semiconductor device - Google Patents
Method for manufacturing resin-sealed semiconductor device, and resin-sealed semiconductor device Download PDFInfo
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- WO2014083647A1 WO2014083647A1 PCT/JP2012/080796 JP2012080796W WO2014083647A1 WO 2014083647 A1 WO2014083647 A1 WO 2014083647A1 JP 2012080796 W JP2012080796 W JP 2012080796W WO 2014083647 A1 WO2014083647 A1 WO 2014083647A1
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- glass composition
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 238
- 238000000034 method Methods 0.000 title claims description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 41
- 239000011521 glass Substances 0.000 claims abstract description 180
- 239000000203 mixture Substances 0.000 claims abstract description 128
- 239000011347 resin Substances 0.000 claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 40
- 238000010304 firing Methods 0.000 claims abstract description 32
- 238000000465 moulding Methods 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 39
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- 238000002844 melting Methods 0.000 claims description 15
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- 230000002093 peripheral effect Effects 0.000 claims description 14
- 238000007789 sealing Methods 0.000 claims description 13
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 7
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- 238000004455 differential thermal analysis Methods 0.000 description 10
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- 229910052760 oxygen Inorganic materials 0.000 description 10
- 238000012986 modification Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
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- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
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- 238000002474 experimental method Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
- C03C3/102—Glass compositions containing silica with 40% to 90% silica, by weight containing lead
- C03C3/105—Glass compositions containing silica with 40% to 90% silica, by weight containing lead containing aluminium
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
- C03C8/24—Fusion seal compositions being frit compositions having non-frit additions, i.e. for use as seals between dissimilar materials, e.g. glass and metal; Glass solders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a method for manufacturing a resin-encapsulated semiconductor device and a resin-encapsulated semiconductor device.
- FIG. 10 is a view for explaining a conventional mesa type semiconductor device 900.
- a conventional mesa semiconductor device 900 includes a mesa semiconductor substrate 908 having a pn junction exposed portion C in an outer peripheral taper region B surrounding the mesa region A, and a glass layer 924 covering the outer peripheral taper region B. And have.
- the glass layer 924 is a glass layer for passivation.
- reference numeral 910 denotes an n ⁇ type semiconductor layer
- reference numeral 912 denotes a p + type semiconductor layer
- reference numeral 914 denotes an n + semiconductor layer
- reference numeral 916a denotes a silicon oxide film
- reference numeral 934 denotes An anode electrode layer is shown
- a reference numeral 936 denotes a cathode electrode layer.
- the conventional mesa type semiconductor element 900 it is possible to configure a semiconductor device having a higher breakdown voltage than a planar type semiconductor element.
- the conventional mesa semiconductor element 900 has a high temperature when it is molded with resin to form a resin-encapsulated semiconductor device (conventional resin-encapsulated semiconductor device). It has become clear that there is a problem that the reverse bias tolerance is low and it is difficult to use it in applications that are used under severe conditions.
- the present invention has been made to solve the above-described problems, and is a resin-encapsulated semiconductor device manufactured by molding a mesa-type semiconductor element with a resin, which is a conventional resin-encapsulated semiconductor device.
- An object of the present invention is to provide a resin-encapsulated semiconductor device having a higher high-temperature reverse bias tolerance. Moreover, it aims at providing the manufacturing method of the resin sealing type
- a method for manufacturing a resin-encapsulated semiconductor device includes a semiconductor substrate preparation step of preparing a semiconductor substrate having a pn junction parallel to a main surface, and the pn junction is exceeded from one surface of the semiconductor substrate.
- a groove forming step for forming a groove having a depth, a glass layer forming step for forming a lead-based glass layer so as to cover an inner surface of the groove, and a mesa mold by cutting the semiconductor substrate along the groove A method for producing a resin-encapsulated semiconductor device, comprising: a semiconductor substrate cutting step for producing a semiconductor element; and a resin encapsulation step for encapsulating the mesa semiconductor element with a molding resin in this order, the glass layer
- the forming step includes a base oxide layer forming step in which an inner surface of the groove is oxidized to form a base oxide layer, and a glass composition made of a lead-based glass composition so as to cover the inner surface of the groove through the base oxide layer.
- Form a material layer A glass composition layer forming step that, characterized in that it comprises a firing step of firing the glass composition layer at a temperature ⁇ point Tf of the lead-based glass composition.
- the melting point Tf means the temperature of the shoulder of the first heat generating portion of the DTA curve in the lead-based glass composition (see FIG. 5 described later).
- the temperature of the shoulder of the 1st heat absorption part of the DTA curve in a lead-type glass composition is a glass transition point Tg.
- the firing step it is preferable to fire the glass composition layer at a temperature equal to or higher than the softening point Ts of the lead-based glass composition.
- the glass composition layer is baked in a wet oxygen gas atmosphere.
- the base oxide layer having a thickness of 10 nm to 100 nm is formed in the base oxide layer forming step.
- the base oxide layer is formed at a temperature within a range of 950 ° C. to 1150 ° C. in the base oxide layer forming step.
- a resin-encapsulated semiconductor device of the present invention is a mesa semiconductor device having a mesa semiconductor substrate having a pn junction exposed portion in an outer peripheral taper region surrounding a mesa region and a lead-based glass layer covering the outer peripheral taper region.
- a molding resin for sealing the mesa semiconductor element wherein the glass layer forms a base oxide layer by oxidizing the inner surface of the groove to form a base oxide layer
- the glass composition layer is formed by performing a firing step of firing the glass composition layer at a temperature equal to or lower than the point Tf.
- the lead-based glass layer oxidizes the inner surface of the groove.
- a base oxide layer forming step of forming a base oxide layer, and a glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition so as to cover the inner surface of the groove via the base oxide layer Since it is formed by carrying out a firing step of firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 described later, It becomes possible to change the charge density of the glass layer from minus to plus.
- the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention) is similar to the conventional resin-encapsulated semiconductor device. While having a structure in which a mesa semiconductor element is molded with resin, a resin-encapsulated semiconductor device having a higher high-temperature reverse bias tolerance than a conventional resin-encapsulated semiconductor device is obtained. That is, the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention) is manufactured by molding a mesa semiconductor element with resin.
- the resin-encapsulated semiconductor device is a resin-encapsulated semiconductor device having higher high-temperature reverse bias tolerance than the conventional resin-encapsulated semiconductor device.
- the glass composition layer is usually fired at a temperature exceeding the melting point Tf of the lead-based glass composition for the purpose of easily removing bubbles generated in the glass layer during firing. As a result, lead-based glass is formed.
- the charge density of the glass layer is changed from minus to plus. It is still unclear why this is possible.
- the glass composition layer was fired at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 and FIG. This is because when the glass composition layer is fired at a temperature exceeding the melting point Tf of the glass composition (870 ° C. in this case), the charge density of the glass layer cannot be changed from minus to plus.
- a method of forming a wide groove (mesa groove) in the process of manufacturing a mesa semiconductor element, and (2) a mesa semiconductor element A method of forming a deep groove (mesa groove) by using a diffusion wafer in the manufacturing process, (3) a method of using a wafer having a low specific resistance, and (4) a method of forming a lead-based glass layer thick are also conceivable.
- the method (1) has a problem that the manufacturing cost of the product increases due to the increase in the chip area.
- the use of a diffusion wafer increases the manufacturing cost of the product due to the fact that the process becomes difficult due to the high price of the wafer and the necessity of deep groove formation. There is a problem of end. Further, the method (3) has a problem that it is difficult to ensure a withstand voltage. The method (4) has a problem that the wafer is warped or easily broken during the process. On the other hand, according to the method for manufacturing a resin-encapsulated semiconductor device and the resin-encapsulated semiconductor device of the present invention, it is possible to increase the high temperature reverse bias tolerance without causing the above-described problems.
- a “glass composition mainly composed of lead silicate” that has been widely used in the past is suitable as the lead-based glass composition. Can be used.
- FIG. 1 is a view for explaining a resin encapsulated semiconductor device 10 according to the embodiment.
- FIG. 1A is a perspective view of the resin-encapsulated semiconductor device 10
- FIG. 1B is a plan view of the resin-encapsulated semiconductor device 10 with the resin removed
- FIG. 3 is a side view of the sealed semiconductor device 10 with a resin removed.
- FIG. FIG. 2 is a view for explaining the mesa semiconductor device 100 according to the embodiment.
- the resin-encapsulated semiconductor device 10 includes a mesa semiconductor element 100 and a molding resin 40 that encapsulates the mesa semiconductor element 100.
- the mesa semiconductor element 100 is placed on the die pad 23 in the lead frame 20 including the lead 21, the lead 22, and the die pad 23.
- One electrode of the mesa semiconductor element 100 is connected to the lead 21 via the die pad 23, and the other electrode of the mesa semiconductor element 100 is connected to the lead 22 via the gold wire 30.
- the mesa semiconductor element 100 includes a mesa semiconductor substrate 108 having a pn junction exposed portion C in an outer peripheral tapered region B surrounding the mesa region A and a lead-based glass layer 124 covering at least the outer peripheral tapered region B.
- the outer peripheral taper region B is covered with the lead-based glass layer 124 through the base oxide layer 211.
- the lead-based glass layer 124 is a glass containing lead silicate as a main component (for example, glass containing SiO 2 : 75.0%, PbO: 20.0%, Al 2 O 3 : 5.0% in a molar ratio). Consists of.
- the mesa type semiconductor substrate 108 includes an n ⁇ type semiconductor layer (n ⁇ type silicon substrate) 110, a p + type semiconductor layer 112 formed by diffusion of p type impurities from one surface of the n ⁇ type semiconductor layer 110, and , An n + type semiconductor layer 114 formed by diffusion of an n type impurity from the other surface of the n ⁇ type semiconductor layer 110.
- the mesa semiconductor device 100 is a pn diode.
- reference numeral 134 denotes an anode electrode layer
- reference numeral 136 denotes a cathode electrode layer.
- the lead-based glass layer 124 includes a base oxide layer forming step of forming the base oxide layer by oxidizing the inner surface of the groove, and the base oxide layer on the inner surface of the groove.
- the resin sealed semiconductor device 10 according to the embodiment can be manufactured by the following method (the manufacturing method of the resin sealed semiconductor device according to the embodiment).
- 3 and 4 are views for explaining the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment.
- 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (d) are process diagrams.
- FIG. 5 is a diagram showing a DTA (differential thermal analysis) curve of the glass composition.
- the method for manufacturing a resin-encapsulated semiconductor device includes a “semiconductor substrate forming step”, a “groove forming step”, a “underlying oxide layer forming step”, and “lead-based glass”.
- “Layer formation process” “Photoresist formation process”, “Oxide film removal process”, “Roughened area formation process”, “Electrode formation process”, “Semiconductor substrate cutting process” and “Resin sealing process” in this order To implement.
- the manufacturing method of the resin-encapsulated semiconductor device according to the embodiment will be described in the order of steps.
- n + type semiconductor layer 112 is diffused from one surface of n ⁇ type semiconductor substrate (n ⁇ type silicon substrate) 110, and n type impurities from the other surface are diffused.
- An n + type semiconductor layer 114 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed.
- oxide films 116 and 118 are formed on the surfaces of the p + type semiconductor layer 112 and the n + type semiconductor layer 114 by thermal oxidation.
- a base oxide layer 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (see FIG. 3B). ).
- the thickness of the base oxide layer 121 is in the range of 10 nm to 100 nm (for example, 20 nm).
- the formation of the base oxide layer 121 is performed by placing the semiconductor substrate in a diffusion furnace and then treating the substrate at a temperature in the range of 950 ° C. to 1050 ° C. for 5 minutes to 30 minutes while flowing oxygen gas. If the thickness of the underlying oxide layer 121 is less than 10 nm, the reverse current reduction effect may not be obtained. On the other hand, if the thickness of the base oxide layer 121 exceeds 100 nm, a layer made of a glass composition may not be formed by electrophoresis in the next glass layer forming step.
- the glass composition is a glass composition containing lead silicate as a main component (for example, a glass composition containing SiO 2 : 75.0%, PbO: 20.0%, Al 2 O 3 : 5.0% in molar ratio). ) Is used.
- the glass composition layer is formed so as to cover the inner surface of the groove 120 via the base oxide layer 121. Therefore, the exposed pn junction in the trench 120 is covered with the lead-based glass layer 124 via the base oxide layer 121.
- Calcination of the glass composition layer is performed by firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition (see FIG. 5).
- the firing step it is preferable to fire the glass composition layer at a temperature equal to or higher than the softening point Ts of the lead-based glass composition (see FIG. 5).
- the temperature exceeds the predetermined temperature Tp at the point where the DTA curve intersects. It is even more preferable to fire the glass composition layer at a temperature (see FIG. 5).
- the glass composition layer is preferably fired in a wet oxygen gas atmosphere.
- (G) Roughened region forming step Next, a roughened surface is formed to increase the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the portion 130 where the Ni-plated electrode film is formed.
- the formation region 132 is formed (see FIG. 4B).
- Electrode Formation Step Ni plating is performed on the semiconductor substrate to form the anode electrode 134 on the roughened region 132, and the cathode electrode 136 is formed on the other surface of the semiconductor substrate (FIG. 4C). )reference.).
- Each electrode is annealed at a temperature of 600 ° C. to 800 ° C. in a nitrogen atmosphere.
- the mesa semiconductor element (pn diode) 102 is manufactured by cutting the semiconductor substrate at the center of the lead-based glass layer 124 by dicing or the like to chip the semiconductor substrate (see FIG. 4 (d).)
- the resin-encapsulated semiconductor device 10 according to the embodiment can be manufactured.
- FIG. 6 is a diagram for explaining the effect of the resin-encapsulated semiconductor device 10 according to the embodiment.
- FIG. 6A is a diagram illustrating a state when a reverse voltage is applied to the resin-encapsulated semiconductor device 10 according to the embodiment
- FIG. 6B illustrates the resin-encapsulated semiconductor device according to the comparative example. It is a figure which shows a mode when a reverse direction voltage is applied. In FIG. 6, the broken line indicates the tip of the depletion layer.
- a resin-encapsulated semiconductor device according to a comparative example is obtained by molding a conventional mesa-type semiconductor element 900 (no base oxide layer, glass composition is baked at 870 ° C. in a wet oxygen atmosphere) with resin, and encapsulating the resin. This is a stationary semiconductor device.
- the BT test in FIG. 6 is a high temperature reverse bias test.
- the lead-based glass layer has a groove A glass composition for forming a glass composition layer composed of a lead-based glass composition so as to coat a base oxide layer by oxidizing the inner surface to form a base oxide layer, and to cover the inner surface of the groove via the base oxide layer Since it is formed by implementing a layer formation process and the baking process which bakes a glass composition layer at the temperature below melting point Tf of a lead-type glass composition, from Test Example 1 mentioned later As can be seen, the charge density of the lead-based glass layer can be changed from minus to plus. As a result, it is possible to suppress the depletion layer from extending toward the end of the outer peripheral taper region during the high temperature reverse bias test (see FIG. 6). The leakage current that increases during the bias test can be reduced as compared with the conventional case.
- the resin-encapsulated semiconductor device according to the embodiment (and the resin-encapsulated semiconductor device manufactured by the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment) is a conventional resin-encapsulated semiconductor device.
- a resin-encapsulated semiconductor device having a high temperature reverse bias tolerance higher than that of a conventional resin-encapsulated semiconductor device while having a structure in which a mesa-type semiconductor element is molded with resin is obtained by molding a mesa semiconductor element with a resin.
- the manufactured resin-encapsulated semiconductor device is a resin-encapsulated semiconductor device having a high temperature reverse bias tolerance higher than that of a conventional resin-encapsulated semiconductor device.
- the glass composition layer was fired at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 and FIG. This is because when the glass composition layer is fired at a temperature exceeding the melting point Tf of the glass composition, the charge density of the lead-based glass layer cannot be changed from minus to plus.
- the glass composition layer is fired at a temperature equal to or higher than the softening point Ts of the lead-based glass composition because the glass composition layer is heated at a temperature lower than the softening point Ts of the lead-based glass composition. This is because when fired, the glass composition layer cannot be sufficiently fired, and only a glass layer having many defects can be obtained.
- the glass composition layer when a glass composition mainly composed of lead silicate is used, it is preferable to fire the glass composition layer at a temperature in the range of 760 ° C. to 840 ° C., and in the range of 800 ° C. to 840 ° C. More preferably, the glass composition layer is fired at a temperature.
- the glass composition layer is fired in a wet oxygen gas atmosphere, as can be seen from Test Example 1 described later, when the glass composition layer is fired in a dry oxygen gas atmosphere. This is because the charge density of the lead-based glass layer cannot be changed from minus to plus.
- the base oxide layer is formed at a temperature within the range of 950 ° C. to 1150 ° C. when the glass composition layer is fired at a temperature of less than 950 ° C. This is because the charge density of the system glass layer cannot be changed from minus to plus. On the other hand, when the glass composition layer is baked at a temperature exceeding 1050 ° C., the electrical characteristics of the semiconductor element may be affected.
- FIG. 7 is a chart showing the conditions and results of Test Example 1. Twenty-four samples were produced as follows. Of these 20 samples (Samples 2-6, 8-12, 14-18, 20-24), one surface of the n ⁇ -type silicon substrate under a predetermined temperature condition (850 ° C. to 1050 ° C.) Is oxidized to form a base oxide layer having a predetermined thickness (requires confirmation of 20 nm), and thereafter a glass composition layer having a predetermined thickness (20 ⁇ m to 30 ⁇ m) is formed by electrophoresis, followed by a predetermined temperature condition ( 820 ° C.
- a predetermined temperature condition 820 ° C.
- a glass composition layer having a predetermined thickness was formed on one surface of the n ⁇ -type silicon substrate without forming a base oxide layer. Then, under a predetermined temperature condition (820 ° C. or 870 ° C.) and a predetermined atmosphere condition (pressure: normal pressure, flow rate: 3 to 9 L / min, atmosphere: dry pure oxygen condition or wet pure oxygen condition), 15 The glass composition layer was baked for a minute. Thereafter, platinum electrodes were formed on the other surface of the n ⁇ -type silicon substrate and the surface of the glass layer.
- Samples 2, 8, 14, and 20 form a base oxide layer at 850 ° C.
- Samples 3, 9, 15, and 21 form a base oxide layer at 900 ° C.
- Samples 4, 10, 16, and 22 Forms a base oxide layer at 950 ° C.
- samples 5, 11, 17, and 23 form a base oxide layer at 1000 ° C.
- samples 6, 12, 18, and 24 form a base oxide layer at 1050 ° C. did.
- Samples 1 to 12 fired the glass composition layer in a dry oxygen atmosphere
- samples 13 to 24 fired the glass composition layer in a wet oxygen gas atmosphere.
- the glass composition layer was fired at 820 ° C.
- the glass composition layer was sintered at 870 ° C.
- the charge density Nss takes a positive value even when the glass composition layer is fired at 840 ° C. Furthermore, it has been found by subsequent experiments that when the glass composition layer is fired at a temperature equal to or lower than the melting point Tf, the charge density Nss takes a positive value.
- a temperature equal to or higher than the softening point Ts preferably, when a line parallel to the horizontal axis is drawn on the high temperature side from a point indicating the glass transition point Tg in the DTA curve of the glass composition. It has been found that when the glass composition layer is baked at a temperature that is equal to or higher than a predetermined temperature Tp at the intersecting point, the baking of the glass composition layer can be completed in a relatively short time (for example, 30 minutes or less). .
- Test Example 2 A resin-encapsulated semiconductor device (withstand voltage of 600 V) was fabricated and used as a sample by the same method as the method for producing the resin-encapsulated semiconductor device according to the embodiment.
- Sample 25 Example
- Sample 26 Comparative Example
- Sample 25 was obtained by forming the base oxide layer at a temperature of 1000 ° C. and firing the glass composition layer at a temperature of 820 ° C. and a wet oxygen atmosphere.
- Sample 26 Comparative Example
- the high temperature reverse bias tolerance is a state in which each sample is put into a constant temperature bath / high temperature reverse bias tester set at a temperature of 150 ° C., and a voltage of 480 V (80% of the withstand voltage) is applied between the anode electrode and the cathode electrode. The reverse current was measured every 10 minutes for 1000 hours.
- FIG. 8 is a diagram showing the results of the high-temperature reverse bias test in Test Example 2.
- the solid line indicates the reverse current for the sample 25 (Example), and the broken line indicates the reverse current for the sample 26 (Comparative Example).
- the leak current (reverse current) continues to increase even after the leak current (reverse current) increases as the temperature rises immediately after the start of the high temperature reverse bias test. I understood that. It was confirmed that the leak current (reverse current) after 100 hours increased to about 10 times the initial leak current (reverse current).
- the resin-encapsulated semiconductor device and the method for producing the resin-encapsulated semiconductor device of the present invention have been described based on the above embodiment, but the present invention is not limited to this and does not depart from the gist thereof. For example, the following modifications are possible.
- the base oxide layer is formed by the thermal oxidation method using dry oxygen (DryO 2 ), but the present invention is not limited to this.
- the insulating layer may be formed by a thermal oxidation method using dry oxygen and nitrogen (DryO 2 + N 2 ), or may be formed by a thermal oxidation method using wet oxygen (WetO 2 ). Then, the insulating layer may be formed by a thermal oxidation method using wet oxygen and nitrogen (WetO 2 + N 2 ).
- the mesa type semiconductor element composed of a diode (pn diode) is used.
- the present invention is not limited to this.
- a mesa semiconductor element made of thyristor may be used.
- the present invention can be applied to all semiconductor devices (for example, power MOSFET, IGBT, etc.) in which a pn junction is exposed.
- FIG. 9 is a diagram for explaining a mesa semiconductor device 200 according to a modification.
- a resin-encapsulated semiconductor device 14 (not shown) according to the modification basically has the same configuration as the resin-encapsulated semiconductor device 10 according to the embodiment, but a mesa-type semiconductor element made of a thyristor is used. The point of using is different from the case of the resin-encapsulated semiconductor device 10 according to the embodiment.
- the resin-encapsulated semiconductor device 14 has a mesa type having a mesa type semiconductor substrate having a pn junction exposed portion in an outer peripheral tapered region surrounding the mesa region and a lead-based glass layer 224 covering at least the outer peripheral tapered region.
- the lead-based glass layer 224 oxidizes the inner surface of the groove to form a base oxide layer.
- the mesa semiconductor element 200 in the modification is a thyristor, and as shown in FIG. 8, an n ⁇ type semiconductor layer 210 and a first p + type semiconductor layer disposed in contact with the n ⁇ type semiconductor layer 210. 212, a second p + type semiconductor layer 214 disposed in contact with the n ⁇ type semiconductor layer 210, an n + type semiconductor region 216 formed on the surface of the second p + type semiconductor layer 214, An anode electrode 234 connected to one p + type semiconductor layer 212, a cathode electrode 236 connected to an n + type semiconductor region 216, and a gate electrode 238 connected to the second p + type semiconductor layer 214. Prepare.
- the resin-encapsulated semiconductor device 14 according to the modification is different from the resin-encapsulated semiconductor device 10 according to the embodiment in that the mesa-type semiconductor element made of thyristor is used.
- the lead-based glass layer coats the inner surface of the groove with the base oxide layer by oxidizing the inner surface of the groove to form the base oxide layer.
- the resin-encapsulated semiconductor according to the embodiment has a structure in which a mesa-type semiconductor element is molded with resin in the same manner as a conventional resin-encapsulated semiconductor device because it is formed by implementation.
- Device 1 As in the case of, the resin-sealed-type semiconductor device having a high high-temperature reverse bias capability than conventional resin-sealed semiconductor device. That is, the resin-encapsulated semiconductor device 14 according to the modification is a resin-encapsulated semiconductor device manufactured by molding a mesa-type semiconductor element with resin and has a higher temperature than that of a conventional resin-encapsulated semiconductor device. A resin-encapsulated semiconductor device having a reverse bias tolerance is obtained.
- the glass layer is formed using the glass composition containing lead silicate as a main component, but the present invention is not limited to this. For example, you may form a glass layer using the glass composition which does not contain lead substantially.
- SYMBOLS 10 Resin sealing type semiconductor device, 20 ... Lead frame, 21, 22 ... Lead, 23 ... Die pad, 30 ... Gold wire, 40 ... Resin, 100, 200 ... Mesa type semiconductor element, 110, 910 ... n ⁇ - > type semiconductor Layer 112,912 ... p + type semiconductor layer 114,914 ... n - type semiconductor layer 116,118,916,918 ... oxide film 120,920 ... groove 121,221 ... underlying oxide layer 124,924 ... Glass layer, 126,926 ... Photoresist, 130,930 ... Ni plating electrode film forming part, 132,932 ...
Abstract
A resin-sealed semiconductor device (10) of the present invention is provided with a mesa-type semiconductor element (100), and a molding resin (40) that seals the mesa-type semiconductor element (100). In the resin-sealed semiconductor device (10), a lead-based glass layer (124) is formed by performing: a base oxide layer forming step for forming a base oxide layer (121) by oxidizing the inner surface of a trench; a glass composition layer forming step for forming a glass composition layer formed of a lead-based glass composition such that the inner surface of the trench is covered with the glass composition layer with the base oxide layer therebetween; and a firing step for firing the glass composition layer at a temperature equal to or lower than the temperature of a deformation point(Tf) of the lead-based glass composition.
This resin-sealed semiconductor device has higher high-temperature reverse bias tolerance than conventional resin-sealed semiconductor devices, while having a structure wherein a mesa-type semiconductor element is molded with a resin in the same manner as in the conventional resin-sealed semiconductor devices.
Description
本発明は、樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置に関する。
The present invention relates to a method for manufacturing a resin-encapsulated semiconductor device and a resin-encapsulated semiconductor device.
従来、メサ領域を囲む外周テーパ領域にｐｎ接合が露出した構造を有するメサ型半導体素子が知られている（例えば、特許文献１及び２参照。）。図１０は、従来のメサ型半導体素子９００を説明するために示す図である。
Conventionally, mesa type semiconductor elements having a structure in which a pn junction is exposed in an outer peripheral tapered region surrounding a mesa region are known (for example, refer to Patent Documents 1 and 2). FIG. 10 is a view for explaining a conventional mesa type semiconductor device 900.
従来のメサ型半導体素子９００は、図１０に示すように、メサ領域Ａを囲む外周テーパ領域Ｂにｐｎ接合露出部Ｃを有するメサ型半導体基体９０８と、外周テーパ領域Ｂを被覆するガラス層９２４とを有する。ガラス層９２４は、パッシベーション用のガラス層である。なお、図１０中、符号９１０はｎ－型半導体層を示し、符号９１２はｐ＋型半導体層を示し、符号９１４はｎ＋半導体層を示し、符号９１６ａはシリコン酸化膜を示し、符号９３４はアノード電極層を示し、符号９３６はカソード電極層を示す。
As shown in FIG. 10, a conventional mesa semiconductor device 900 includes a mesa semiconductor substrate 908 having a pn junction exposed portion C in an outer peripheral taper region B surrounding the mesa region A, and a glass layer 924 covering the outer peripheral taper region B. And have. The glass layer 924 is a glass layer for passivation. In FIG. 10, reference numeral 910 denotes an n − type semiconductor layer, reference numeral 912 denotes a p + type semiconductor layer, reference numeral 914 denotes an n + semiconductor layer, reference numeral 916a denotes a silicon oxide film, and reference numeral 934 denotes An anode electrode layer is shown, and a reference numeral 936 denotes a cathode electrode layer.
従来のメサ型半導体素子９００によれば、プレーナー型の半導体素子に比較して高耐圧の半導体素子を構成することが可能となる。
According to the conventional mesa type semiconductor element 900, it is possible to configure a semiconductor device having a higher breakdown voltage than a planar type semiconductor element.
しかしながら、本発明の発明者らの研究により、従来のメサ型半導体素子９００においては、これを樹脂でモールドして樹脂封止型半導体装置（従来の樹脂封止型半導体装置）としたときの高温逆バイアス耐量が低く、過酷な条件で使用する用途には使用することが難しいという問題があることが明らかになった。
However, as a result of research by the inventors of the present invention, the conventional mesa semiconductor element 900 has a high temperature when it is molded with resin to form a resin-encapsulated semiconductor device (conventional resin-encapsulated semiconductor device). It has become clear that there is a problem that the reverse bias tolerance is low and it is difficult to use it in applications that are used under severe conditions.
そこで、本発明は、上記した問題を解決するためになされたもので、メサ型半導体素子を樹脂でモールドして製造された樹脂封止型半導体装置であって、従来の樹脂封止型半導体装置よりも高い高温逆バイアス耐量を有する樹脂封止型半導体装置を提供することを目的とする。また、このような樹脂封止型半導体装置を製造可能な樹脂封止型半導体装置の製造方法を提供することを目的とする。
Accordingly, the present invention has been made to solve the above-described problems, and is a resin-encapsulated semiconductor device manufactured by molding a mesa-type semiconductor element with a resin, which is a conventional resin-encapsulated semiconductor device. An object of the present invention is to provide a resin-encapsulated semiconductor device having a higher high-temperature reverse bias tolerance. Moreover, it aims at providing the manufacturing method of the resin sealing type | mold semiconductor device which can manufacture such a resin sealing type | mold semiconductor device.
［１］本発明の樹脂封止型半導体装置の製造方法は、主面に平行なｐｎ接合を備える半導体基板を準備する半導体基板準備工程と、前記半導体基板の一方の表面から前記ｐｎ接合を超える深さの溝を形成する溝形成工程と、前記溝の内面を被覆するように鉛系ガラス層を形成するガラス層形成工程と、前記溝に沿って前記半導体基板を切断することにより、メサ型半導体素子を作製する半導体基板切断工程と、前記メサ型半導体素子をモールド用樹脂で封止する樹脂封止工程とをこの順序で含む樹脂封止型半導体装置の製造方法であって、前記ガラス層形成工程は、前記溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、前記溝の内面を前記下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、前記鉛系ガラス組成物の溶倒点Ｔｆ以下の温度で前記ガラス組成物層を焼成する焼成工程とを含むことを特徴とする。
[1] A method for manufacturing a resin-encapsulated semiconductor device according to the present invention includes a semiconductor substrate preparation step of preparing a semiconductor substrate having a pn junction parallel to a main surface, and the pn junction is exceeded from one surface of the semiconductor substrate. A groove forming step for forming a groove having a depth, a glass layer forming step for forming a lead-based glass layer so as to cover an inner surface of the groove, and a mesa mold by cutting the semiconductor substrate along the groove A method for producing a resin-encapsulated semiconductor device, comprising: a semiconductor substrate cutting step for producing a semiconductor element; and a resin encapsulation step for encapsulating the mesa semiconductor element with a molding resin in this order, the glass layer The forming step includes a base oxide layer forming step in which an inner surface of the groove is oxidized to form a base oxide layer, and a glass composition made of a lead-based glass composition so as to cover the inner surface of the groove through the base oxide layer. Form a material layer A glass composition layer forming step that, characterized in that it comprises a firing step of firing the glass composition layer at a temperature 溶倒 point Tf of the lead-based glass composition.
本明細書において、溶倒点Ｔｆとは、鉛系ガラス組成物におけるＤＴＡ曲線の第１発熱部の肩の温度をいう（後述する図５参照。）。なお、鉛系ガラス組成物におけるＤＴＡ曲線の第１吸熱部の肩の温度がガラス転移点Ｔｇである。
In the present specification, the melting point Tf means the temperature of the shoulder of the first heat generating portion of the DTA curve in the lead-based glass composition (see FIG. 5 described later). In addition, the temperature of the shoulder of the 1st heat absorption part of the DTA curve in a lead-type glass composition is a glass transition point Tg.
［２］本発明の樹脂封止型半導体装置の製造方法において、前記焼成工程においては、前記鉛系ガラス組成物の軟化点Ｔｓ以上の温度で前記ガラス組成物層を焼成することが好ましい。
[2] In the method for producing a resin-encapsulated semiconductor device of the present invention, in the firing step, it is preferable to fire the glass composition layer at a temperature equal to or higher than the softening point Ts of the lead-based glass composition.
［３］本発明の樹脂封止型半導体装置の製造方法において、前記焼成工程においては、前記鉛系ガラス組成物のＤＴＡ曲線におけるガラス転移点Ｔｇを示す点から高温側に横軸と平行な線を引いたときに当該ＤＴＡ曲線と交わる点における所定温度Ｔｐ以上の温度で前記ガラス組成物層を焼成することが好ましい。
[3] In the method for producing a resin-encapsulated semiconductor device of the present invention, in the firing step, a line parallel to the horizontal axis from the point showing the glass transition point Tg in the DTA curve of the lead-based glass composition to the high temperature side. It is preferable to fire the glass composition layer at a temperature equal to or higher than a predetermined temperature Tp at the point where the DTA curve intersects when.
［４］本発明の樹脂封止型半導体装置の製造方法において、前記焼成工程においては、湿潤酸素ガス雰囲気で前記ガラス組成物層を焼成することが好ましい。
[4] In the method for manufacturing a resin-encapsulated semiconductor device of the present invention, in the baking step, it is preferable that the glass composition layer is baked in a wet oxygen gas atmosphere.
［５］本発明の樹脂封止型半導体装置の製造方法において、前記下地酸化層形成工程においては、１０ｎｍ～１００ｎｍの厚さの前記下地酸化層を形成することが好ましい。
[5] In the method for manufacturing a resin-encapsulated semiconductor device of the present invention, it is preferable that the base oxide layer having a thickness of 10 nm to 100 nm is formed in the base oxide layer forming step.
［６］本発明の樹脂封止型半導体装置の製造方法において、前記下地酸化層形成工程においては、９５０℃～１１５０℃の範囲内の温度で下地酸化層を形成することが好ましい。
[6] In the method for manufacturing a resin-encapsulated semiconductor device of the present invention, it is preferable that the base oxide layer is formed at a temperature within a range of 950 ° C. to 1150 ° C. in the base oxide layer forming step.
［７］本発明の樹脂封止型半導体装置は、メサ領域を囲む外周テーパ領域にｐｎ接合露出部を有するメサ型半導体基体及び前記外周テーパ領域を被覆する鉛系ガラス層を有するメサ型半導体素子と、前記メサ型半導体素子を封止するモールド用樹脂とを備える樹脂封止型半導体装置であって、前記ガラス層は、前記溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、前記溝の内面を前記下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、前記鉛系ガラス組成物の溶倒点Ｔｆ以下の温度で前記ガラス組成物層を焼成する焼成工程とを実施することにより形成されたものであることを特徴とする。
[7] A resin-encapsulated semiconductor device of the present invention is a mesa semiconductor device having a mesa semiconductor substrate having a pn junction exposed portion in an outer peripheral taper region surrounding a mesa region and a lead-based glass layer covering the outer peripheral taper region. And a molding resin for sealing the mesa semiconductor element, wherein the glass layer forms a base oxide layer by oxidizing the inner surface of the groove to form a base oxide layer A glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition so as to cover an inner surface of the groove with the underlying oxide layer, and melting of the lead-based glass composition The glass composition layer is formed by performing a firing step of firing the glass composition layer at a temperature equal to or lower than the point Tf.
本発明の樹脂封止型半導体装置（及び本発明の樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）によれば、鉛系ガラス層が、溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、溝の内面を前記下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成する焼成工程とを実施することにより形成されたものであることから、後述する試験例１からも分かるように、ガラス層の電荷密度をマイナスからプラスに変えることが可能となる。その結果、高温逆バイアス試験中に外周テーパ領域の端部に向けて伸長する空乏層の伸びを抑制することが可能となり（後述する図６参照、）、後述する試験例２からも分かるように、高温逆バイアス試験中に増大するリーク電流を従来よりも低減することが可能となる。
According to the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention), the lead-based glass layer oxidizes the inner surface of the groove. A base oxide layer forming step of forming a base oxide layer, and a glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition so as to cover the inner surface of the groove via the base oxide layer, Since it is formed by carrying out a firing step of firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 described later, It becomes possible to change the charge density of the glass layer from minus to plus. As a result, it becomes possible to suppress the extension of the depletion layer extending toward the end of the outer peripheral taper region during the high temperature reverse bias test (see FIG. 6 described later), and as can be seen from Test Example 2 described later. In addition, the leakage current that increases during the high-temperature reverse bias test can be reduced as compared with the prior art.
その結果、本発明の樹脂封止型半導体装置（及び本発明の樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）は、従来の樹脂封止型半導体装置と同様にメサ型半導体素子を樹脂でモールドした構造を有するものでありながら、従来の樹脂封止型半導体装置よりも高い高温逆バイアス耐量を有する樹脂封止型半導体装置となる。すなわち、本発明の樹脂封止型半導体装置（及び本発明の樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）は、メサ型半導体素子を樹脂でモールドして製造された樹脂封止型半導体装置であって、従来の樹脂封止型半導体装置よりも高い高温逆バイアス耐量を有する樹脂封止型半導体装置となる。
As a result, the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention) is similar to the conventional resin-encapsulated semiconductor device. While having a structure in which a mesa semiconductor element is molded with resin, a resin-encapsulated semiconductor device having a higher high-temperature reverse bias tolerance than a conventional resin-encapsulated semiconductor device is obtained. That is, the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention) is manufactured by molding a mesa semiconductor element with resin. The resin-encapsulated semiconductor device is a resin-encapsulated semiconductor device having higher high-temperature reverse bias tolerance than the conventional resin-encapsulated semiconductor device.
なお、従来、鉛系ガラス層を形成した後に水素含有雰囲気でアニ－ルすることにより鉛系ガラス層の電荷密度をプラスにする技術が知られている（特許第３３１３５６６号）。しかしながら、従来の技術においては、鉛系ガラス層を形成した後に水素含有雰囲気でアニ－ルする必要があることから工程が長くなり生産性が低下する。また、水素含有雰囲気でアニールするため安全性が低く防爆仕様のアニール炉を使用する必要があり製造コストが上昇する。これに対して、本発明の樹脂封止型半導体装置（及び本発明の樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）は、このような問題がない。
Conventionally, a technique is known in which the charge density of the lead-based glass layer is increased by annealing in a hydrogen-containing atmosphere after the formation of the lead-based glass layer (Japanese Patent No. 3313566). However, in the prior art, since it is necessary to anneal in a hydrogen-containing atmosphere after forming the lead-based glass layer, the process becomes longer and the productivity is lowered. In addition, since annealing is performed in a hydrogen-containing atmosphere, it is necessary to use an annealing furnace with low safety and an explosion-proof specification, which increases manufacturing costs. On the other hand, the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention) does not have such a problem.
なお、従来の技術においては、焼成時にガラス層内に発生する気泡を抜け易くする等の目的のため、通常、鉛系ガラス組成物の溶倒点Ｔｆを超える温度でガラス組成物層を焼成することにより鉛系ガラスを形成している。
In the prior art, the glass composition layer is usually fired at a temperature exceeding the melting point Tf of the lead-based glass composition for the purpose of easily removing bubbles generated in the glass layer during firing. As a result, lead-based glass is formed.
本発明の樹脂封止型半導体装置（及び本発明の樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）の場合に、ガラス層の電荷密度をマイナスからプラスに変えることが可能となる理由についてはまだ不明である。
In the case of the resin-encapsulated semiconductor device of the present invention (and the resin-encapsulated semiconductor device manufactured by the method of manufacturing the resin-encapsulated semiconductor device of the present invention), the charge density of the glass layer is changed from minus to plus. It is still unclear why this is possible.
ここで、焼成工程において、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成することとしたのは、後述する試験例１及び図５からも分かるように、鉛系ガラス組成物の溶倒点Ｔｆを超える温度（この場合８７０℃）でガラス組成物層を焼成した場合には、ガラス層の電荷密度をマイナスからプラスに変えることができないからである。
Here, in the firing step, the glass composition layer was fired at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 and FIG. This is because when the glass composition layer is fired at a temperature exceeding the melting point Tf of the glass composition (870 ° C. in this case), the charge density of the glass layer cannot be changed from minus to plus.
樹脂封止型半導体装置の高温逆バイアス耐量を高くするには、（１）メサ型半導体素子を製造する過程で幅の広い溝（メサ溝）を形成する方法、（２）メサ型半導体素子を製造する過程で拡散ウェーハを使用し、深い溝（メサ溝）を形成する方法、（３）比抵抗の低いウェーハを使用する方法及び（４）鉛系ガラス層を厚く形成する方法も考えられる。しかしながら、上記（１）の方法においては、チップ面積が大きくなることに起因して、製品の製造コストが高くなってしまうという問題がある。また、上記（２）の方法においては、拡散ウェーハの使用で、ウェーハの価格の高騰、深い溝形成の必要性から工程が難しくなったりすることに起因して、製品の製造コストが高くなってしまうという問題がある。また、上記（３）の方法においては、耐圧を確保することが難しくなるという問題がある。また、上記（４）の方法においては、工程中にウェーハが反ったり割れやすくなったりするという問題がある。これに対して、本発明の樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置によれば、上記した問題を発生させることなく、高温逆バイアス耐量を高くすることができる。
In order to increase the high temperature reverse bias tolerance of the resin-encapsulated semiconductor device, (1) a method of forming a wide groove (mesa groove) in the process of manufacturing a mesa semiconductor element, and (2) a mesa semiconductor element A method of forming a deep groove (mesa groove) by using a diffusion wafer in the manufacturing process, (3) a method of using a wafer having a low specific resistance, and (4) a method of forming a lead-based glass layer thick are also conceivable. However, the method (1) has a problem that the manufacturing cost of the product increases due to the increase in the chip area. In the method (2), the use of a diffusion wafer increases the manufacturing cost of the product due to the fact that the process becomes difficult due to the high price of the wafer and the necessity of deep groove formation. There is a problem of end. Further, the method (3) has a problem that it is difficult to ensure a withstand voltage. The method (4) has a problem that the wafer is warped or easily broken during the process. On the other hand, according to the method for manufacturing a resin-encapsulated semiconductor device and the resin-encapsulated semiconductor device of the present invention, it is possible to increase the high temperature reverse bias tolerance without causing the above-described problems.
本発明の樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置においては、鉛系ガラス組成物として、従来から広く使用されている「珪酸鉛を主成分とするガラス組成物」を好適に用いることができる。
In the method for producing a resin-encapsulated semiconductor device and the resin-encapsulated semiconductor device of the present invention, a “glass composition mainly composed of lead silicate” that has been widely used in the past is suitable as the lead-based glass composition. Can be used.
以下、本発明の樹脂封止型半導体装置の製造方法及び樹脂封止型半導体装置について、図に示す実施の形態に基づいて説明する。
Hereinafter, a method for manufacturing a resin-encapsulated semiconductor device and a resin-encapsulated semiconductor device of the present invention will be described based on the embodiments shown in the drawings.
［実施形態］
１．樹脂封止型半導体装置
図１は、実施形態に係る樹脂封止型半導体装置１０を説明するために示す図である。図１（ａ）は樹脂封止型半導体装置１０の斜視図であり、図１（ｂ）は樹脂封止型半導体装置１０から樹脂を取り除いたものの平面図であり、図１（ｃ）は樹脂封止型半導体装置１０から樹脂を取り除いたものの側面図である。
図２は、実施形態におけるメサ型半導体素子１００を説明するために示す図である。 [Embodiment]
1. Resin Encapsulated Semiconductor Device FIG. 1 is a view for explaining a resin encapsulatedsemiconductor device 10 according to the embodiment. FIG. 1A is a perspective view of the resin-encapsulated semiconductor device 10, FIG. 1B is a plan view of the resin-encapsulated semiconductor device 10 with the resin removed, and FIG. 3 is a side view of the sealed semiconductor device 10 with a resin removed. FIG.
FIG. 2 is a view for explaining themesa semiconductor device 100 according to the embodiment.
１．樹脂封止型半導体装置
図１は、実施形態に係る樹脂封止型半導体装置１０を説明するために示す図である。図１（ａ）は樹脂封止型半導体装置１０の斜視図であり、図１（ｂ）は樹脂封止型半導体装置１０から樹脂を取り除いたものの平面図であり、図１（ｃ）は樹脂封止型半導体装置１０から樹脂を取り除いたものの側面図である。
図２は、実施形態におけるメサ型半導体素子１００を説明するために示す図である。 [Embodiment]
1. Resin Encapsulated Semiconductor Device FIG. 1 is a view for explaining a resin encapsulated
FIG. 2 is a view for explaining the
実施形態に係る樹脂封止型半導体装置１０は、図１に示すように、メサ型半導体素子１００と、メサ型半導体素子１００を封止するモールド用樹脂４０とを備える。メサ型半導体素子１００は、リード２１、リード２２及びダイパッド２３からなるリードフレーム２０におけるダイパッド２３上に載置されている。メサ型半導体素子１００の一方の電極はダイパッド２３を介してリード２１に接続されており、メサ型半導体素子１００の他方の電極は金ワイヤー３０を介してリード２２に接続されている。
As shown in FIG. 1, the resin-encapsulated semiconductor device 10 according to the embodiment includes a mesa semiconductor element 100 and a molding resin 40 that encapsulates the mesa semiconductor element 100. The mesa semiconductor element 100 is placed on the die pad 23 in the lead frame 20 including the lead 21, the lead 22, and the die pad 23. One electrode of the mesa semiconductor element 100 is connected to the lead 21 via the die pad 23, and the other electrode of the mesa semiconductor element 100 is connected to the lead 22 via the gold wire 30.
メサ型半導体素子１００は、図２に示すように、メサ領域Ａを囲む外周テーパ領域Ｂにｐｎ接合露出部Ｃを有するメサ型半導体基体１０８及び少なくとも外周テーパ領域Ｂを被覆する鉛系ガラス層１２４を有する。外周テーパ領域Ｂは、下地酸化層２１１を介して鉛系ガラス層１２４により被覆されている。鉛系ガラス層１２４は、珪酸鉛を主成分とするガラス（例えば、モル比でＳｉＯ２：７５．０％、ＰｂＯ：２０．０％、Ａｌ２Ｏ３：５．０％を含有するガラス）からなる。
As shown in FIG. 2, the mesa semiconductor element 100 includes a mesa semiconductor substrate 108 having a pn junction exposed portion C in an outer peripheral tapered region B surrounding the mesa region A and a lead-based glass layer 124 covering at least the outer peripheral tapered region B. Have The outer peripheral taper region B is covered with the lead-based glass layer 124 through the base oxide layer 211. The lead-based glass layer 124 is a glass containing lead silicate as a main component (for example, glass containing SiO 2 : 75.0%, PbO: 20.0%, Al 2 O 3 : 5.0% in a molar ratio). Consists of.
メサ型半導体基体１０８は、ｎ－型半導体層（ｎ－型シリコン基板）１１０と、ｎ－型半導体層１１０の一方の表面からのｐ型不純物の拡散により形成されたｐ＋型半導体層１１２と、ｎ－型半導体層１１０の他方の表面からのｎ型不純物の拡散により形成されたｎ＋型半導体層１１４とを有する。メサ型半導体素子１００は、ｐｎダイオードである。なお、図２中、符号１３４はアノード電極層を示し、符号１３６はカソード電極層を示す。
The mesa type semiconductor substrate 108 includes an n − type semiconductor layer (n − type silicon substrate) 110, a p + type semiconductor layer 112 formed by diffusion of p type impurities from one surface of the n − type semiconductor layer 110, and , An n + type semiconductor layer 114 formed by diffusion of an n type impurity from the other surface of the n − type semiconductor layer 110. The mesa semiconductor device 100 is a pn diode. In FIG. 2, reference numeral 134 denotes an anode electrode layer, and reference numeral 136 denotes a cathode electrode layer.
そして、実施形態に係る樹脂封止型半導体装置１０においては、鉛系ガラス層１２４は、溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、溝の内面を下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成する焼成工程とを実施することにより形成されたものである。
In the resin-encapsulated semiconductor device 10 according to the embodiment, the lead-based glass layer 124 includes a base oxide layer forming step of forming the base oxide layer by oxidizing the inner surface of the groove, and the base oxide layer on the inner surface of the groove. A glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition so as to cover the glass composition, and firing the glass composition layer at a temperature below the melting point Tf of the lead-based glass composition It is formed by performing a baking process.
２．樹脂封止型半導体装置の製造方法
実施形態に係る樹脂封止型半導体装置１０は、以下のような方法（実施形態に係る樹脂封止型半導体装置の製造方法）によって製造することができる。
図３及び図４は、実施形態に係る樹脂封止型半導体装置の製造方法を説明するために示す図である。図３（ａ）～図３（ｄ）及び図４（ａ）～図４（ｄ）は各工程図である。図５は、ガラス組成物のＤＴＡ（示差熱分析）曲線を示す図である。 2. Manufacturing Method of Resin Sealed Semiconductor Device The resin sealedsemiconductor device 10 according to the embodiment can be manufactured by the following method (the manufacturing method of the resin sealed semiconductor device according to the embodiment).
3 and 4 are views for explaining the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment. 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (d) are process diagrams. FIG. 5 is a diagram showing a DTA (differential thermal analysis) curve of the glass composition.
実施形態に係る樹脂封止型半導体装置１０は、以下のような方法（実施形態に係る樹脂封止型半導体装置の製造方法）によって製造することができる。
図３及び図４は、実施形態に係る樹脂封止型半導体装置の製造方法を説明するために示す図である。図３（ａ）～図３（ｄ）及び図４（ａ）～図４（ｄ）は各工程図である。図５は、ガラス組成物のＤＴＡ（示差熱分析）曲線を示す図である。 2. Manufacturing Method of Resin Sealed Semiconductor Device The resin sealed
3 and 4 are views for explaining the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment. 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (d) are process diagrams. FIG. 5 is a diagram showing a DTA (differential thermal analysis) curve of the glass composition.
実施形態に係る樹脂封止型半導体装置の製造方法は、図３及び図４に示すように、「半導体基板形成工程」、「溝形成工程」、「下地酸化層形成工程」、「鉛系ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」、「半導体基板切断工程」及び「樹脂封止工程」をこの順序で実施する。以下、実施形態に係る樹脂封止型半導体装置の製造方法を工程順に説明する。
As shown in FIGS. 3 and 4, the method for manufacturing a resin-encapsulated semiconductor device according to the embodiment includes a “semiconductor substrate forming step”, a “groove forming step”, a “underlying oxide layer forming step”, and “lead-based glass”. "Layer formation process", "Photoresist formation process", "Oxide film removal process", "Roughened area formation process", "Electrode formation process", "Semiconductor substrate cutting process" and "Resin sealing process" in this order To implement. Hereinafter, the manufacturing method of the resin-encapsulated semiconductor device according to the embodiment will be described in the order of steps.
（ａ）半導体基板準備工程
まず、ｎ－型半導体基板（ｎ－型シリコン基板）１１０の一方の表面からのｐ型不純物の拡散によりｐ＋型半導体層１１２、他方の表面からのｎ型不純物の拡散によりｎ＋型半導体層１１４を形成して、主面に平行なｐｎ接合が形成された半導体基板を形成する。その後、熱酸化によりｐ＋型半導体層１１２及びｎ＋型半導体層１１４の表面に酸化膜１１６，１１８を形成する。 (A) Semiconductor substrate preparation step First, p +type semiconductor layer 112 is diffused from one surface of n − type semiconductor substrate (n − type silicon substrate) 110, and n type impurities from the other surface are diffused. An n + type semiconductor layer 114 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed. Thereafter, oxide films 116 and 118 are formed on the surfaces of the p + type semiconductor layer 112 and the n + type semiconductor layer 114 by thermal oxidation.
まず、ｎ－型半導体基板（ｎ－型シリコン基板）１１０の一方の表面からのｐ型不純物の拡散によりｐ＋型半導体層１１２、他方の表面からのｎ型不純物の拡散によりｎ＋型半導体層１１４を形成して、主面に平行なｐｎ接合が形成された半導体基板を形成する。その後、熱酸化によりｐ＋型半導体層１１２及びｎ＋型半導体層１１４の表面に酸化膜１１６，１１８を形成する。 (A) Semiconductor substrate preparation step First, p +
（ｂ）溝形成工程
次に、フォトエッチング法によって、酸化膜１１６の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基板のエッチングを行い、半導体基板の一方の表面からｐｎ接合を超える深さの溝１２０を形成する（図３（ａ）参照。）。 (B) Groove Formation Step Next, a predetermined opening is formed at a predetermined portion of theoxide film 116 by a photoetching method. After the oxide film is etched, the semiconductor substrate is subsequently etched to form a groove 120 having a depth exceeding the pn junction from one surface of the semiconductor substrate (see FIG. 3A).
次に、フォトエッチング法によって、酸化膜１１６の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基板のエッチングを行い、半導体基板の一方の表面からｐｎ接合を超える深さの溝１２０を形成する（図３（ａ）参照。）。 (B) Groove Formation Step Next, a predetermined opening is formed at a predetermined portion of the
（ｃ）下地酸化層形成工程
次に、ドライ酸素（ＤｒｙＯ２）を用いた熱酸化法によって、溝１２０の内面にシリコン酸化膜からなる下地酸化層１２１を形成する（図３（ｂ）参照。）。下地酸化層１２１の厚さは、１０ｎｍ～１００ｎｍの範囲内（例えば２０ｎｍ）とする。下地酸化層１２１の形成は、半導体基体を拡散炉に入れた後、酸素ガスを流しながら９５０℃～１０５０℃の範囲内にある温度で５分～３０分処理することにより行う。下地酸化層１２１の厚さが１０ｎｍ未満であると逆方向電流低減の効果が得られなくなる場合がある。一方、下地酸化層１２１の厚さが１００ｎｍを超えると次のガラス層形成工程で電気泳動法によりガラス組成物からなる層を形成することができなくなる場合がある。 (C) Base oxide layer forming step Next, abase oxide layer 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (see FIG. 3B). ). The thickness of the base oxide layer 121 is in the range of 10 nm to 100 nm (for example, 20 nm). The formation of the base oxide layer 121 is performed by placing the semiconductor substrate in a diffusion furnace and then treating the substrate at a temperature in the range of 950 ° C. to 1050 ° C. for 5 minutes to 30 minutes while flowing oxygen gas. If the thickness of the underlying oxide layer 121 is less than 10 nm, the reverse current reduction effect may not be obtained. On the other hand, if the thickness of the base oxide layer 121 exceeds 100 nm, a layer made of a glass composition may not be formed by electrophoresis in the next glass layer forming step.
次に、ドライ酸素（ＤｒｙＯ２）を用いた熱酸化法によって、溝１２０の内面にシリコン酸化膜からなる下地酸化層１２１を形成する（図３（ｂ）参照。）。下地酸化層１２１の厚さは、１０ｎｍ～１００ｎｍの範囲内（例えば２０ｎｍ）とする。下地酸化層１２１の形成は、半導体基体を拡散炉に入れた後、酸素ガスを流しながら９５０℃～１０５０℃の範囲内にある温度で５分～３０分処理することにより行う。下地酸化層１２１の厚さが１０ｎｍ未満であると逆方向電流低減の効果が得られなくなる場合がある。一方、下地酸化層１２１の厚さが１００ｎｍを超えると次のガラス層形成工程で電気泳動法によりガラス組成物からなる層を形成することができなくなる場合がある。 (C) Base oxide layer forming step Next, a
（ｄ）ガラス層形成工程
次に、電気泳動法により溝１２０の内面及びその近傍の半導体基板表面に鉛系ガラス組成物からなるガラス組成物層を形成するとともに、当該ガラス組成物層を焼成することにより、パッシベーション用のガラス層１２４を形成する（図３（ｃ）参照。）。ガラス組成物は珪酸鉛を主成分とするガラス組成物（例えば、モル比でＳｉＯ２：７５．０％、ＰｂＯ：２０．０％、Ａｌ２Ｏ３：５．０％を含有するガラス組成物）を用いる。なお、溝１２０の内面に鉛系ガラス組成物からなる層を形成する際には、溝１２０の内面を下地酸化層１２１を介して被覆するようにガラス組成物層を形成する。従って、溝１２０の内部におけるｐｎ接合露出部は下地酸化層１２１を介して鉛系ガラス層１２４により被覆された状態となる。 (D) Glass layer formation process Next, while forming the glass composition layer which consists of a lead-type glass composition in the inner surface of the groove |channel 120 and the semiconductor substrate surface of the vicinity by electrophoresis, the said glass composition layer is baked. Thus, a glass layer 124 for passivation is formed (see FIG. 3C). The glass composition is a glass composition containing lead silicate as a main component (for example, a glass composition containing SiO 2 : 75.0%, PbO: 20.0%, Al 2 O 3 : 5.0% in molar ratio). ) Is used. When forming a layer made of a lead-based glass composition on the inner surface of the groove 120, the glass composition layer is formed so as to cover the inner surface of the groove 120 via the base oxide layer 121. Therefore, the exposed pn junction in the trench 120 is covered with the lead-based glass layer 124 via the base oxide layer 121.
次に、電気泳動法により溝１２０の内面及びその近傍の半導体基板表面に鉛系ガラス組成物からなるガラス組成物層を形成するとともに、当該ガラス組成物層を焼成することにより、パッシベーション用のガラス層１２４を形成する（図３（ｃ）参照。）。ガラス組成物は珪酸鉛を主成分とするガラス組成物（例えば、モル比でＳｉＯ２：７５．０％、ＰｂＯ：２０．０％、Ａｌ２Ｏ３：５．０％を含有するガラス組成物）を用いる。なお、溝１２０の内面に鉛系ガラス組成物からなる層を形成する際には、溝１２０の内面を下地酸化層１２１を介して被覆するようにガラス組成物層を形成する。従って、溝１２０の内部におけるｐｎ接合露出部は下地酸化層１２１を介して鉛系ガラス層１２４により被覆された状態となる。 (D) Glass layer formation process Next, while forming the glass composition layer which consists of a lead-type glass composition in the inner surface of the groove |
ガラス組成物層の焼成（焼成工程）は、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成することにより行う（図５参照。）。当該焼成工程においては、鉛系ガラス組成物の軟化点Ｔｓ以上の温度でガラス組成物層を焼成することが好ましい（図５参照。）。また、焼成工程においては、鉛系ガラス組成物のＤＴＡ曲線におけるガラス転移点Ｔｇを示す点から高温側に横軸と平行な線を引いたときに当該ＤＴＡ曲線と交わる点における所定温度Ｔｐ以上の温度でガラス組成物層を焼成することがより一層好ましい（図５参照。）。焼成工程においては、湿潤酸素ガス雰囲気でガラス組成物層を焼成することが好ましい。
Calcination of the glass composition layer (firing process) is performed by firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition (see FIG. 5). In the firing step, it is preferable to fire the glass composition layer at a temperature equal to or higher than the softening point Ts of the lead-based glass composition (see FIG. 5). Further, in the firing step, when a line parallel to the horizontal axis is drawn on the high temperature side from the point indicating the glass transition point Tg in the DTA curve of the lead-based glass composition, the temperature exceeds the predetermined temperature Tp at the point where the DTA curve intersects. It is even more preferable to fire the glass composition layer at a temperature (see FIG. 5). In the firing step, the glass composition layer is preferably fired in a wet oxygen gas atmosphere.
（ｅ）フォトレジスト形成工程
次に、ガラス層１２４の表面を覆うようにフォトレジスト１２６を形成する（図３（ｄ）参照。）。 (E) Photoresist Formation Step Next, aphotoresist 126 is formed so as to cover the surface of the glass layer 124 (see FIG. 3D).
次に、ガラス層１２４の表面を覆うようにフォトレジスト１２６を形成する（図３（ｄ）参照。）。 (E) Photoresist Formation Step Next, a
（ｆ）酸化膜除去工程
次に、フォトレジスト１２６をマスクとして酸化膜１１６のエッチングを行い、Ｎｉめっき電極膜を形成する部位１３０における酸化膜１１６を除去する（図４（ａ）参照。）。 (F) Oxide Film Removal Step Next, theoxide film 116 is etched using the photoresist 126 as a mask to remove the oxide film 116 at the site 130 where the Ni plating electrode film is to be formed (see FIG. 4A).
次に、フォトレジスト１２６をマスクとして酸化膜１１６のエッチングを行い、Ｎｉめっき電極膜を形成する部位１３０における酸化膜１１６を除去する（図４（ａ）参照。）。 (F) Oxide Film Removal Step Next, the
（ｇ）粗面化領域形成工程
次に、Ｎｉめっき電極膜を形成する部位１３０における半導体基板表面の粗面化処理を行い、Ｎｉめっき電極と半導体基板との密着性を高くするための粗面化領域１３２を形成する（図４（ｂ）参照。）。 (G) Roughened region forming step Next, a roughened surface is formed to increase the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in theportion 130 where the Ni-plated electrode film is formed. The formation region 132 is formed (see FIG. 4B).
次に、Ｎｉめっき電極膜を形成する部位１３０における半導体基板表面の粗面化処理を行い、Ｎｉめっき電極と半導体基板との密着性を高くするための粗面化領域１３２を形成する（図４（ｂ）参照。）。 (G) Roughened region forming step Next, a roughened surface is formed to increase the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the
（ｈ）電極形成工程
次に、半導体基板にＮｉめっきを行い、粗面化領域１３２上にアノード電極１３４を形成するとともに、半導体基板の他方の表面にカソード電極１３６を形成する（図４（ｃ）参照。）。各電極のアニールは、窒素雰囲気下、６００℃～８００℃の温度で行う。 (H) Electrode Formation Step Next, Ni plating is performed on the semiconductor substrate to form theanode electrode 134 on the roughened region 132, and the cathode electrode 136 is formed on the other surface of the semiconductor substrate (FIG. 4C). )reference.). Each electrode is annealed at a temperature of 600 ° C. to 800 ° C. in a nitrogen atmosphere.
次に、半導体基板にＮｉめっきを行い、粗面化領域１３２上にアノード電極１３４を形成するとともに、半導体基板の他方の表面にカソード電極１３６を形成する（図４（ｃ）参照。）。各電極のアニールは、窒素雰囲気下、６００℃～８００℃の温度で行う。 (H) Electrode Formation Step Next, Ni plating is performed on the semiconductor substrate to form the
（ｉ）半導体基板切断工程
次に、ダイシング等により、鉛系ガラス層１２４の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体素子（ｐｎダイオード）１０２を製造する（図４（ｄ）参照。）。 (I) Semiconductor Substrate Cutting Step Next, the mesa semiconductor element (pn diode) 102 is manufactured by cutting the semiconductor substrate at the center of the lead-basedglass layer 124 by dicing or the like to chip the semiconductor substrate (see FIG. 4 (d).)
次に、ダイシング等により、鉛系ガラス層１２４の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体素子（ｐｎダイオード）１０２を製造する（図４（ｄ）参照。）。 (I) Semiconductor Substrate Cutting Step Next, the mesa semiconductor element (pn diode) 102 is manufactured by cutting the semiconductor substrate at the center of the lead-based
（ｊ）樹脂封止工程
次に、図示しないリードフレーム（図１参照。）におけるダイパッド２３上にメサ型半導体素子１００を実装することによりメサ型半導体素子１００の一方の電極とリード２１とを接続するとともに、メサ型半導体素子１００の他方の電極とリード２２とを金ワイヤー３０で接続する。その後、これらを図示しない樹脂封止用金型に入れた後、モールド用樹脂を金型内に注入して硬化させることにより、樹脂封止型半導体装置を製造する。この樹脂封止型半導体装置を金型から取り出せば、実施形態に係る樹脂封止型半導体装置１０となる。 (J) Resin Sealing Step Next, themesa semiconductor element 100 is mounted on the die pad 23 in a lead frame (not shown) (see FIG. 1) to connect one electrode of the mesa semiconductor element 100 and the lead 21. At the same time, the other electrode of the mesa semiconductor element 100 and the lead 22 are connected by the gold wire 30. Then, after putting these in a resin sealing mold (not shown), a resin for molding is injected into the mold and cured to manufacture a resin sealed semiconductor device. If this resin-encapsulated semiconductor device is taken out of the mold, the resin-encapsulated semiconductor device 10 according to the embodiment is obtained.
次に、図示しないリードフレーム（図１参照。）におけるダイパッド２３上にメサ型半導体素子１００を実装することによりメサ型半導体素子１００の一方の電極とリード２１とを接続するとともに、メサ型半導体素子１００の他方の電極とリード２２とを金ワイヤー３０で接続する。その後、これらを図示しない樹脂封止用金型に入れた後、モールド用樹脂を金型内に注入して硬化させることにより、樹脂封止型半導体装置を製造する。この樹脂封止型半導体装置を金型から取り出せば、実施形態に係る樹脂封止型半導体装置１０となる。 (J) Resin Sealing Step Next, the
以上のようにして、実施形態に係る樹脂封止型半導体装置１０を製造することができる。
As described above, the resin-encapsulated semiconductor device 10 according to the embodiment can be manufactured.
３．樹脂封止型半導体装置の効果
図６は、実施形態に係る樹脂封止型半導体装置１０の効果を説明するために示す図である。図６（ａ）は実施形態に係る樹脂封止型半導体装置１０に逆方向電圧を印加したときの様子を示す図であり、図６（ｂ）は比較例に係る樹脂封止型半導体装置に逆方向電圧を印加したときの様子を示す図である。なお、図６中、破線は空乏層の先端部を示す。比較例に係る樹脂封止型半導体装置は、従来のメサ型半導体素子９００（下地酸化層無し、ガラス組成物の焼成は湿潤酸素雰囲気で８７０℃で行ったもの）を樹脂でモールドして樹脂封止型半導体装置としたものである。また、図６におけるＢＴ試験とは、高温逆バイアス試験のことである。 3. Effect of Resin-Encapsulated Semiconductor Device FIG. 6 is a diagram for explaining the effect of the resin-encapsulatedsemiconductor device 10 according to the embodiment. FIG. 6A is a diagram illustrating a state when a reverse voltage is applied to the resin-encapsulated semiconductor device 10 according to the embodiment, and FIG. 6B illustrates the resin-encapsulated semiconductor device according to the comparative example. It is a figure which shows a mode when a reverse direction voltage is applied. In FIG. 6, the broken line indicates the tip of the depletion layer. A resin-encapsulated semiconductor device according to a comparative example is obtained by molding a conventional mesa-type semiconductor element 900 (no base oxide layer, glass composition is baked at 870 ° C. in a wet oxygen atmosphere) with resin, and encapsulating the resin. This is a stationary semiconductor device. The BT test in FIG. 6 is a high temperature reverse bias test.
図６は、実施形態に係る樹脂封止型半導体装置１０の効果を説明するために示す図である。図６（ａ）は実施形態に係る樹脂封止型半導体装置１０に逆方向電圧を印加したときの様子を示す図であり、図６（ｂ）は比較例に係る樹脂封止型半導体装置に逆方向電圧を印加したときの様子を示す図である。なお、図６中、破線は空乏層の先端部を示す。比較例に係る樹脂封止型半導体装置は、従来のメサ型半導体素子９００（下地酸化層無し、ガラス組成物の焼成は湿潤酸素雰囲気で８７０℃で行ったもの）を樹脂でモールドして樹脂封止型半導体装置としたものである。また、図６におけるＢＴ試験とは、高温逆バイアス試験のことである。 3. Effect of Resin-Encapsulated Semiconductor Device FIG. 6 is a diagram for explaining the effect of the resin-encapsulated
実施形態に係る樹脂封止型半導体装置１０（及び実施形態に係る本樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）によれば、鉛系ガラス層が、溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、溝の内面を前記下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成する焼成工程とを実施することにより形成されたものであることから、後述する試験例１からも分かるように、鉛系ガラス層の電荷密度をマイナスからプラスに変えることが可能となる。その結果、高温逆バイアス試験中に外周テーパ領域の端部に向けて伸長する空乏層の伸びを抑制することが可能となり（図６参照）、後述する試験例２からも分かるように、高温逆バイアス試験中に増大するリーク電流を従来よりも低減することが可能となる。
According to the resin-encapsulated semiconductor device 10 according to the embodiment (and the resin-encapsulated semiconductor device manufactured by the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment), the lead-based glass layer has a groove A glass composition for forming a glass composition layer composed of a lead-based glass composition so as to coat a base oxide layer by oxidizing the inner surface to form a base oxide layer, and to cover the inner surface of the groove via the base oxide layer Since it is formed by implementing a layer formation process and the baking process which bakes a glass composition layer at the temperature below melting point Tf of a lead-type glass composition, from Test Example 1 mentioned later As can be seen, the charge density of the lead-based glass layer can be changed from minus to plus. As a result, it is possible to suppress the depletion layer from extending toward the end of the outer peripheral taper region during the high temperature reverse bias test (see FIG. 6). The leakage current that increases during the bias test can be reduced as compared with the conventional case.
その結果、実施形態に係る樹脂封止型半導体装置（及び実施形態に係る樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）は、従来の樹脂封止型半導体装置と同様にメサ型半導体素子を樹脂でモールドした構造を有するものでありながら、従来の樹脂封止型半導体装置よりも高い高温逆バイアス耐量を有する樹脂封止型半導体装置となる。すなわち、実施形態に係る樹脂封止型半導体装置（及び実施形態に係る樹脂封止型半導体装置の製造方法により製造される樹脂封止型半導体装置）は、メサ型半導体素子を樹脂でモールドして製造された樹脂封止型半導体装置であって、従来の樹脂封止型半導体装置よりも高い高温逆バイアス耐量を有する樹脂封止型半導体装置となる。
As a result, the resin-encapsulated semiconductor device according to the embodiment (and the resin-encapsulated semiconductor device manufactured by the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment) is a conventional resin-encapsulated semiconductor device. Similarly, a resin-encapsulated semiconductor device having a high temperature reverse bias tolerance higher than that of a conventional resin-encapsulated semiconductor device while having a structure in which a mesa-type semiconductor element is molded with resin. That is, the resin-encapsulated semiconductor device according to the embodiment (and the resin-encapsulated semiconductor device manufactured by the method for manufacturing the resin-encapsulated semiconductor device according to the embodiment) is obtained by molding a mesa semiconductor element with a resin. The manufactured resin-encapsulated semiconductor device is a resin-encapsulated semiconductor device having a high temperature reverse bias tolerance higher than that of a conventional resin-encapsulated semiconductor device.
ここで、焼成工程において、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成することとしたのは、後述する試験例１及び図５からも分かるように、鉛系ガラス組成物の溶倒点Ｔｆを超える温度でガラス組成物層を焼成した場合には、鉛系ガラス層の電荷密度をマイナスからプラスに変えることができないからである。また、焼成工程において、鉛系ガラス組成物の軟化点Ｔｓ以上の温度でガラス組成物層を焼成することとしたのは、鉛系ガラス組成物の軟化点Ｔｓ未満の温度でガラス組成物層を焼成した場合には、ガラス組成物層を十分に焼成することができず、欠陥の多いガラス層しか得られないからである。従って、珪酸鉛を主成分とするガラス組成物を用いた場合には、７６０℃～８４０℃の範囲内の温度でガラス組成物層を焼成することが好ましく、８００℃～８４０℃の範囲内の温度でガラス組成物層を焼成することがより一層好ましい。
Here, in the firing step, the glass composition layer was fired at a temperature equal to or lower than the melting point Tf of the lead-based glass composition, as can be seen from Test Example 1 and FIG. This is because when the glass composition layer is fired at a temperature exceeding the melting point Tf of the glass composition, the charge density of the lead-based glass layer cannot be changed from minus to plus. In the firing step, the glass composition layer is fired at a temperature equal to or higher than the softening point Ts of the lead-based glass composition because the glass composition layer is heated at a temperature lower than the softening point Ts of the lead-based glass composition. This is because when fired, the glass composition layer cannot be sufficiently fired, and only a glass layer having many defects can be obtained. Therefore, when a glass composition mainly composed of lead silicate is used, it is preferable to fire the glass composition layer at a temperature in the range of 760 ° C. to 840 ° C., and in the range of 800 ° C. to 840 ° C. More preferably, the glass composition layer is fired at a temperature.
また、焼成工程において、湿潤酸素ガス雰囲気でガラス組成物層を焼成することとしたのは、後述する試験例１からも分かるように、乾燥酸素ガス雰囲気でガラス組成物層を焼成した場合には、鉛系ガラス層の電荷密度をマイナスからプラスに変えることができないからである。
In the firing step, the glass composition layer is fired in a wet oxygen gas atmosphere, as can be seen from Test Example 1 described later, when the glass composition layer is fired in a dry oxygen gas atmosphere. This is because the charge density of the lead-based glass layer cannot be changed from minus to plus.
また、下地酸化層形成工程において、９５０℃～１１５０℃の範囲内の温度で下地酸化層を形成することとしたのは、９５０℃未満の温度でガラス組成物層を焼成した場合には、鉛系ガラス層の電荷密度をマイナスからプラスに変えることができないからである。一方、１０５０℃を超える温度でガラス組成物層を焼成した場合には、半導体素子の電気的特性に影響を与える可能性が出てくるからである。
In the base oxide layer forming step, the base oxide layer is formed at a temperature within the range of 950 ° C. to 1150 ° C. when the glass composition layer is fired at a temperature of less than 950 ° C. This is because the charge density of the system glass layer cannot be changed from minus to plus. On the other hand, when the glass composition layer is baked at a temperature exceeding 1050 ° C., the electrical characteristics of the semiconductor element may be affected.
［試験例１］
１．試料の調整
図７は、試験例１の条件及び結果を示す図表である。
以下のようにして２４個の試料を作製した。このうち２０個の試料（試料２－６，８－１２，１４－１８，２０－２４）については、所定の温度条件（８５０℃～１０５０℃）の下、ｎ－型シリコン基板の一方の表面を酸化して所定厚さ（２０ｎｍ要確認）の下地酸化層を形成し、その後、電気泳動法により所定厚さ（２０μｍ～３０μｍ）のガラス組成物層を形成し、その後、所定の温度条件（８２０℃又は８７０℃）及び所定の雰囲気条件（圧力：常圧、流量：３～９Ｌ／分、雰囲気：乾燥純酸素条件又は湿潤純酸素条件）の下、1５分間、ガラス組成物層を焼成した。また、残りの４個の試料（試料１，７，１３，１９）については、ｎ－型シリコン基板の一方の表面に、下地酸化層を形成することなく所定厚さのガラス組成物層を形成し、その後、所定の温度条件（８２０℃又は８７０℃）及び所定の雰囲気条件（圧力：常圧、流量：３～９Ｌ／分、雰囲気：乾燥純酸素条件又は湿潤純酸素条件）の下、１５分間、ガラス組成物層を焼成した。その後、ｎ－型シリコン基板の他方の表面及びガラス層の表面に白金電極を形成した。 [Test Example 1]
1. Preparation of Sample FIG. 7 is a chart showing the conditions and results of Test Example 1.
Twenty-four samples were produced as follows. Of these 20 samples (Samples 2-6, 8-12, 14-18, 20-24), one surface of the n − -type silicon substrate under a predetermined temperature condition (850 ° C. to 1050 ° C.) Is oxidized to form a base oxide layer having a predetermined thickness (requires confirmation of 20 nm), and thereafter a glass composition layer having a predetermined thickness (20 μm to 30 μm) is formed by electrophoresis, followed by a predetermined temperature condition ( 820 ° C. or 870 ° C.) and a predetermined atmospheric condition (pressure: normal pressure, flow rate: 3 to 9 L / min, atmosphere: dry pure oxygen condition or wet pure oxygen condition), and the glass composition layer was baked for 15 minutes. . For the remaining four samples (samples 1, 7, 13, and 19), a glass composition layer having a predetermined thickness was formed on one surface of the n − -type silicon substrate without forming a base oxide layer. Then, under a predetermined temperature condition (820 ° C. or 870 ° C.) and a predetermined atmosphere condition (pressure: normal pressure, flow rate: 3 to 9 L / min, atmosphere: dry pure oxygen condition or wet pure oxygen condition), 15 The glass composition layer was baked for a minute. Thereafter, platinum electrodes were formed on the other surface of the n − -type silicon substrate and the surface of the glass layer.
１．試料の調整
図７は、試験例１の条件及び結果を示す図表である。
以下のようにして２４個の試料を作製した。このうち２０個の試料（試料２－６，８－１２，１４－１８，２０－２４）については、所定の温度条件（８５０℃～１０５０℃）の下、ｎ－型シリコン基板の一方の表面を酸化して所定厚さ（２０ｎｍ要確認）の下地酸化層を形成し、その後、電気泳動法により所定厚さ（２０μｍ～３０μｍ）のガラス組成物層を形成し、その後、所定の温度条件（８２０℃又は８７０℃）及び所定の雰囲気条件（圧力：常圧、流量：３～９Ｌ／分、雰囲気：乾燥純酸素条件又は湿潤純酸素条件）の下、1５分間、ガラス組成物層を焼成した。また、残りの４個の試料（試料１，７，１３，１９）については、ｎ－型シリコン基板の一方の表面に、下地酸化層を形成することなく所定厚さのガラス組成物層を形成し、その後、所定の温度条件（８２０℃又は８７０℃）及び所定の雰囲気条件（圧力：常圧、流量：３～９Ｌ／分、雰囲気：乾燥純酸素条件又は湿潤純酸素条件）の下、１５分間、ガラス組成物層を焼成した。その後、ｎ－型シリコン基板の他方の表面及びガラス層の表面に白金電極を形成した。 [Test Example 1]
1. Preparation of Sample FIG. 7 is a chart showing the conditions and results of Test Example 1.
Twenty-four samples were produced as follows. Of these 20 samples (Samples 2-6, 8-12, 14-18, 20-24), one surface of the n − -type silicon substrate under a predetermined temperature condition (850 ° C. to 1050 ° C.) Is oxidized to form a base oxide layer having a predetermined thickness (requires confirmation of 20 nm), and thereafter a glass composition layer having a predetermined thickness (20 μm to 30 μm) is formed by electrophoresis, followed by a predetermined temperature condition ( 820 ° C. or 870 ° C.) and a predetermined atmospheric condition (pressure: normal pressure, flow rate: 3 to 9 L / min, atmosphere: dry pure oxygen condition or wet pure oxygen condition), and the glass composition layer was baked for 15 minutes. . For the remaining four samples (
なお、試料２，８，１４，２０は、８５０℃で下地酸化層を形成し、試料３，９，１５，２１は、９００℃で下地酸化層を形成し、試料４，１０，１６，２２は、９５０℃で下地酸化層を形成し、試料５，１１，１７，２３は、１０００℃で下地酸化層を形成し、試料６，１２，１８，２４は、１０５０℃で下地酸化層を形成した。
Samples 2, 8, 14, and 20 form a base oxide layer at 850 ° C., Samples 3, 9, 15, and 21 form a base oxide layer at 900 ° C., and Samples 4, 10, 16, and 22 Forms a base oxide layer at 950 ° C., samples 5, 11, 17, and 23 form a base oxide layer at 1000 ° C., and samples 6, 12, 18, and 24 form a base oxide layer at 1050 ° C. did.
また、試料１～１２は、乾燥酸素雰囲気でガラス組成物層を焼成し、試料１３～２４は、湿潤酸素ガス雰囲気でガラス組成物層を焼成した。また、試料１～６，１３～１８は、８２０℃でガラス組成物層を焼成し、試料７～１２，１９～２４は、８７０℃でガラス組成物層を焼結した。
Samples 1 to 12 fired the glass composition layer in a dry oxygen atmosphere, and samples 13 to 24 fired the glass composition layer in a wet oxygen gas atmosphere. In Samples 1 to 6, 13 to 18, the glass composition layer was fired at 820 ° C., and in Samples 7 to 12 and 19 to 24, the glass composition layer was sintered at 870 ° C.
２．電荷密度Ｎｓｓの測定
電荷密度Ｎｓｓの測定は、上記１．で作製した各試料におけるｎ－型シリコン基板の他方の表面に形成した白金電極及びガラス層の表面に形成した白金電極との間に印加する電圧を走査することにより作成したＣＶ曲線から電荷密度Ｎｓｓを算出することにより行った。 2. Measurement of Charge Density Nss The measurement of the charge density Nss is as described in 1. above. The charge density Nss from the CV curve created by scanning the voltage applied between the platinum electrode formed on the other surface of the n − -type silicon substrate and the platinum electrode formed on the surface of the glass layer in each sample prepared inStep 1. This was done by calculating
電荷密度Ｎｓｓの測定は、上記１．で作製した各試料におけるｎ－型シリコン基板の他方の表面に形成した白金電極及びガラス層の表面に形成した白金電極との間に印加する電圧を走査することにより作成したＣＶ曲線から電荷密度Ｎｓｓを算出することにより行った。 2. Measurement of Charge Density Nss The measurement of the charge density Nss is as described in 1. above. The charge density Nss from the CV curve created by scanning the voltage applied between the platinum electrode formed on the other surface of the n − -type silicon substrate and the platinum electrode formed on the surface of the glass layer in each sample prepared in
３．結果
試験例１の結果、図７に示すように、（ａ）下地酸化層を介してガラス層を形成し、かつ、（ｂ）９５０℃～１０５０℃の範囲内の温度で下地酸化層を形成し、かつ、（ｃ）湿潤酸素雰囲気でガラス組成物層を焼成し、かつ、（ｄ）８２０℃でガラス組成物層を焼成した場合に、電荷密度Ｎｓｓがプラスの値を採るようになることが分かった。 3. Results As a result of Test Example 1, as shown in FIG. 7, (a) a glass layer is formed through the base oxide layer, and (b) a base oxide layer is formed at a temperature in the range of 950 ° C. to 1050 ° C. And (c) when the glass composition layer is fired in a wet oxygen atmosphere and (d) the glass composition layer is fired at 820 ° C., the charge density Nss becomes a positive value. I understood.
試験例１の結果、図７に示すように、（ａ）下地酸化層を介してガラス層を形成し、かつ、（ｂ）９５０℃～１０５０℃の範囲内の温度で下地酸化層を形成し、かつ、（ｃ）湿潤酸素雰囲気でガラス組成物層を焼成し、かつ、（ｄ）８２０℃でガラス組成物層を焼成した場合に、電荷密度Ｎｓｓがプラスの値を採るようになることが分かった。 3. Results As a result of Test Example 1, as shown in FIG. 7, (a) a glass layer is formed through the base oxide layer, and (b) a base oxide layer is formed at a temperature in the range of 950 ° C. to 1050 ° C. And (c) when the glass composition layer is fired in a wet oxygen atmosphere and (d) the glass composition layer is fired at 820 ° C., the charge density Nss becomes a positive value. I understood.
なお、その後の実験により、８４０℃でガラス組成物層の焼成を行った場合にも、電荷密度Ｎｓｓがプラスの値を採るようになることが分かった。さらに、その後の実験により、溶倒点Ｔｆ以下の温度でガラス組成物層の焼成を行った場合には、電荷密度Ｎｓｓがプラスの値を採るようになることが分かった。また、その後の実験により、軟化点Ｔｓ以上の温度（好ましくは、ガラス組成物のＤＴＡ曲線におけるガラス転移点Ｔｇを示す点から高温側に横軸と平行な線を引いたときに当該ＤＴＡ曲線と交わる点における所定温度Ｔｐ以上の温度）でガラス組成物層の焼成を行った場合には、比較的短い時間（例えば３０分間以下）でガラス組成物層の焼成を完了させることができることが分かった。
In addition, it was found by subsequent experiments that the charge density Nss takes a positive value even when the glass composition layer is fired at 840 ° C. Furthermore, it has been found by subsequent experiments that when the glass composition layer is fired at a temperature equal to or lower than the melting point Tf, the charge density Nss takes a positive value. Further, in a subsequent experiment, a temperature equal to or higher than the softening point Ts (preferably, when a line parallel to the horizontal axis is drawn on the high temperature side from a point indicating the glass transition point Tg in the DTA curve of the glass composition, It has been found that when the glass composition layer is baked at a temperature that is equal to or higher than a predetermined temperature Tp at the intersecting point, the baking of the glass composition layer can be completed in a relatively short time (for example, 30 minutes or less). .
［試験例２］
実施形態に係る樹脂封止型半導体装置の製造方法と同様の方法によって樹脂封止型半導体装置（耐圧６００Ｖ）を作製し試料とした。但し、１０００℃の温度で下地酸化層の形成を行い、８２０℃の温度及び湿潤酸素雰囲気の条件でガラス組成物層の焼成を行ったものを試料２５（実施例）とした。また、下地酸化層を形成することなく、８７０℃の温度、湿潤酸素雰囲気の条件でガラス組成物層の焼成を行ったものを試料２６（比較例）とした。 [Test Example 2]
A resin-encapsulated semiconductor device (withstand voltage of 600 V) was fabricated and used as a sample by the same method as the method for producing the resin-encapsulated semiconductor device according to the embodiment. However, Sample 25 (Example) was obtained by forming the base oxide layer at a temperature of 1000 ° C. and firing the glass composition layer at a temperature of 820 ° C. and a wet oxygen atmosphere. Further, Sample 26 (Comparative Example) was obtained by firing the glass composition layer under the conditions of a temperature of 870 ° C. and a wet oxygen atmosphere without forming a base oxide layer.
実施形態に係る樹脂封止型半導体装置の製造方法と同様の方法によって樹脂封止型半導体装置（耐圧６００Ｖ）を作製し試料とした。但し、１０００℃の温度で下地酸化層の形成を行い、８２０℃の温度及び湿潤酸素雰囲気の条件でガラス組成物層の焼成を行ったものを試料２５（実施例）とした。また、下地酸化層を形成することなく、８７０℃の温度、湿潤酸素雰囲気の条件でガラス組成物層の焼成を行ったものを試料２６（比較例）とした。 [Test Example 2]
A resin-encapsulated semiconductor device (withstand voltage of 600 V) was fabricated and used as a sample by the same method as the method for producing the resin-encapsulated semiconductor device according to the embodiment. However, Sample 25 (Example) was obtained by forming the base oxide layer at a temperature of 1000 ° C. and firing the glass composition layer at a temperature of 820 ° C. and a wet oxygen atmosphere. Further, Sample 26 (Comparative Example) was obtained by firing the glass composition layer under the conditions of a temperature of 870 ° C. and a wet oxygen atmosphere without forming a base oxide layer.
その後、作製した樹脂封止型半導体装置（試料２５，２６）について高温逆バイアス試験を行い、高温逆バイアス耐量を測定した。高温逆バイアス耐量は、温度１５０℃に条件設定された恒温槽・高温逆バイアス試験機に各試料を投入して、アノード電極・カソード電極間に４８０Ｖ（耐圧の８０％）の電圧を印加した状態で１０００時間にわたって１０分毎に逆方向電流を測定することにより行った。
Thereafter, the manufactured resin-encapsulated semiconductor device (samples 25 and 26) was subjected to a high temperature reverse bias test, and the high temperature reverse bias tolerance was measured. The high temperature reverse bias tolerance is a state in which each sample is put into a constant temperature bath / high temperature reverse bias tester set at a temperature of 150 ° C., and a voltage of 480 V (80% of the withstand voltage) is applied between the anode electrode and the cathode electrode. The reverse current was measured every 10 minutes for 1000 hours.
図８は、試験例２における高温逆バイアス試験の結果を示す図である。図８中、実線は試料２５（実施例）についての逆方向電流を示し、破線は試料２６（比較例）についての逆方向電流を示す。
その結果、図８に示すように、試料２６においては、高温逆バイアス試験開始直後に温度上昇に伴ってリーク電流（逆方向電流）が増大した後もリーク電流（逆方向電流）が増大し続けることが分かった。そして、１００時間経過後のリーク電流（逆方向電流）は初期のリーク電流（逆方向電流）の１０倍程度にまで増大することが確認できた。これに対して、試料２５については、高温逆バイアス試験開始直後に温度上昇に伴ってリーク電流（逆方向電流）が増大した後はリーク電流（逆方向電流）がほとんど増大しないことが分かった。１０００時間経過後のリーク電流（逆方向電流）は初期のリーク電流（逆方向電流）の２倍程度に収まっていることが確認できた。 FIG. 8 is a diagram showing the results of the high-temperature reverse bias test in Test Example 2. In FIG. 8, the solid line indicates the reverse current for the sample 25 (Example), and the broken line indicates the reverse current for the sample 26 (Comparative Example).
As a result, as shown in FIG. 8, in the sample 26, the leak current (reverse current) continues to increase even after the leak current (reverse current) increases as the temperature rises immediately after the start of the high temperature reverse bias test. I understood that. It was confirmed that the leak current (reverse current) after 100 hours increased to about 10 times the initial leak current (reverse current). On the other hand, for sample 25, it was found that the leak current (reverse current) hardly increased after the leak current (reverse current) increased as the temperature increased immediately after the start of the high temperature reverse bias test. It was confirmed that the leakage current (reverse current) after 1000 hours was about twice the initial leakage current (reverse current).
その結果、図８に示すように、試料２６においては、高温逆バイアス試験開始直後に温度上昇に伴ってリーク電流（逆方向電流）が増大した後もリーク電流（逆方向電流）が増大し続けることが分かった。そして、１００時間経過後のリーク電流（逆方向電流）は初期のリーク電流（逆方向電流）の１０倍程度にまで増大することが確認できた。これに対して、試料２５については、高温逆バイアス試験開始直後に温度上昇に伴ってリーク電流（逆方向電流）が増大した後はリーク電流（逆方向電流）がほとんど増大しないことが分かった。１０００時間経過後のリーク電流（逆方向電流）は初期のリーク電流（逆方向電流）の２倍程度に収まっていることが確認できた。 FIG. 8 is a diagram showing the results of the high-temperature reverse bias test in Test Example 2. In FIG. 8, the solid line indicates the reverse current for the sample 25 (Example), and the broken line indicates the reverse current for the sample 26 (Comparative Example).
As a result, as shown in FIG. 8, in the sample 26, the leak current (reverse current) continues to increase even after the leak current (reverse current) increases as the temperature rises immediately after the start of the high temperature reverse bias test. I understood that. It was confirmed that the leak current (reverse current) after 100 hours increased to about 10 times the initial leak current (reverse current). On the other hand, for sample 25, it was found that the leak current (reverse current) hardly increased after the leak current (reverse current) increased as the temperature increased immediately after the start of the high temperature reverse bias test. It was confirmed that the leakage current (reverse current) after 1000 hours was about twice the initial leakage current (reverse current).
以上、本発明の樹脂封止型半導体装置及び樹脂封止型半導体装置の製造方法を上記の実施形態に基づいて説明したが、本発明はこれに限定されるものではなく、その要旨を逸脱しない範囲において実施することが可能であり、例えば次のような変形も可能である。
As described above, the resin-encapsulated semiconductor device and the method for producing the resin-encapsulated semiconductor device of the present invention have been described based on the above embodiment, but the present invention is not limited to this and does not depart from the gist thereof. For example, the following modifications are possible.
（１）上記の実施形態においては、ドライ酸素（ＤｒｙＯ２）を用いた熱酸化法によって下地酸化層を形成したが、本発明はこれに限定されるものではない。例えば、ドライ酸素及び窒素（ＤｒｙＯ２＋Ｎ２）を用いた熱酸化法によって絶縁層を形成してもよいし、ウェット酸素（ＷｅｔＯ２）を用いた熱酸化法によって絶縁層を形成してもよいし、ウェット酸素及び窒素（ＷｅｔＯ２＋Ｎ２）を用いた熱酸化法によって絶縁層を形成してもよい。
(1) In the above embodiment, the base oxide layer is formed by the thermal oxidation method using dry oxygen (DryO 2 ), but the present invention is not limited to this. For example, the insulating layer may be formed by a thermal oxidation method using dry oxygen and nitrogen (DryO 2 + N 2 ), or may be formed by a thermal oxidation method using wet oxygen (WetO 2 ). Then, the insulating layer may be formed by a thermal oxidation method using wet oxygen and nitrogen (WetO 2 + N 2 ).
（２）上記の実施形態においては、ダイオード（ｐｎダイオード）からなるメサ型半導体素子を用いたが、本発明はこれに限定されるものではない。例えば、サイリスターからなるメサ型半導体素子を用いてもよい。また、サイリスターからなるメサ型半導体素子のほか、ｐｎ接合が露出する半導体装置全般（例えば、パワーＭＯＳＦＥＴ、ＩＧＢＴなど。）に本発明を適用することもできる。
(2) In the above embodiment, the mesa type semiconductor element composed of a diode (pn diode) is used. However, the present invention is not limited to this. For example, a mesa semiconductor element made of thyristor may be used. In addition to mesa type semiconductor elements made of thyristors, the present invention can be applied to all semiconductor devices (for example, power MOSFET, IGBT, etc.) in which a pn junction is exposed.
図９は、変形例におけるメサ型半導体素子２００を説明するために示す図である。
変形例に係る樹脂封止型半導体装置１４（図示せず。）は、基本的には実施形態に係る樹脂封止型半導体装置１０と同様の構成を有するが、サイリスターからなるメサ型半導体素子を用いる点が実施形態に係る樹脂封止型半導体装置１０の場合とは異なる。 FIG. 9 is a diagram for explaining amesa semiconductor device 200 according to a modification.
A resin-encapsulated semiconductor device 14 (not shown) according to the modification basically has the same configuration as the resin-encapsulatedsemiconductor device 10 according to the embodiment, but a mesa-type semiconductor element made of a thyristor is used. The point of using is different from the case of the resin-encapsulated semiconductor device 10 according to the embodiment.
変形例に係る樹脂封止型半導体装置１４（図示せず。）は、基本的には実施形態に係る樹脂封止型半導体装置１０と同様の構成を有するが、サイリスターからなるメサ型半導体素子を用いる点が実施形態に係る樹脂封止型半導体装置１０の場合とは異なる。 FIG. 9 is a diagram for explaining a
A resin-encapsulated semiconductor device 14 (not shown) according to the modification basically has the same configuration as the resin-encapsulated
すなわち、変形例に係る樹脂封止型半導体装置１４は、メサ領域を囲む外周テーパ領域にｐｎ接合露出部を有するメサ型半導体基体及び少なくとも外周テーパ領域を被覆する鉛系ガラス層２２４を有するメサ型半導体素子２００と、メサ型半導体素子２００を封止するモールド用樹脂とを備える樹脂封止型半導体装置であって、鉛系ガラス層２２４は、溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、溝の内面を下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成する焼成工程とを実施することにより形成されたものである。
That is, the resin-encapsulated semiconductor device 14 according to the modified example has a mesa type having a mesa type semiconductor substrate having a pn junction exposed portion in an outer peripheral tapered region surrounding the mesa region and a lead-based glass layer 224 covering at least the outer peripheral tapered region. In the resin-encapsulated semiconductor device including the semiconductor element 200 and a molding resin for encapsulating the mesa-type semiconductor element 200, the lead-based glass layer 224 oxidizes the inner surface of the groove to form a base oxide layer. A base oxide layer forming step, a glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition so as to cover the inner surface of the groove via the base oxide layer, and a solution of the lead-based glass composition It is formed by carrying out a firing step of firing the glass composition layer at a temperature equal to or lower than the inversion point Tf.
変形例におけるメサ型半導体素子２００は、サイリスターであって、図８に示すように、ｎ－型半導体層２１０と、ｎ－型半導体層２１０に接して配置された第１のｐ＋型半導体層２１２と、ｎ－型半導体層２１０に接して配置された第２のｐ＋型半導体層２１４と、第２のｐ＋型半導体層２１４の表面に形成されたｎ＋型半導体領域２１６と、第１のｐ＋型半導体層２１２に接続されたアノード電極２３４と、ｎ＋型半導体領域２１６に接続されたカソード電極２３６と、第２のｐ＋型半導体層２１４に接続されたゲート電極２３８とを備える。
The mesa semiconductor element 200 in the modification is a thyristor, and as shown in FIG. 8, an n − type semiconductor layer 210 and a first p + type semiconductor layer disposed in contact with the n − type semiconductor layer 210. 212, a second p + type semiconductor layer 214 disposed in contact with the n − type semiconductor layer 210, an n + type semiconductor region 216 formed on the surface of the second p + type semiconductor layer 214, An anode electrode 234 connected to one p + type semiconductor layer 212, a cathode electrode 236 connected to an n + type semiconductor region 216, and a gate electrode 238 connected to the second p + type semiconductor layer 214. Prepare.
このように、変形例に係る樹脂封止型半導体装置１４は、サイリスターからなるメサ型半導体素子を用いる点が実施形態に係る樹脂封止型半導体装置１０の場合とは異なるが、実施形態に係る樹脂封止型半導体装置１０の場合と同様に、鉛系ガラス層が、溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、溝の内面を下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、鉛系ガラス組成物の溶倒点Ｔｆ以下の温度でガラス組成物層を焼成する焼成工程とを実施することにより形成されたものであることから、従来の樹脂封止型半導体装置と同様にメサ型半導体素子を樹脂でモールドした構造を有するものでありながら、実施形態に係る樹脂封止型半導体装置１０の場合と同様に、従来の樹脂封止型半導体装置よりも高い高温逆バイアス耐量を有する樹脂封止型半導体装置となる。すなわち、変形例に係る樹脂封止型半導体装置１４は、メサ型半導体素子を樹脂でモールドして製造された樹脂封止型半導体装置であって、従来の樹脂封止型半導体装置よりも高い高温逆バイアス耐量を有する樹脂封止型半導体装置となる。
As described above, the resin-encapsulated semiconductor device 14 according to the modification is different from the resin-encapsulated semiconductor device 10 according to the embodiment in that the mesa-type semiconductor element made of thyristor is used. As in the case of the resin-encapsulated semiconductor device 10, the lead-based glass layer coats the inner surface of the groove with the base oxide layer by oxidizing the inner surface of the groove to form the base oxide layer. A glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition, and a firing step of firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition. The resin-encapsulated semiconductor according to the embodiment has a structure in which a mesa-type semiconductor element is molded with resin in the same manner as a conventional resin-encapsulated semiconductor device because it is formed by implementation. Device 1 As in the case of, the resin-sealed-type semiconductor device having a high high-temperature reverse bias capability than conventional resin-sealed semiconductor device. That is, the resin-encapsulated semiconductor device 14 according to the modification is a resin-encapsulated semiconductor device manufactured by molding a mesa-type semiconductor element with resin and has a higher temperature than that of a conventional resin-encapsulated semiconductor device. A resin-encapsulated semiconductor device having a reverse bias tolerance is obtained.
（３）上記の実施形態においては、珪酸鉛を主成分とするガラス組成物を用いてガラス層を形成したが、本発明はこれに限定されるものではない。例えば、鉛を実質的に含有しないガラス組成物を用いてガラス層を形成してもよい。
(3) In the above embodiment, the glass layer is formed using the glass composition containing lead silicate as a main component, but the present invention is not limited to this. For example, you may form a glass layer using the glass composition which does not contain lead substantially.
１０…樹脂封止型半導体装置、２０…リードフレーム、２１，２２…リード、２３…ダイパッド、３０…金ワイヤー、４０…樹脂、１００，２００…メサ型半導体素子、１１０，９１０…ｎ－型半導体層、１１２，９１２…ｐ＋型半導体層、１１４，９１４…ｎ－型半導体層、１１６，１１８，９１６，９１８…酸化膜、１２０，９２０…溝、１２１，２２１…下地酸化層、１２４，９２４…ガラス層、１２６，９２６…フォトレジスト、１３０，９３０…Ｎｉめっき電極膜を形成する部位、１３２，９３２…粗面化領域、１３４，２３４，９３４，２３４…アノード電極、１３６，２３６，９３６…カソード電極、２１０…ｎ－型半導体層、２１２…第１のｐ＋型半導体層２１２、２１４…第２のｐ＋型半導体層、２１６…ｎ＋型半導体領域、２３８…ゲート電極層
DESCRIPTION OF SYMBOLS 10 ... Resin sealing type semiconductor device, 20 ... Lead frame, 21, 22 ... Lead, 23 ... Die pad, 30 ... Gold wire, 40 ... Resin, 100, 200 ... Mesa type semiconductor element, 110, 910 ... n < - > type semiconductor Layer 112,912 ... p + type semiconductor layer 114,914 ... n - type semiconductor layer 116,118,916,918 ... oxide film 120,920 ... groove 121,221 ... underlying oxide layer 124,924 ... Glass layer, 126,926 ... Photoresist, 130,930 ... Ni plating electrode film forming part, 132,932 ... Roughened region, 134,234,934,234 ... Anode electrode, 136,236,936 ... cathode electrode, 210 ... n - -type semiconductor layer, 212 ... first p + - type semiconductor layer 212, 214 ... second p + -type semiconductor layer, 216 ... n + -type semiconductive Body region, 238... Gate electrode layer
Claims (7)
- 主面に平行なｐｎ接合を備える半導体基板を準備する半導体基板準備工程と、
前記半導体基板の一方の表面から前記ｐｎ接合を超える深さの溝を形成する溝形成工程と、
前記溝の内面を被覆するように鉛系ガラス層を形成するガラス層形成工程と、
前記溝に沿って前記半導体基板を切断することにより、メサ型半導体素子を作製する半導体基板切断工程と、
前記メサ型半導体素子をモールド用樹脂で封止する樹脂封止工程とをこの順序で含む樹脂封止型半導体装置の製造方法であって、
前記ガラス層形成工程は、
前記溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、
前記溝の内面を前記下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、
前記鉛系ガラス組成物の溶倒点Ｔｆ以下の温度で前記ガラス組成物層を焼成する焼成工程とを含むことを特徴とする樹脂封止型半導体装置の製造方法。 A semiconductor substrate preparation step of preparing a semiconductor substrate having a pn junction parallel to the main surface;
Forming a groove having a depth exceeding the pn junction from one surface of the semiconductor substrate;
A glass layer forming step of forming a lead-based glass layer so as to cover the inner surface of the groove;
A semiconductor substrate cutting step for producing a mesa semiconductor element by cutting the semiconductor substrate along the groove;
And a resin sealing step of sealing the mesa semiconductor element with a molding resin in this order,
The glass layer forming step includes
A base oxide layer forming step of oxidizing the inner surface of the groove to form a base oxide layer;
A glass composition layer forming step of forming a glass composition layer made of a lead-based glass composition so as to cover the inner surface of the groove via the base oxide layer;
And a firing step of firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition. - 前記焼成工程においては、前記鉛系ガラス組成物の軟化点Ｔｓ以上の温度で前記ガラス組成物層を焼成することを特徴とする請求項１に記載の樹脂封止型半導体装置の製造方法。 The method for manufacturing a resin-encapsulated semiconductor device according to claim 1, wherein, in the baking step, the glass composition layer is fired at a temperature equal to or higher than a softening point Ts of the lead-based glass composition.
- 前記焼成工程においては、前記鉛系ガラス組成物のＤＴＡ曲線におけるガラス転移点Ｔｇを示す点から高温側に横軸と平行な線を引いたときに当該ＤＴＡ曲線と交わる点における所定温度Ｔｐ以上の温度で前記ガラス組成物層を焼成することを特徴とする請求項２に記載の樹脂封止型半導体装置の製造方法。 In the firing step, when a line parallel to the horizontal axis is drawn on the high temperature side from the point showing the glass transition point Tg in the DTA curve of the lead-based glass composition, the temperature exceeds a predetermined temperature Tp at the point where the DTA curve intersects. The method for producing a resin-encapsulated semiconductor device according to claim 2, wherein the glass composition layer is baked at a temperature.
- 前記焼成工程においては、湿潤酸素ガス雰囲気で前記ガラス組成物層を焼成することを特徴とする請求項１～３のいずれかに記載の樹脂封止型半導体装置の製造方法。 The method for manufacturing a resin-encapsulated semiconductor device according to any one of claims 1 to 3, wherein, in the baking step, the glass composition layer is fired in a wet oxygen gas atmosphere.
- 前記下地酸化層形成工程においては、１０ｎｍ～１００ｎｍの厚さの前記下地酸化層を形成することを特徴とする請求項１～４のいずれかに記載の樹脂封止型半導体装置の製造方法。 5. The method for manufacturing a resin-encapsulated semiconductor device according to claim 1, wherein in the base oxide layer forming step, the base oxide layer having a thickness of 10 nm to 100 nm is formed.
- 前記下地酸化層形成工程においては、９５０℃～１１５０℃の範囲内の温度で下地酸化層を形成することを特徴とする請求項１～５のいずれかに記載の樹脂封止型半導体装置の製造方法。 6. The resin-encapsulated semiconductor device according to claim 1, wherein in the base oxide layer forming step, the base oxide layer is formed at a temperature within a range of 950 ° C. to 1150 ° C. Method.
- メサ領域を囲む外周テーパ領域にｐｎ接合露出部を有するメサ型半導体基体及び前記外周テーパ領域を被覆する鉛系ガラス層を有するメサ型半導体素子と、
前記メサ型半導体素子を封止するモールド用樹脂とを備える樹脂封止型半導体装置であって、
前記鉛系ガラス層は、前記溝の内面を酸化して下地酸化層を形成する下地酸化層形成工程と、前記溝の内面を前記下地酸化層を介して被覆するように鉛系ガラス組成物からなるガラス組成物層を形成するガラス組成物層形成工程と、前記鉛系ガラス組成物の溶倒点Ｔｆ以下の温度で前記ガラス組成物層を焼成する焼成工程とを実施することにより形成されたものであることを特徴とする樹脂封止型半導体装置。 A mesa semiconductor substrate having a pn junction exposed portion in an outer peripheral taper region surrounding the mesa region, and a mesa semiconductor element having a lead-based glass layer covering the outer peripheral taper region;
A resin-encapsulated semiconductor device comprising a molding resin that encapsulates the mesa semiconductor element,
The lead-based glass layer is formed from a lead-based glass composition so as to oxidize the inner surface of the groove to form a base oxide layer, and to cover the inner surface of the groove via the base oxide layer. Formed by performing a glass composition layer forming step for forming the glass composition layer and a firing step for firing the glass composition layer at a temperature equal to or lower than the melting point Tf of the lead-based glass composition. What is claimed is: 1. A resin-encapsulated semiconductor device, comprising:
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| CN104599963B (en) * | 2015-01-15 | 2017-12-19 | 苏州启澜功率电子有限公司 | A kind of table top chip double-side electrophoresis glass passivation process |
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| CN112444717A (en) * | 2019-08-29 | 2021-03-05 | 珠海格力电器股份有限公司 | Verification method for matching degree of plastic package material and chip |
| CN112103197B (en) * | 2020-11-09 | 2021-02-09 | 浙江里阳半导体有限公司 | Method for manufacturing semiconductor discrete device and passivation device thereof |
| CN114171416B (en) * | 2022-02-14 | 2022-06-03 | 浙江里阳半导体有限公司 | TVS chip and glass passivation method and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09246571A (en) * | 1996-03-13 | 1997-09-19 | Hitachi Ltd | Manufacture of diode |
| JPH10125628A (en) * | 1996-10-24 | 1998-05-15 | Hitachi Ltd | Electrode-forming method of glass-coated semiconductor device |
| JPH10294473A (en) * | 1997-04-17 | 1998-11-04 | Hitachi Ltd | Surface-mount type semiconductor device and manufacture thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02163938A (en) * | 1988-12-16 | 1990-06-25 | Fuji Electric Co Ltd | Manufacture of semiconductor element |
| JP3542677B2 (en) * | 1995-02-27 | 2004-07-14 | セイコーエプソン株式会社 | Resin-sealed semiconductor device and method of manufacturing the same |
-
2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09246571A (en) * | 1996-03-13 | 1997-09-19 | Hitachi Ltd | Manufacture of diode |
| JPH10125628A (en) * | 1996-10-24 | 1998-05-15 | Hitachi Ltd | Electrode-forming method of glass-coated semiconductor device |
| JPH10294473A (en) * | 1997-04-17 | 1998-11-04 | Hitachi Ltd | Surface-mount type semiconductor device and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731675A (en) * | 2017-09-18 | 2018-02-23 | 山东晶导微电子有限公司 | A kind of semiconductor wafer mechanical slotting technique |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201428860A (en) | 2014-07-16 |
| CN103975422B (en) | 2016-09-14 |
| JPWO2014083647A1 (en) | 2017-01-05 |
| TWI556330B (en) | 2016-11-01 |
| JP5308595B1 (en) | 2013-10-09 |
| CN103975422A (en) | 2014-08-06 |
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