JP2006173366A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for activating and forming a second principal surface side p+ collector layer 8 of a substrate by a low temperature heat treatment (anneal furnace) which does not detrimentally affect the existence of the metallic film of a first principal surface side gate and the emitter electrode of the substrate in an n-type semiconductor substrate 7. <P>SOLUTION: In a process for forming a p+ collector layer 8, ion implantation of boron (B<SP>+</SP>) or boron bifluoride (BF<SB>2</SB><SP>+</SP>) is carried out at accumulated 2E15/cm<SP>2</SP>, ion implantation is carried out twice or three times divisionally, and heating is carried out for 16 hours at 500°C in a low temperature anneal furnace for each divided ion implantation process, thus activating and forming a p<SP>+</SP>collector layer 8 at a low temperature. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a manufacturing method used for a semiconductor substrate in an insulated gate bipolar transistor (IGBT) semiconductor device.

Insulated gate bipolar transistors (IGBTs) are generally manufactured using an expensive epitaxial wafer (p ⁺ substrate and n layer) and an n-type semiconductor substrate that is less expensive (see, for example, Patent Document 1).

When manufacturing an IGBT using an n-type semiconductor substrate, it is necessary to form an active portion of a gate electrode and an emitter electrode on the first main surface and then form a p ⁺ collector layer on the second main surface. This is because it is necessary to grind the second main surface of the n-type semiconductor substrate in order to reduce the on-voltage, and then the p ⁺ collector layer is formed.

Therefore, when an n-type semiconductor substrate is used, in the step of forming a p ⁺ collector layer on the second main surface of the n-type semiconductor substrate, a high-temperature heat treatment at 900 ° C. or higher is generally required. Heat treatment at a temperature lower than the temperature (577 ° C.) at which the metal film of the main surface gate and emitter electrode melts or deteriorates is indispensable.
JP 2001-160559 A

The present invention has been made in view of the above-described circumstances, and uses an n-type semiconductor substrate, and the substrate by low-temperature processing that does not adversely affect the presence of the metal film of the first main surface gate and emitter electrode of the substrate. It is an object of the present invention to provide a manufacturing method for forming a p ⁺ collector layer on the second main surface.

  In order to solve the above problems, the present invention provides a first step of preparing a first conductivity type semiconductor substrate having a first main surface and a second main surface, and the semiconductor substrate includes the second step. A second step of implanting impurities of the second conductivity type from the main surface of the semiconductor substrate in an ion state, and a third step of activating the impurities implanted into the semiconductor substrate by heat treatment. Forming a single second conductivity type high impurity concentration layer on the second main surface of the semiconductor substrate by executing the step and the third step twice or three times in this order. This is a feature of a semiconductor device manufacturing method.

  The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon (Si) substrate.

The ionic species for forming the second conductivity type high impurity concentration layer on the second main surface of the semiconductor substrate is boron (B ⁺ ) or boron difluoride (BF ₂ ⁺ ). 1. A method for manufacturing a semiconductor device according to 1.

^{2. The} method of manufacturing a semiconductor device according to claim 1, wherein a dose amount per one impurity introduction step is 2E15 / cm ² or less.

  The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment step is performed by heating at 500 ° C. for 16 hours.

  According to the present invention, the impurity can be activated by performing divided impurity introduction for ion implantation and low-temperature heat treatment in the semiconductor substrate for each division of impurity introduction. Low-temperature heat treatment uses an annealing furnace, so that the semiconductor device can be made inexpensive.

In an insulated gate bipolar transistor using an n-type semiconductor substrate, boron (B ⁺ ) or boron difluoride (BF) is formed in the step of forming the p ⁺ collector layer of the second main surface using the n-type semiconductor substrate. ₂ ⁺ ) is divided into a predetermined amount of ion implantation, and low-temperature heat treatment (using an annealing furnace) is performed for each of the divided steps of the ion implantation, thereby activating the first principal surface electrode at a low temperature. It is a production method that can be performed.

FIGS. 1 to 3 show an n-type semiconductor substrate 7 prepared from a first main surface showing only one half of one part of an element active portion and a second main surface including a single p ⁺ high impurity concentration layer. It is sectional drawing which shows the manufacturing method of the insulated gate bipolar transistor (IGBT) which becomes this in order of a process.

FIG. 1 is a cross-sectional view of a process example before forming an IGBT p ⁺ collector layer using an n-type semiconductor substrate 7 according to an embodiment of the present invention. After the gate oxide film 4 and the gate electrode film (polycrystalline silicon) 3 are formed on the first main surface of the n-type semiconductor substrate 7, the emitter layer 5 is formed after the base layer 6 is formed. Thereafter, after forming and processing the interlayer insulating film 2, the emitter electrode film 1 is formed and processed.

FIG. 2 is a cross-sectional view of the process of forming the p ⁺ collector layer 8 after the process of FIG. The 2E15 / cm ² ion implantation of B ⁺ or BF ₂ ⁺ ions is divided twice, and heat treatment is performed in an annealing furnace at 500 ° C. for 16 hours for each division. As two exemplary division, the ion implantation dose 1E15 / cm ^2, then heat treated 500 ° C. 16 hours at an annealing furnace, performing the ion implantation dose 1E15 / cm ^2, 500 ℃ 16 hours of heat treatment at an annealing furnace in addition . Note that heat treatment at 500 ° C. for 16 hours or longer is desirable to recover crystal defects in the ion implantation. FIG. 3 is a cross-sectional view of the process of forming the p ⁺ collector electrode film 9 after the process of FIG.

Since the p ⁺ collector layer 8 formed as described above has a low specific resistance compared to the case where the p ⁺ collector layer 8 is formed without being divided, it is possible to realize a good ohmic property with the p ⁺ collector electrode film 9. it can.

Finally, as an example of an assembly process for a package, although not shown, the planar IGBT in the wafer state is made into chips by dicing. In the chip, the gate electrode film and the emitter electrode film 3 are connected to the gate and the emitter terminal by aluminum wire bonding, respectively, and the p ⁺ collector electrode film 9 is connected to the frame (collector terminal) by soldering and sealed with resin. The

Note that the present invention can also be applied to a structure in which an n ⁺ buffer layer is provided between the n-type semiconductor substrate 7 and the p ⁺ collector layer 8.

Alternatively, the ion implantation dose amount of 0.5E15 / cm ^{2 in} an annealing furnace is heated at 500 ° C. for 16 hours, and the ion implantation dose amount of 0.5E15 / cm ^2, and heat treated 500 ° C. 16 hours at an annealing furnace, performing the ion implantation dose 1E15 / cm ^2, 500 ℃ 16 hours of heat treatment at an annealing furnace in addition.

FIG. 4 is a relationship diagram between BF ₂ ⁺ accumulated dose and sheet resistance of the P ⁺ collector layer 8 in the heat treatment at 500 ° C. for 16 hours for each number of BF ₂ ⁺ ion implantation divisions. Paying attention to the case where the process is performed without dividing, the sheet resistance should be reduced by the increase of the dose amount. However, if the ion implantation is performed at a dose amount exceeding 2E15 / cm ² , it is formed at the time of ion implantation. It can be understood that the sheet resistance increases conversely with the increase in the dose because the crystal defects to be made are difficult to recover in the subsequent low-temperature heat treatment at 500 ° C. Therefore, it is desirable that the dose amount per ion implantation step is 2E15 / cm ² . Further, when attention is paid to the case where the division is performed, it can be seen that the sheet resistance of the four-time division method in the p ⁺ collector layer 8 is substantially the same as the two-time or three-time division processing method in the first and second embodiments. Therefore, it is preferable to use two or three divisions with a short processing time.

  The present invention can also be applied to a structure in which the second main surface of an IGBT n-type semiconductor substrate of the IGBT whose first main surface is a trench type is ground.

The IGBT example sectional drawing before the process of forming a p ⁺ collector layer in the 2nd main surface of the n-type semiconductor substrate 7 which concerns on the 1st Example of this invention. 1 is a cross-sectional view of an IGBT example after forming a p ⁺ collector layer 8 after the implementation step. FIG. 3 is a cross-sectional view of an IGBT example after a collector electrode film 9 is formed on the p ⁺ collector layer 8 after FIG. relationship diagram _BF ^{2 +} dose and the sheet resistance in the _BF ^{2 +} ion implantation division number for each and _BF ^{2 +} ion implantation dividing 500 ° C. 16 hours of heat treatment for each of the p ⁺ collector layer 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Emitter electrode film 2 Interlayer insulation film 3 Gate electrode film 4 Gate oxide film 5 Emitter layer 6 Base layer 7 N-type semiconductor substrate 8 Collector layer 9 Collector electrode film

Claims (5)

A first step of preparing a first conductivity type semiconductor substrate having a first main surface and a second main surface;
A second step of implanting ions of a second conductivity type from the second main surface into the semiconductor substrate in an ion state;
And a third step of activating the impurity implanted into the semiconductor substrate by heat treatment,
By performing the second step and the third step twice or three times in this order, a single second conductivity type high impurity concentration layer is formed on the second main surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon (Si) substrate. The ionic species for forming the second conductivity type high impurity concentration layer on the second main surface of the semiconductor substrate is boron (B ⁺ ) or boron difluoride (BF ₂ ⁺ ). 2. A method for manufacturing a semiconductor device according to 1. ^{2. The} method of manufacturing a semiconductor device according to claim 1, wherein a dose per one time of the impurity introduction step is 2E15 / cm ² or less. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment step is performed by heating at 500 ° C. for 16 hours.

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