JPH10294448A - Manufacture of high breakdown voltage semiconductor device - Google Patents

Manufacture of high breakdown voltage semiconductor device

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Publication number
JPH10294448A
JPH10294448A JP10423797A JP10423797A JPH10294448A JP H10294448 A JPH10294448 A JP H10294448A JP 10423797 A JP10423797 A JP 10423797A JP 10423797 A JP10423797 A JP 10423797A JP H10294448 A JPH10294448 A JP H10294448A
Authority
JP
Japan
Prior art keywords
type semiconductor
semiconductor region
semiconductor device
silicon dioxide
sol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10423797A
Other languages
Japanese (ja)
Inventor
Susumu Murakami
進 村上
Yasuo Onose
保夫 小野瀬
Shin Morishima
森島  慎
Masao Tsuruoka
征男 鶴岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10423797A priority Critical patent/JPH10294448A/en
Publication of JPH10294448A publication Critical patent/JPH10294448A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To prevent a punch through breakdown from occurring at a transistor part with a pnp structure, by applying an inorganic polymer precursor substance onto a pn-junction surface by the sol/gel method, and forming a silicone rubber finally. SOLUTION: Polyimide resin 7 that is a second insulation film is formed on a silicon dioxide film 6, and further a third insulation film a silicone rubber 8, is formed on it. A positive electric charge 10 exists in the silicon dioxide film 6. Even if a slight negative electric charge occurs in the second insulation film 7 and the third insulation film 8, it can be regarded that a positive electric charge exists in first, second, and third insulation films effectively due to the positive electric charge 10. An accumulation layer where the number of electrons is larger inside is formed on an n-type semiconductor region, thus extending the distance between an edge part 91b of a depletion layer being spread into the n-type semiconductor region and a p-type semiconductor region 3 as compared with the inside, and preventing a punch through breakdown from occurring at a transistor part with a pnp structure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は高耐圧半導体装置の
表面安定化保護膜を形成する製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a surface stabilizing protective film of a high breakdown voltage semiconductor device.

【0002】[0002]

【従来の技術】高耐圧半導体装置に関する従来技術とし
て、例えばIEE PROC.Vol.129,Pt.I
No.5,p.376(1982)に記載された技術が
知られている。この従来技術は、サイリスタの側面に露
出したpnp構造を2重正ベベル形状に加工したもので
あり、pn接合に逆バイアスが印加された場合、表面の
空乏層は正ベベル構造により主にn層側に広がるので高
耐圧化が達成でき、端面の窪んだところでは逆に空乏層
が広がりにくくなるので、端面のpnp部でのパンチス
ルー降伏を防止できるとされている。
2. Description of the Related Art As a prior art relating to a high breakdown voltage semiconductor device, for example, IEEE PROC. Vol.129, Pt.I
No. 5, p. 376 (1982) is known. In this prior art, a pnp structure exposed on a side surface of a thyristor is processed into a double positive bevel shape. When a reverse bias is applied to a pn junction, a depletion layer on the surface is mainly an n-layer due to the positive bevel structure. It is described that a high withstand voltage can be achieved because it spreads to the side, and a depletion layer is unlikely to spread at a concave portion of the end face, so that punch-through breakdown at a pnp portion of the end face can be prevented.

【0003】また、高耐圧の半導体装置を製造する従来
技術として、特開平3−245536 号公報に開示された技術
が知られている。この従来技術では、pn接合が側面に
露出した半導体基板の一主面を金属板の上面に固着し、
側面をエッチングした後側面に生じた酸化膜を除去し、
側面を保護膜で被覆する製造方法により、従来のような
pn接合の露出した表面が重金属を含む酸化膜により被
覆されることが防止できるので、酸化膜中の重金属を介
した漏れ電流が防止でき、信頼性の優れた高耐圧半導体
装置が得られるとされている。
As a conventional technique for manufacturing a semiconductor device having a high breakdown voltage, a technique disclosed in Japanese Patent Application Laid-Open No. 3-245536 is known. In this conventional technique, one main surface of a semiconductor substrate having a pn junction exposed on a side surface is fixed to an upper surface of a metal plate,
After etching the side surface, remove the oxide film generated on the side surface,
By the manufacturing method of covering the side surfaces with the protective film, the exposed surface of the pn junction can be prevented from being covered with the oxide film containing the heavy metal as in the related art, so that the leakage current through the heavy metal in the oxide film can be prevented. It is said that a high breakdown voltage semiconductor device having excellent reliability can be obtained.

【0004】[0004]

【発明が解決しようとする課題】前述した前者の従来技
術は、いわゆる主サイリスタの阻止電圧を高める利点を
有し、後者の従来技術は、いわゆる端面のpnpトラン
ジスタ部の重金属を含む汚染された酸化膜を除去し、清
浄な半導体表面を得る効果はあるが、表面保護膜中の電
荷の極性や大きさの変動により、所定の電圧を印加した
まま高温にさらす寿命試験などで、リーク電流が増加し
たり、耐圧が低下する問題点に関しては考慮されていな
かった。
The former prior art described above has the advantage of increasing the blocking voltage of the so-called main thyristor, while the latter prior art has the advantage that the so-called contaminated oxidation containing heavy metals in the so-called pnp transistor section at the end face. Although it has the effect of removing the film and obtaining a clean semiconductor surface, the leakage current increases due to fluctuations in the polarity and magnitude of the charge in the surface protective film, such as in life tests where the film is exposed to high temperatures with a specified voltage applied. And the problem of reduced withstand voltage has not been considered.

【0005】本発明の目的は、従来の半導体装置の製造
方法の問題点を解決した信頼性の高い半導体装置の製造
方法を提供することにある。
An object of the present invention is to provide a highly reliable semiconductor device manufacturing method which solves the problems of the conventional semiconductor device manufacturing method.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
の本発明による半導体装置の製造方法の特徴は、一対の
主表面を有し、少なくとも一つのpn接合が側面に露出
している半導体基体と前記半導体基体の側面に露出した
pn接合の表面に絶縁保護膜を形成する半導体装置の製
造方法において、pn接合表面にゾル・ゲル法により無
機ポリマ前駆物質をスピン塗布するか、あるいは浸漬塗
布した後に加熱乾燥・硬化させ二酸化珪素膜を被覆する
工程と、ポリイミド樹脂をスピン塗布するか、あるいは
浸漬塗布した後に加熱乾燥・硬化させ形成する工程と、
シリコーンゴムを形成する工程を含む高耐圧半導体装置
の製造方法としたものである。
A feature of a method of manufacturing a semiconductor device according to the present invention to achieve the above object is that a semiconductor substrate has a pair of main surfaces and at least one pn junction is exposed on a side surface. And a method of manufacturing a semiconductor device in which an insulating protective film is formed on a surface of a pn junction exposed on a side surface of the semiconductor substrate, wherein an inorganic polymer precursor is spin-coated or immersed on the pn-junction surface by a sol-gel method. A step of coating the silicon dioxide film by heating and drying afterwards, and a step of forming by heating and drying and curing after spin coating or dip coating the polyimide resin,
This is a method for manufacturing a high withstand voltage semiconductor device including a step of forming a silicone rubber.

【0007】さらに、ゾル・ゲル法による二酸化珪素膜
はテトラエトキシシラン,純水,硝酸,エタノールを混
合して無機ポリマ前駆物質とした製造方法としたもので
ある。
Further, the silicon dioxide film formed by the sol-gel method is a method of producing an inorganic polymer precursor by mixing tetraethoxysilane, pure water, nitric acid and ethanol.

【0008】[0008]

【発明の実施の形態】以下、本発明の実施例を図面を用
いて説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0009】(実施例1)図1は本発明による高耐圧半
導体装置の第1実施例を示す断面図である。図1の実施
例では半導体装置としてサイリスタの断面図を示してい
る。1はnベース層となるn型半導体領域、2はpベー
ス層となるp型半導体領域、3はpエミッタ層となるp
+型半導体領域、4はnエミッタ層となるn+型半導体
領域、40は主サイリスタのカソード電極、41は光ト
リガ信号を受光するサイリスタのカソード電極、42は
補助サイリスタのカソード電極であり、p+型半導体領
域3にはアノード電極30が接続されている。6は本発
明によるゾル・ゲル法を用いて形成した二酸化珪素膜で
あり、二酸化珪素膜6上に第2絶縁膜であるポリイミド
樹脂7が形成され、さらにポリイミド樹脂7上に第3絶
縁膜であるシリコーンゴム8が形成されている。
FIG. 1 is a sectional view showing a first embodiment of a high breakdown voltage semiconductor device according to the present invention. In the embodiment of FIG. 1, a sectional view of a thyristor is shown as a semiconductor device. 1 is an n-type semiconductor region serving as an n-base layer, 2 is a p-type semiconductor region serving as a p-base layer, and 3 is p-type semiconductor region serving as a p-emitter layer.
A + type semiconductor region, 4 an n + type semiconductor region serving as an n emitter layer, 40 a cathode electrode of a main thyristor, 41 a cathode electrode of a thyristor for receiving a light trigger signal, 42 a cathode electrode of an auxiliary thyristor, and a p + type An anode electrode 30 is connected to the semiconductor region 3. Reference numeral 6 denotes a silicon dioxide film formed by using the sol-gel method according to the present invention. A polyimide resin 7 as a second insulating film is formed on the silicon dioxide film 6, and a third insulating film is formed on the polyimide resin 7. A certain silicone rubber 8 is formed.

【0010】図2は本発明によるゾル・ゲル法を用いて
形成した二酸化珪素膜6が信頼性向上に有効となる動作
を説明する図である。図2において、図1と同じ符号に
ついては、説明を省略する。図2において、9はアノー
ド電極30が正、カソード電極40が負となる順方向阻
止電圧が印加された場合に、nベース層となるn型半導
体領域1とpベース層となるp型半導体領域2からなる
pn接合から広がる空乏層であり、91a及び91bは
p型半導体領域2に広がる空乏層端、92a及び92b
はn型半導体領域1に広がる空乏層端である。10は本
発明による二酸化珪素膜中の正電荷である。
FIG. 2 is a view for explaining an operation in which the silicon dioxide film 6 formed by using the sol-gel method according to the present invention is effective for improving the reliability. 2, the description of the same reference numerals as those in FIG. 1 is omitted. In FIG. 2, reference numeral 9 denotes an n-type semiconductor region 1 serving as an n-base layer and a p-type semiconductor region serving as a p-base layer when a forward blocking voltage in which the anode electrode 30 is positive and the cathode electrode 40 is negative is applied. 2, a depletion layer 91a and 91b extending from the pn junction composed of Pn.
Is a depletion layer end extending to the n-type semiconductor region 1. 10 is a positive charge in the silicon dioxide film according to the present invention.

【0011】順方向阻止電圧を印加すると、n型半導体
領域1に広がる空乏層の端部91bはn型半導体領域1
とp型半導体領域2からなるpn接合の端面が正ベベル
構造となっているため、比較的印加電圧の低い場合は端
面での空乏層幅は内部より広くなって、電界強度を下げ
る働きがある。また、さらに順方向阻止電圧を高くする
と、空乏層端92bはさらに広がるが、n型半導体領域
1とp型半導体領域3からなるpn接合の端面が負ベベ
ル構造となっているため、n型半導体領域1表面では内
部より広がりにくくなって、表面において、pnp構造
のパンチスルー降伏が生じにくい構造となっている。
When a forward blocking voltage is applied, the end portion 91b of the depletion layer extending to the n-type semiconductor region 1 becomes
Since the end face of the pn junction composed of the p-type semiconductor region 2 and the p-type semiconductor region 2 has a positive bevel structure, when the applied voltage is relatively low, the width of the depletion layer at the end face becomes wider than the inside, and has a function of lowering the electric field strength. . Further, when the forward blocking voltage is further increased, the depletion layer end 92b further expands, but since the end face of the pn junction formed by the n-type semiconductor region 1 and the p-type semiconductor region 3 has a negative bevel structure, the n-type semiconductor The surface of the region 1 is hardly spread from the inside, and the surface has a structure in which punch-through breakdown of a pnp structure is unlikely to occur.

【0012】ところが、順方向阻止電圧を印加したまま
高温にさらす、いわゆる高温バイアス試験等を実施する
と、本発明による二酸化珪素膜中の正電荷10が無く第
2の絶縁膜7が直接n型半導体領域1に接して形成され
ている場合、第2の絶縁膜7及び第3の絶縁膜8中に僅
かの約1〜6×1010/cm2 の負電荷が発生し、n型半
導体領域1の表面に空乏層あるいは反転層が形成される
ため、p型半導体領域2,n型半導体領域1及びp+型
半導体領域3からなるpnp構造を有するトランジスタ
部でパンチスルー降伏が生じ耐圧が低下したり、リーク
電流が増加する問題がある。そこで、本発明によるゾル
・ゲル法を用いて形成した二酸化珪素膜6中には約1〜
2×1011/cm2 程度の正電荷10が存在しているの
で、たとえ第2の絶縁膜7及び第3の絶縁膜8中に僅か
の約1〜6×1010/cm2 の負電荷が発生しても、本発
明によるゾル・ゲル法を用いて形成した二酸化珪素膜6
中の約1〜2×1011/cm2 程度の正電荷10のため、
実効的に0.4〜1.9×1011/cm2 の正電荷が第1絶縁
膜,第2絶縁膜及び第3絶縁膜中に存在しているとみな
すことができ、n型半導体領域1の表面には電子が内部
より多い蓄積層が形成されるので、図2に示したように
n型半導体領域に広がる空乏層の端部91bとp型半導
体領域3との距離は内部より端面の方で長くすることが
できる。従って、端面においてp型半導体領域2,n型
半導体領域1及びp+型半導体領域3からなるpnp構
造を有するトランジスタ部でパンチスルー降伏が生じな
く各種寿命試験で耐圧の低下を起こすことがなく、極め
て高信頼の半導体装置を得ることができる。
However, when a so-called high-temperature bias test or the like is performed in which the semiconductor device is exposed to a high temperature while a forward blocking voltage is applied, no positive charge 10 is present in the silicon dioxide film according to the present invention, and the second insulating film 7 is directly connected to the n-type semiconductor. When formed in contact with the region 1, a slight negative charge of about 1 to 6 × 10 10 / cm 2 is generated in the second insulating film 7 and the third insulating film 8, and the n-type semiconductor region 1 is formed. Since a depletion layer or an inversion layer is formed on the surface of the transistor, punch-through breakdown occurs in the transistor portion having a pnp structure including the p-type semiconductor region 2, the n-type semiconductor region 1, and the p + -type semiconductor region 3, and the breakdown voltage is reduced. However, there is a problem that the leak current increases. Therefore, the silicon dioxide film 6 formed by using the sol-gel method according to the present invention has about 1 to
Since a positive charge 10 of about 2 × 10 11 / cm 2 is present, even a slight negative charge of about 1 to 6 × 10 10 / cm 2 exists in the second insulating film 7 and the third insulating film 8. Occurs, the silicon dioxide film 6 formed using the sol-gel method according to the present invention.
Because of the positive charge 10 of about 1-2 × 10 11 / cm 2 ,
Effectively, it can be considered that a positive charge of 0.4 to 1.9 × 10 11 / cm 2 exists in the first insulating film, the second insulating film, and the third insulating film, and the n-type semiconductor region 2, a distance between the end 91b of the depletion layer spreading over the n-type semiconductor region and the p-type semiconductor region 3 is larger than that of the inside, as shown in FIG. Can be longer. Therefore, punch-through breakdown does not occur in the transistor portion having the pnp structure including the p-type semiconductor region 2, the n-type semiconductor region 1, and the p + -type semiconductor region 3 on the end face, and the breakdown voltage does not decrease in various life tests. A highly reliable semiconductor device can be obtained.

【0013】次に本発明による図1に示した高耐圧半導
体装置の製造方法について述べる。まず、抵抗率が50
0±50Ω・cmの高抵抗のn型半導体基板1の両主表面
からp型不純物となるアルミニウムを拡散する。この場
合の表面不純物濃度は約1×1016/cm3 、拡散深さは
約150μmである。このとき、最終のnエミッタ層と
なるn+型半導体領域4を形成した場合、n+型半導体
領域4直下のpベース層となるp型半導体領域2のシー
ト抵抗が約800〜900Ω/□となるように、エッチ
ングによりその厚さが調整される。
Next, a method of manufacturing the high breakdown voltage semiconductor device shown in FIG. 1 according to the present invention will be described. First, the resistivity is 50
Aluminum serving as a p-type impurity is diffused from both main surfaces of the n-type semiconductor substrate 1 having a high resistance of 0 ± 50 Ω · cm. In this case, the surface impurity concentration is about 1 × 10 16 / cm 3 and the diffusion depth is about 150 μm. At this time, when the n + type semiconductor region 4 serving as the final n emitter layer is formed, the sheet resistance of the p type semiconductor region 2 serving as the p base layer immediately below the n + type semiconductor region 4 is about 800 to 900 Ω / □. Then, the thickness is adjusted by etching.

【0014】続いて、表面不純物濃度が約1×1019
1×1020/cm3 の高不純物濃度のnエミッタ層となる
n+型半導体領域4を次亜塩素酸リンを用いたP(リ
ン)の拡散により、深さが約8μmとなるように形成す
る(a)。
Subsequently, the surface impurity concentration is about 1 × 10 19 to
An n + type semiconductor region 4 serving as an n emitter layer having a high impurity concentration of 1 × 10 20 / cm 3 is formed to a depth of about 8 μm by diffusion of P (phosphorus) using phosphorous hypochlorite. (A).

【0015】引き続いて、公知のホトエッチングにより
カソード側のn+型半導体領域4を分割し、両主表面に
アルミニウムを蒸着し、カソード側のアルミニウムを公
知のホトエッチングにより加工し、p型半導体領域2と
部分的に短絡される主サイリスタのカソード電極40,
光トリガ信号を受光するサイリスタのカソード電極4
1,補助サイリスタのカソード電極42を形成し、アノ
ード側のアルミニウムを公知のホトエッチングにより加
工し、アノード電極30を形成する(b)。次に、ウェ
ハの端面を公知のサンドブラスト法あるいは研削機械を
用いるベベリング技術によりΣ形状に加工し、Σ形状に
加工された端面をエッチングし加工歪みを除去し、純水
洗浄を実施し乾燥させた後、本発明によるゾル・ゲル法
を用いて形成する第1絶縁膜となる二酸化珪素膜6を被
着する(c)。
Subsequently, the n + type semiconductor region 4 on the cathode side is divided by known photoetching, aluminum is vapor-deposited on both main surfaces, and the aluminum on the cathode side is processed by known photoetching to form a p-type semiconductor region 2. The cathode electrode 40 of the main thyristor partially short-circuited with
Cathode electrode 4 of thyristor that receives light trigger signal
1. The cathode electrode 42 of the auxiliary thyristor is formed, and aluminum on the anode side is processed by known photoetching to form the anode electrode 30 (b). Next, the end face of the wafer was processed into a Σ shape by a known sand blasting method or a beveling technique using a grinding machine, the end face processed into the Σ shape was etched to remove processing distortion, washed with pure water, and dried. Thereafter, a silicon dioxide film 6 serving as a first insulating film formed using the sol-gel method according to the present invention is deposited (c).

【0016】二酸化珪素膜6の形成には、テトラエトキ
シシラン,純水,硝酸,エタノールをモル比で1:1
3:0.25:45 の割合で混合した原料をスピン塗布
し、大気中で200〜500℃の温度範囲で加熱乾燥・
硬化させた。なお、アノード電極30及びカソード電極
40を気密性の良いカバーで覆い、浸漬塗布した後に加
熱乾燥・硬化させてもよい。さらに第1絶縁膜上にポリ
イミド樹脂等の第2絶縁膜をスピン塗布し、80℃のホ
ットプレート上で5分間乾燥した後、窒素雰囲気中で1
00℃で1時間、150℃で1時間、250℃で4時間
加熱し硬化させた(d)。
The silicon dioxide film 6 is formed by mixing tetraethoxysilane, pure water, nitric acid and ethanol at a molar ratio of 1: 1.
The raw materials mixed at a ratio of 3: 0.25: 45 are spin-coated, and dried by heating at a temperature range of 200 to 500 ° C. in the air.
Cured. The anode electrode 30 and the cathode electrode 40 may be covered with a cover having good airtightness, dipped and then dried and cured by heating. Further, a second insulating film such as a polyimide resin is spin-coated on the first insulating film, and dried on a hot plate at 80 ° C. for 5 minutes.
It was cured by heating at 00 ° C. for 1 hour, 150 ° C. for 1 hour, and 250 ° C. for 4 hours (d).

【0017】その後、所定の型を有する容器に半導体基
体を入れ、前記第2絶縁膜上に第3絶縁膜となるシリコ
ーンゴムを充填した後、窒素雰囲気中で100℃で1時
間、150℃で1時間、200℃で2時間加熱し硬化さ
せた(e)。
Thereafter, the semiconductor substrate is placed in a container having a predetermined mold, and silicone rubber to be a third insulating film is filled on the second insulating film. It was cured by heating at 200 ° C. for 2 hours for 1 hour (e).

【0018】最後に、この半導体装置基体をセラミック
パッケージに納め、パッケージ内部の雰囲気を乾燥窒素
とし、密閉して高耐圧半導体装置を完成する。前述の工
程を経て製造された半導体装置の耐圧は9000Vであ
り、そのばらつきは±300Vであった。
Finally, the semiconductor device base is placed in a ceramic package, the atmosphere inside the package is made of dry nitrogen, and the package is sealed to complete a high withstand voltage semiconductor device. The breakdown voltage of the semiconductor device manufactured through the above-described steps was 9000 V, and the variation was ± 300 V.

【0019】(実施例2)図4は本発明による高耐圧半
導体装置の製造方法をゲートターンオフサイリスタに適
用した例を示す。図4において、図1と同符号のものは
説明を省略する。5はアノード短絡用のn+型半導体領
域、20はpベース層となるp型半導体領域に接続され
たゲート電極である。図1では半導体基体の端面がΣ形
状にベベリング加工されていたが、図4に示したゲート
ターンオフサイリスタでは、順方向のみ阻止機能を有す
るのでp型半導体領域2とn型半導体領域1からなるp
n接合の端面は正ベベル形状に加工されている。本発明
による絶縁膜の形成方法は図3で詳細に説明したものと
ほぼ同様であり、所定の各半導体領域を拡散で形成し、
電極を蒸着加工した後、端面が正ベベルとなるようウェ
ハの端面を公知のサンドブラスト法あるいは研削機械を
用いるベベリング技術により正ベベル形状に加工し、加
工された端面をエッチングし加工歪みを除去し、純水洗
浄を実施し乾燥させた後、本発明によるゾル・ゲル法を
用いて形成する第1絶縁膜6,第2絶縁膜7,第3絶縁
膜8を形成し、最後に半導体装置基体をセラミックパッ
ケージに納め、パッケージ内部の雰囲気を乾燥窒素と
し、密閉して高耐圧半導体装置を完成した。製造された
半導体装置の耐圧は8000Vであり、そのばらつきは
±200Vであり、特に本発明によるゾル・ゲル法を用
いて形成した第1絶縁膜6中に正の電荷が存在している
ので、順方向阻止電圧を印加したまま高温にさらす、い
わゆる高温バイアス試験等を実施しても、n型半導体領
域1の表面には電子が内部より多い蓄積層が形成され、
n型半導体領域1の表面がp型に反転してn+型半導体
領域5近傍のn型半導体領域1表面での電界集中による
耐圧低下を防止することができる。
(Embodiment 2) FIG. 4 shows an example in which a method for manufacturing a high breakdown voltage semiconductor device according to the present invention is applied to a gate turn-off thyristor. In FIG. 4, the description of the same reference numerals as in FIG. 1 is omitted. Reference numeral 5 denotes an n + type semiconductor region for anode short circuit, and reference numeral 20 denotes a gate electrode connected to a p-type semiconductor region serving as a p-base layer. In FIG. 1, the end face of the semiconductor substrate is beveled in the shape of a triangle. However, the gate turn-off thyristor shown in FIG. 4 has a blocking function only in the forward direction, and thus has a p-type semiconductor region 2 and an n-type semiconductor region 1.
The end surface of the n-junction is processed into a regular bevel shape. The method of forming an insulating film according to the present invention is substantially the same as that described in detail with reference to FIG.
After depositing the electrode, the end surface of the wafer is processed into a regular bevel shape by a known sand blasting method or a beveling technique using a grinding machine so that the end surface becomes a positive bevel, and the processed end surface is etched to remove processing distortion, After cleaning with pure water and drying, a first insulating film 6, a second insulating film 7, and a third insulating film 8 are formed by using the sol-gel method according to the present invention. The package was housed in a ceramic package, the atmosphere inside the package was made of dry nitrogen, and the package was sealed to complete a high withstand voltage semiconductor device. The withstand voltage of the manufactured semiconductor device is 8000 V, and its variation is ± 200 V. Particularly, since a positive charge exists in the first insulating film 6 formed by using the sol-gel method according to the present invention, Even if a so-called high-temperature bias test or the like is performed while exposing the substrate to a high temperature while applying a forward blocking voltage, a storage layer having more electrons than the inside is formed on the surface of the n-type semiconductor region 1,
The surface of the n-type semiconductor region 1 is inverted to the p-type, and it is possible to prevent a decrease in breakdown voltage due to electric field concentration on the surface of the n-type semiconductor region 1 near the n + -type semiconductor region 5.

【0020】(実施例3)図5は本発明による高耐圧半
導体装置の製造方法をダイオードに適用した例を示す。
図5において、図1と同符号のものは説明を省略する。
11はn型半導体領域、13はアノード層となるp+型
半導体領域、14はカソード層となるn+型半導体領域
である。図4に示したゲートターンオフサイリスタと同
様に、p+型半導体領域13とn型半導体領域11から
なるpn接合の端面は正ベベル形状に加工されている。
本発明による絶縁膜の形成方法は図3で詳細に説明した
ものとほぼ同様であり、所定の各半導体領域を拡散で形
成し、電極を蒸着加工した後、端面が正ベベルとなるよ
うウェハの端面を公知のサンドブラスト法あるいは研削
機械を用いるベベリング技術により正ベベル形状に加工
し、加工された端面をエッチングし加工歪みを除去し、
純水洗浄を実施し乾燥させた後、本発明によるゾル・ゲ
ル法を用いて形成する第1絶縁膜6,第2絶縁膜7,第
3絶縁膜8を形成し、最後に半導体装置基体をセラミッ
クパッケージに納め、パッケージ内部の雰囲気を乾燥窒
素とし、密閉して高耐圧半導体装置を完成した。製造さ
れた半導体装置の耐圧は6000Vであり、そのばらつ
きは±200Vであった。
(Embodiment 3) FIG. 5 shows an example in which a method of manufacturing a high breakdown voltage semiconductor device according to the present invention is applied to a diode.
5, the description of the same reference numerals as in FIG. 1 is omitted.
Reference numeral 11 denotes an n-type semiconductor region, 13 denotes a p + -type semiconductor region serving as an anode layer, and 14 denotes an n + -type semiconductor region serving as a cathode layer. Similarly to the gate turn-off thyristor shown in FIG. 4, the end face of the pn junction composed of the p + type semiconductor region 13 and the n type semiconductor region 11 is processed into a regular bevel shape.
The method of forming an insulating film according to the present invention is substantially the same as that described in detail with reference to FIG. 3. After a predetermined semiconductor region is formed by diffusion, an electrode is vapor-deposited, and a wafer is formed so that an end face becomes a positive bevel. The end face is processed into a regular bevel shape by a known sand blasting method or beveling technique using a grinding machine, and the processed end face is etched to remove processing distortion,
After cleaning with pure water and drying, a first insulating film 6, a second insulating film 7, and a third insulating film 8 are formed by using the sol-gel method according to the present invention. The package was housed in a ceramic package, the atmosphere inside the package was made of dry nitrogen, and the package was sealed to complete a high withstand voltage semiconductor device. The withstand voltage of the manufactured semiconductor device was 6000 V, and its variation was ± 200 V.

【0021】また、図4で述べたように図5の実施例に
おいても同様の作用効果により、順方向阻止電圧を印加
したまま高温にさらす、いわゆる高温バイアス試験等を
実施しても、n+型半導体領域14近傍のn型半導体領
域11表面での電界集中による耐圧低下を防止すること
ができる。
As described with reference to FIG. 4, even in the embodiment shown in FIG. 5, even when a so-called high-temperature bias test or the like, in which the device is exposed to a high temperature while applying a forward blocking voltage, is performed, the n + type It is possible to prevent a decrease in withstand voltage due to electric field concentration on the surface of the n-type semiconductor region 11 near the semiconductor region 14.

【0022】以上詳述した本発明による高耐圧半導体装
置の製造方法において、p型半導体領域2を形成するの
にp型不純物のアルミニウムを用いて説明したが、p+
型半導体領域3,13の形成も同様に、本発明はなにも
p型不純物としてアルミニウムだけに限られず、ボロン
(B)やガリウム(Ga)を用いても構わない。また、
n+型半導体領域4を形成するのにn型不純物のリン
(P)を用いて説明したが、n+型半導体領域5,14
の形成も同様に、本発明はなにもn型不純物としてリン
だけに限られず、アンチモン(Sb)や砒素(As)を
用いても構わない。
In the method of manufacturing a high breakdown voltage semiconductor device according to the present invention described in detail above, the p-type semiconductor region 2 is formed using p-type impurity aluminum.
Similarly, the formation of the type semiconductor regions 3 and 13 is not limited to aluminum as the p-type impurity in the present invention, and boron (B) or gallium (Ga) may be used. Also,
Although the n + type semiconductor region 4 is formed using phosphorus (P) as an n type impurity, the n + type semiconductor regions 5 and 14 have been described.
Similarly, the present invention is not limited to phosphorus as an n-type impurity, and antimony (Sb) or arsenic (As) may be used.

【0023】さらに、以上詳述した本発明による高耐圧
半導体装置の製造方法によれば、高温バイアス試験(印
加電圧が定格電圧の80%、接合温度が125あるいは
150℃、試験時間が1000h)を実施したが、耐圧の
変動はなくリーク電流は初期値の40%増にとどまり、
高信頼性を示すことを確認した。また、高温放置試験
(接合温度が200℃、試験時間が1000h)を実施
したが、耐圧の変動はなくリーク電流は初期値の10%
増にとどまり、高信頼性を示すことを確認した。
Further, according to the method of manufacturing a high breakdown voltage semiconductor device of the present invention described in detail above, a high temperature bias test (applied voltage is 80% of rated voltage, junction temperature is 125 or
The test was performed at 150 ° C. and a test time of 1000 h). However, there was no change in the breakdown voltage, and the leakage current increased only 40% of the initial value.
High reliability was confirmed. A high-temperature storage test (junction temperature: 200 ° C., test time: 1000 h) was performed, but there was no change in withstand voltage and the leak current was 10% of the initial value.
It was confirmed that it showed high reliability.

【0024】[0024]

【発明の効果】本発明による高耐圧半導体装置の製造方
法によれば、有機物からなるパッシベーション膜中の電
荷の変動が多少あっても、高耐圧かつ高信頼の半導体装
置が得られる。
According to the method of manufacturing a high-breakdown-voltage semiconductor device according to the present invention, a high-breakdown-voltage and high-reliability semiconductor device can be obtained even if there is some variation in the charge in the passivation film made of an organic substance.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による高耐圧半導体装置の第1の実施例
を示す断面図。
FIG. 1 is a sectional view showing a first embodiment of a high breakdown voltage semiconductor device according to the present invention.

【図2】本発明による高耐圧半導体装置の動作を説明す
る断面図。
FIG. 2 is a cross-sectional view illustrating the operation of the high breakdown voltage semiconductor device according to the present invention.

【図3】本発明による高耐圧半導体装置の第1の実施例
の製造工程を示す説明図。
FIG. 3 is an explanatory view showing a manufacturing process of the first embodiment of the high breakdown voltage semiconductor device according to the present invention.

【図4】本発明による高耐圧半導体装置の製造方法を他
の半導体装置に適用した断面図。
FIG. 4 is a cross-sectional view in which the method of manufacturing a high breakdown voltage semiconductor device according to the present invention is applied to another semiconductor device.

【図5】本発明による高耐圧半導体装置の製造方法をさ
らに他の半導体装置に適用した断面図。
FIG. 5 is a cross-sectional view in which the method of manufacturing a high withstand voltage semiconductor device according to the present invention is applied to still another semiconductor device.

【符号の説明】[Explanation of symbols]

1,11…n型半導体領域、2…p型半導体領域、3,
13…p+型半導体領域、4,5,14…n+型半導体
領域、6…第1絶縁膜、7…第2絶縁膜、8…第3絶縁
膜、9…空乏層、10…正電荷、20…ゲ−ト電極、3
0…アノード電極、40,41,42…カソード電極、
91a,91b,92a,92b…空乏層端。
1,11 ... n-type semiconductor region, 2 ... p-type semiconductor region, 3,
13 ... p + type semiconductor region, 4,5,14 ... n + type semiconductor region, 6 ... first insulating film, 7 ... second insulating film, 8 ... third insulating film, 9 ... depletion layer, 10 ... positive charge, 20 ... Gate electrode, 3
0: anode electrode, 40, 41, 42: cathode electrode,
91a, 91b, 92a, 92b ... depletion layer ends.

フロントページの続き (72)発明者 鶴岡 征男 茨城県日立市幸町三丁目1番1号 株式会 社日立製作所日立工場内Continuing from the front page (72) Inventor Muneo Tsuruoka 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Pref. Hitachi, Ltd. Hitachi Plant

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】一対の主表面を有し、少なくとも一つのp
n接合が側面に露出している半導体基体と前記半導体基
体の側面に露出したpn接合の表面に絶縁保護膜を形成
する半導体装置の製造方法において、pn接合表面にゾ
ル・ゲル法による二酸化珪素膜を被覆する工程と、ポリ
イミド樹脂を形成する工程と、シリコーンゴムを形成す
る工程を含むことを特徴とする高耐圧半導体装置の製造
方法。
1. A semiconductor device having a pair of main surfaces and at least one p
In a method of manufacturing a semiconductor device in which an n-junction is exposed on a side surface of a semiconductor substrate and an insulating protective film is formed on a surface of the pn junction exposed on a side surface of the semiconductor substrate, a silicon dioxide film is formed on the pn junction surface by a sol-gel method. , A step of forming a polyimide resin, and a step of forming a silicone rubber.
【請求項2】ゾル・ゲル法による二酸化珪素膜は無機ポ
リマ前駆物質をスピン塗布するか、あるいは浸漬塗布し
た後に加熱乾燥・硬化させ、ポリイミド樹脂はスピン塗
布するか、あるいは浸漬塗布した後に加熱乾燥・硬化さ
せ、シリコーンゴムは半導体基体を所定の容器に入れ、
容器中に充填した後硬化させる請求項1に記載の高耐圧
半導体装置の製造方法。
2. A silicon dioxide film formed by a sol-gel method is spin-coated with an inorganic polymer precursor or heat-dried and cured after dip coating, and a polyimide resin is spin-coated or heat-dried after dip coating.・ Curing the silicone rubber, put the semiconductor substrate in a predetermined container,
The method for manufacturing a high-voltage semiconductor device according to claim 1, wherein the semiconductor device is cured after being filled in a container.
【請求項3】ゾル・ゲル法による二酸化珪素膜はテトラ
エトキシシラン,純水,硝酸,エタノールを混合して無
機ポリマ前駆物質とした請求項1に記載の高耐圧半導体
装置の製造方法。
3. The method according to claim 1, wherein the silicon dioxide film formed by the sol-gel method is a mixture of tetraethoxysilane, pure water, nitric acid, and ethanol to form an inorganic polymer precursor.
JP10423797A 1997-04-22 1997-04-22 Manufacture of high breakdown voltage semiconductor device Pending JPH10294448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10423797A JPH10294448A (en) 1997-04-22 1997-04-22 Manufacture of high breakdown voltage semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10423797A JPH10294448A (en) 1997-04-22 1997-04-22 Manufacture of high breakdown voltage semiconductor device

Publications (1)

Publication Number Publication Date
JPH10294448A true JPH10294448A (en) 1998-11-04

Family

ID=14375362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10423797A Pending JPH10294448A (en) 1997-04-22 1997-04-22 Manufacture of high breakdown voltage semiconductor device

Country Status (1)

Country Link
JP (1) JPH10294448A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102522333A (en) * 2012-01-09 2012-06-27 薛列龙 Manufacturing method for planar bidirectional trigger diode chip
JP2013004982A (en) * 2011-06-14 2013-01-07 Abb Technology Ag Bipolar punch-through semiconductor device and method for manufacturing such semiconductor device
JP2017022206A (en) * 2015-07-08 2017-01-26 東レエンジニアリング株式会社 Insulation protective film for semiconductor, and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013004982A (en) * 2011-06-14 2013-01-07 Abb Technology Ag Bipolar punch-through semiconductor device and method for manufacturing such semiconductor device
CN102522333A (en) * 2012-01-09 2012-06-27 薛列龙 Manufacturing method for planar bidirectional trigger diode chip
JP2017022206A (en) * 2015-07-08 2017-01-26 東レエンジニアリング株式会社 Insulation protective film for semiconductor, and manufacturing method thereof

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