JP3239738B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art To increase the current of a thyristor, it is necessary to lower the on-voltage at an arbitrary recovery current _Irp in order to reduce the loss. I _rp is the maximum current flowing in the reverse direction when switching from the conducting state to the blocking state.
In applications such as power conversion that passes a current of 000 A or more, I _rp
Must be smaller than the rated value. Although there is a trade-off relationship between the on-voltage and I _{rp, under} a constant I _rp condition, the higher the p-based sheet resistance, the lower the on-voltage.
Here, the p base means a p-type diffusion layer region immediately below the n emitter, and is a semiconductor layer that mainly determines the amount of electrons injected from the n emitter. However, when the sheet resistance of the p base is increased, the dv / dt resistance is deteriorated. Prevent false firing, dv / d
As a means for improving the t-resistance, a so-called emitter short-circuit structure in which an n-emitter layer and a p-base layer are connected by electrodes at a number of positions on the main thyristor surface, as described in JP-A-56-140661. well known.

In order to increase the current of the thyristor, it is effective to increase the area of the thyristor. For large area thyristors,
Usually, a structure is adopted in which a relatively small auxiliary thyristor portion is built inside the main thyristor. As the emitter area increases, a larger area of the main thyristor portion must be initially turned on. This requires a large gate current, so a small gate current first ignites the auxiliary thyristor, and the additional current flowing into it becomes the gate current to the main thyristor, so that the main thyristor is initially turned on in a wider area. Can be done.

[0004]

SUMMARY OF THE INVENTION In a thyristor,
If the area resistance of the p-base is increased in order to reduce the on-voltage at a constant I _rp , the dv / dt resistance is reduced and erroneous firing is liable to occur. In the main thyristor portion, the dv / dt resistance can be controlled by the short circuit structure. On the other hand, when the dv / dt resistance is adjusted by short-circuiting in the auxiliary thyristor portion, the gate current required to turn on the thyristor in this portion increases, resulting in a significant decrease in ignition sensitivity. For this reason, it is difficult to improve the dv / dt resistance of the auxiliary thyristor. Therefore, it is difficult to optimize the on-voltage and the dv / dt withstand capability at the same time in the related art in which the sheet resistance is increased.

The present invention has been made in consideration of the above problems, and has as its object to optimize both the ON voltage and the dv / dt resistance of a semiconductor device having a thyristor structure.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
The area resistance of the p-base of the second region having the main thyristor portion is higher than the area resistance of the p-base of the first region having the light receiving portion and the auxiliary thyristor portion.

[0007] Therefore, the main thyristor section can reduce the on-voltage while ensuring the dv / dt resistance by making the short-circuit structure dense.

Further, in the auxiliary thyristor, dv / dt resistance can be secured without deteriorating the firing sensitivity. As described above, it is possible to simultaneously optimize the on-voltage and the dv / dt resistance of the semiconductor device having the thyristor structure.

As a method of manufacturing the semiconductor device of the present invention, the process of controlling the p-base sheet resistance with the p-base width is the easiest. In particular, the semiconductor device of the present invention can be easily manufactured by a process of forming a p-layer by diffusion, forming a step on the substrate surface side of the p-layer by etching or the like, and controlling the thickness of the p-base.

Further, the semiconductor device of the present invention is most easily manufactured by a process of forming a step on the substrate surface by etching, and then diffusing and etching the n layer to separate the n layer such as a main thyristor and an auxiliary thyristor. can do.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings describing the embodiments, components having the same functions are denoted by the same reference numerals.

(Embodiment 1) FIG. 1 is a sectional view showing a main part of a light trigger thyristor structure according to a first embodiment of the present invention. In the semiconductor substrate 10, the ignition thyristor Q _x the center, the auxiliary thyristor part Q _y is located in the immediate. The region where Q _x and Q _y exist is the first region A. A main thyristor portion _Qz exists in a second region B around the periphery.

[0013] n emitter layer 4 of the main thyristor unit Q _z (fourth semiconductor layer) has a deleted region shape that is dimensionally somewhat regularly arranged, p base layer in this deleted part 3 (third semiconductor layer) is exposed to the cathode and is connected to the cathode electrode 7 (main electrode 2). That is, n emitter layer 4 and p base layer 3 are partially short-circuited. Generally, this is referred to as an emitter short-circuit structure 41, and the emitter short-circuit structure 41 causes the dv of the main thyristor portion to be dv.
/ Dt resistance is increased.

Further, all the cathode side of the main thyristor unit Q _z is covered with the main thyristor cathode electrode 7z, and the cathode electrode 7y of the auxiliary thyristor portion Q _y region of the inside is not connected.

In this embodiment, the second region B of the p base layer 3
Is a region higher than that of the first region A. Specifically, 500 to 900Ω in the first region
/ □, and 900 to 2000 Ω / □ in the second region. As a result, the concentration of the p base layer in the second region B is reduced, a low on-state voltage is achieved, and the dv / dt resistance can be maintained. p boundary of the base layer 3 of the first region A low sheet resistivity second region B, and 0.5mm inwardly from the outermost region n emitter of the auxiliary thyristor portion Q _y is present, the main thyristor unit Q _z Exists between the innermost region of the region where the n emitters exist. Within this range, even if the boundary between the first region A and the second region B is changed, the ON voltage and the dv / dt withstand capability are
Neither are affected.

[0016] Figure 16 is revealed by the study of the present inventors, showing a relationship between the ON voltage and the short interval in the main thyristor unit Q _Z. This relationship is a result of studying by changing the sheet resistance of the p base layer of the main thyristor portion, and the recovery current _Irp is fixed. As this figure shows,
When the sheet resistance is in the range of 900 to 2000 Ω / □, the influence of the short-circuit interval on the on-voltage is small, but the sheet resistance has a large effect. In the embodiment of FIG. 1, the p-base sheet resistance of the second region, which is the main thyristor portion, is 900 to 2000.
Since Ω / □ is set, the on-voltage is reduced, and the dv / dt withstand capability can be improved by making the short-circuit interval dense without being affected by the on-voltage.

Further, in this embodiment, since the area resistance of the p base of the first region, which is the auxiliary thyristor portion, is made smaller than that of the second region, the auxiliary thyristor portion does not need to have a short circuit interval. dv / dt resistance can be improved. For this reason, the ignition sensitivity of the auxiliary thyristor does not deteriorate.

As described above, the light trigger thyristor of this embodiment has a low on-voltage characteristic and a high d without impairing the ignition sensitivity.
v / dt resistance. In this embodiment, the main thyristor unit and the auxiliary thyristor unit have d.
v / dt resistance can be adjusted independently. In such a case, the dv / dt resistance of the entire light trigger thyristor is limited by the lower one of the dv / dt resistance of the main thyristor and the auxiliary thyristor. Therefore, in this embodiment,
The p-base sheet resistance of the auxiliary thyristor is set such that the dv / dt resistance of the auxiliary thyristor is substantially equal to the dv / dt resistance of the main thyristor and the auxiliary thyristor.

Next, a method of manufacturing the thyristor of this embodiment will be described.

First, as shown in FIG.
A semiconductor substrate 10 of n-type silicon having a thickness of 1200 μm is prepared.

Next, as shown in FIG.
A silicon oxide film 60 having a thickness of 0.1 to 0.05 .mu.m is formed on the main surface by thermal oxidation. Next, as shown in FIG. 6, using a photoresist mask 70, boron is implanted only in the central portion of one main surface under the conditions of an implantation amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² and an energy of 10 to 200 keV. Ions are implanted. Next, the photoresist mask 70 is removed, and again,
The amount of boron implanted over the entire surface is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm
^-2 , ions are implanted under the condition of energy of 10 to 200 keV. Next, the amount of boron implanted into the other main surface is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² , and the energy is 10 to 20.
Ion implantation is performed under the condition of 0 keV.

Next, activation and stretching diffusion are performed by a heat treatment at 1000 ° C. to 1200 ° C. to form a p emitter layer 2 and a p base layer 3 having a predetermined depth, as shown in FIG.
At this time, the sheet resistance of the first region A of the p base layer 3 is 50
0 to 900Ω / □, and the area resistance of the second region B is 900 to 900Ω / □.
2000Ω / □.

Thereafter, n-type impurity phosphorus is diffused over the entire surfaces of both main surfaces of the semiconductor substrate 10 to form an n + -type diffusion layer. Then, as shown in FIG.
The mold diffusion layer is removed, leaving the n emitter layer 4 only on the cathode surface.

Next, as shown in FIG. 9, the n + type diffusion layer 4 is processed into a predetermined plane pattern to obtain an n emitter layer 4.
Central to the light receiving portion Q _x the auxiliary thyristor Q _y thereabout, a further peripheral portion main thyristor unit Q _z, light receiving portion Q
n emitter of _x and the auxiliary thyristor Q _y and a main thyristor unit Q _z are independent, the light-receiving portion Q _x and the auxiliary thyristor Q _y is p based low sheet resistivity regions (first region A) Exists.

Finally, aluminum is vapor-deposited on both main surfaces of the semiconductor substrate 10, and the aluminum film on the anode surface and the cathode surface is processed into a predetermined pattern using a photoresist, thereby completing a thyristor.

(Embodiment 2) FIG. 2 is a sectional view showing a main part of a light trigger thyristor structure according to a second embodiment of the present invention.

[0027] In the semiconductor substrate 10, the ignition thyristor Q _x the center, the auxiliary thyristor Q _y is located in the immediate. The region where Q _x and Q _y exist is the first region A. A main thyristor portion _Qz exists in a second region B around the periphery. In the semiconductor substrate of this embodiment, since the first region A is more convex than the second region B on the cathode side surface of the semiconductor substrate 10, the area resistance of the first region A is lower than the second region B.
Is lower than the sheet resistance. Therefore, d of the auxiliary thyristor section
The ON voltage can be reduced without deteriorating the v / dt resistance.

Next, a method of manufacturing the thyristor of this embodiment will be described. First, as shown in FIG.
Prepare a semiconductor substrate 10 of n-type silicon having a thickness of 1200 μm in cm.

Next, aluminum, which is a p-type impurity, is
Diffusion is performed by a gas phase diffusion method at 0 ° C. to 1100 ° C. Further, stretching and diffusion are performed at a higher temperature than during the gas phase diffusion, and FIG.
On both sides of the n base layer 1 like p, p emitter layers 2 and p base layers 3 having a predetermined thickness are formed. The sheet resistance values of the p emitter layer 2 and the p base layer 3 are 500 to 900 Ω / □. Next, as shown in FIG. 11, the peripheral portion (second region B) is removed by an etching method, and the area resistance of the p base layer in the peripheral portion (second region B) is set to 900 to 2000 Ω / □.
Thereafter, over the entire surface of both main surfaces of the semiconductor substrate, n
Is diffused to form an n @ + -type diffusion layer.
Then, the n + type diffusion layer on the anode surface is removed, and the n + diffusion layer (4) is left only on the cathode surface as shown in FIG.

Next, as shown in FIG. 13, the n + type diffusion layer (4) is processed into a predetermined pattern to obtain an n emitter layer 4. In the present invention, the outermost portion of the auxiliary thyristor portion Q _y is preferably present in the step portion of the semiconductor substrate 10. However, the auxiliary thyristor Q _y according to the study results of the present invention have not protrude 0.5mm more than the convex portion of the semiconductor substrate. When the protrusion exceeds 0.5 mm, the dv / dt resistance rapidly decreases. As an example of such a study result, FIG. 14 shows the relationship between the protrusion amount X of the auxiliary thyristor unit and the dv / dt resistance.

Finally, aluminum is vapor-deposited on both main surfaces of the semiconductor substrate 10, and the aluminum film on the anode surface and the cathode surface is processed into a predetermined pattern using a photoresist, thereby completing a thyristor. If the outermost portion of the auxiliary thyristor portion is present at the step portion of the semiconductor substrate 10, the processing of the aluminum electrode is easy.

(Embodiment 3) FIG. 3 is a sectional view showing a main part of a light trigger thyristor structure according to a third embodiment of the present invention. Q _x the light receiving portion in the semiconductor substrate 10, Q _y represents an auxiliary thyristor. The region where Q _x and Q _y exist is the first region A. The other part is the main thyristor part _Qz (second region B).

The semiconductor substrate of the present embodiment is characterized in that the diffusion front of the p base layer in the first region A is more convex than the p base layer in the second region B in the substrate. Therefore, the sheet resistance of the first region A is lower than the sheet resistance of the second region B. Therefore, the ON voltage can be reduced without deteriorating the dv / dt resistance of the auxiliary thyristor unit.

In Examples 1 to 3, after forming an n-emitter layer 4 for the purpose of making ohmic contact between the p-layer and the electrode, aluminum as a p-type impurity is vapor-phase diffused to form an anode electrode 8 and a p-emitter layer. Layer or a contact portion between the cathode electrode and the p base layer in some cases. Although the p @ + layer has a very small sheet resistance, it does not significantly affect the dv / dt withstand capability, and the area resistance of the p base layer immediately below the n emitter layer where no p @ + layer exists is d.
v / dt resistance is determined. Therefore, in a thyristor in which a p + layer exists at a contact portion between an electrode and a p-layer, the area resistance of the p-base layer immediately below the n-emitter layer is defined as the area resistance of the p-base layer.

With the structure of the first to third embodiments, the diameter 140
mm, n base width: 960 μm, p emitter width: 70 μm, short circuit interval: 1.0 mm, area resistance of the p base layer in the first region having a diameter of 40 mm is 900Ω / □, and area resistance of the p base layer in the second region is 1500Ω. / □, the breakdown voltage: 6 kV, the on-voltage: 1.7 V (current: 5.5 kV)
A), dv / dt resistance: 3500 V / μs can be realized.

An optical thyristor to which the present invention is applied;
The on-voltage and dv / d when the I _rp is fixed using an optical thyristor having a constant p-based sheet resistance, which is a conventional technique, is used.
FIG. 15 shows the relationship between the dt tolerance. It can be seen that the optical thyristor to which the present invention is applied realizes a high dv / dt withstand voltage at a low ON voltage.

The present invention can be applied not only to a light trigger thyristor but also to an electric gate thyristor. The present invention has the same effect even if the conductivity type of each semiconductor layer is reversed in each of the above embodiments.

[0038]

According to the present invention, it is possible to increase the current of the thyristor without deteriorating the dv / dt resistance.

[Brief description of the drawings]

FIG. 1 is a sectional view of a light trigger thyristor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a light trigger thyristor according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a light trigger thyristor according to a third embodiment of the present invention.

FIG. 4 is a diagram for explaining a method of manufacturing the light trigger thyristor of the first embodiment shown in FIG.

FIG. 5 is a diagram for explaining a method of manufacturing the light trigger thyristor of the first embodiment shown in FIG.

FIG. 6 is a view for explaining a method of manufacturing the light trigger thyristor of the first embodiment shown in FIG.

FIG. 7 is a diagram for explaining a method of manufacturing the light trigger thyristor according to the first embodiment shown in FIG.

FIG. 8 is a diagram for explaining a method of manufacturing the light trigger thyristor according to the first embodiment shown in FIG.

FIG. 9 is a diagram for explaining a method of manufacturing the light trigger thyristor of the first embodiment shown in FIG.

FIG. 10 is a diagram for explaining a method of manufacturing the optical trigger thyristor according to the second embodiment shown in FIG.

FIG. 11 is a view for explaining a method of manufacturing the optical trigger thyristor according to the second embodiment shown in FIG. 2;

FIG. 12 is a diagram for explaining a method of manufacturing the optical trigger thyristor according to the second embodiment shown in FIG.

FIG. 13 is a view for explaining a method of manufacturing the light trigger thyristor according to the second embodiment shown in FIG. 2;

FIG. 14 is a view for explaining a method of manufacturing the optical trigger thyristor according to the second embodiment shown in FIG. 2;

FIG. 15 shows characteristics of the light trigger thyristor of the first embodiment shown in FIG.

FIG. 16 shows a relationship between an on-voltage and a short-circuit interval.

[Explanation of symbols]

1 ... n base layer, 2 ... p emitter layer, 3 ... p base layer,
4 ... n emitter layer, 7 ... cathode electrode, 7y ... auxiliary thyristor cathode electrode, 7z ... main thyristor cathode electrode, 8 ... anode electrode, 10 ... semiconductor substrate, 31 ... p base layer low area resistance part, 32 ... p base Layer high area resistance value, 41: emitter short-circuit structure, 50: high concentration layer, 60:
Oxide film mask, 70 photomask, A first region, B
Second area, Q _x ... firing thyristor section, Q _y ... auxiliary thyristor section, Q _z ... main thyristor section.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Yokota 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Katsumi Ishikawa 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Katsuaki Saito 3-1-1 Kochicho, Hitachi-shi, Ibaraki Pref. Hitachi, Ltd. Hitachi Plant (56) References JP-A-54-46488 (JP, A) JP-A-7-122728 (JP, A) JP-A-63-84067 (JP, A) JP-A-5-299641 (JP, A) JP-A-6-318714 (JP, A) 335861 (JP, A) JP-A-6-169080 (JP, A) JP-A-4-241461 (JP, A) JP-A-58-128765 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/74 H01L 21/332

Claims (4)

(57) [Claims] A first semiconductor layer of one conductivity type; a second semiconductor layer of the other conductivity type adjacent to the first semiconductor layer; a third semiconductor layer of one conductivity type adjacent to the second semiconductor layer; A semiconductor substrate including a third semiconductor layer adjacent to the third semiconductor layer and a semiconductor region including a first region including an auxiliary thyristor portion and a second region including a main thyristor portion; In the device, the first region including the auxiliary thyristor portion is the semiconductor substrate.
And a second region including the main thyristor portion is located around a periphery of the first region.
And the third semiconductor layer in the first region has a sheet resistance of the second semiconductor layer.
Rather lower than the sheet resistance value of the third semiconductor layer in the region, and the center of the first region is a center of said semiconductor substrate, a point
A semiconductor device having an arc thyristor . 2. The semiconductor device according to claim 1, wherein the thickness of the third semiconductor layer in the first region is larger than the thickness of the third semiconductor layer in the second region. 3. The method according to claim 1, wherein an interface between the third semiconductor layer and the fourth semiconductor layer in the first region protrudes from an interface between the third semiconductor layer and the fourth semiconductor layer in the second region. Characteristic semiconductor device. 4. A first step of ion-implanting a first impurity of the other conductive type into a central portion of a main surface on one side of a semiconductor substrate of one conductive type, and after the first step, the one side of the semiconductor base is provided. Main surface of
Ion implantation of a first impurity of the other conductivity type into the entire surface of
Two steps and, after the second step, a main table on the other side of the semiconductor substrate.
Ion-implanting a first impurity of the other conductivity type into the entire surface
A third step, and after the third step, other than the steps from the first step to the third step,
A fourth step of thermally diffusing anisotropy conductive type first impurity, after the fourth step, a fifth step of the entire surface to the second impurity ion implantation of the other conductivity type in both main table surface of the semiconductor substrate A method for manufacturing a semiconductor device having: