JPH10294450A - Gate turn-off thyristor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the minimum gate ignition current by performing ion implantation of an n-type impurity in a p-base surface that is included between the n-type semiconductor region and an n-type emitter region of a mesa part, and forming an n-type inversion layer on the p-base surface by the positive charge of an insulation film. SOLUTION: Normally, a positive charge exists in an oxide film 7, an opposite charge is induced on the surface of a p-type semiconductor region 3 when the p-type semiconductor region 3 makes contact with the oxide film 7, and the surface of the p-type semiconductor region 3 is subjected to acceptor-type impurity ionization. As a result, a depletion layer is formed. By including an n-type inversion layer 6 between the p-type semiconductor region 3 and the oxide film 7, the surface of the n-type inversion layer 6 cannot turn to a depletion layer even if a gate current is allowed to flow on turn-on, thus preventing a surface recombination current from flowing, essentially increasing the ratio of a true gate current that flows into a p base, and reducing the minimum gate ignition current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a gate turn-off thyristor capable of reducing a minimum gate firing current and a method of manufacturing the same.

[0002]

2. Description of the Related Art Various techniques have been proposed to improve the switching performance of a gate turn-off thyristor.

[0003] For example, as a conventional technique for improving the controllable current, a technique described in Japanese Patent Publication No. 6-24243 is known. In this prior art, the cathode region is formed so as to be deeper than the center portion at the edge portion in contact with the etching region, so that the cathode region having a lower impurity concentration is formed at the edge portion than the center portion, and the gate-cathode breakdown voltage is increased. ,
It is said that the controllable current is improved.

Another conventional technique for improving the turn-off performance of a gate turn-off thyristor is disclosed in
The techniques described in JP-A-7-120787 and JP-B-6-69092 are known. In these prior arts, first, a concave portion serving as a gate dug portion is formed in an n-type silicon substrate, and then formed by drive-in diffusion after diffusion of gallium or boron of a p-type impurity, thereby forming the gate dug portion. It is described that a decrease in the impurity concentration of the p base layer can be suppressed, the gate turn-off capability can be maintained, and the current blocking capability can be improved.

[0005]

However, in the prior art, when a gate turn-off thyristor is fired, a forward bias voltage is applied between a gate and a cathode to flow a gate current, but the surface recombination occurs on the p base surface. Since the current flows, the minimum gate firing current increases and its in-plane variation occurs, and the on-voltage increases and the in-plane turn-off performance varies, so that the problem that the maximum controllable current decreases is not considered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate turn-off thyristor and a method for manufacturing the same, which solve the problems of the conventional semiconductor device and the method for manufacturing the same.

Specifically, the object of the present invention is to provide a gate
An object of the present invention is to provide a gate turn-off thyristor capable of reducing a surface recombination current on a p-base surface between cathodes and reducing a minimum gate ignition current, and a method of manufacturing the same.

[0008]

In order to achieve the above object, the present invention has a pair of main surfaces, and an n emitter region, a p base region, an n base region, and a p emitter region are sequentially formed from one of the main surfaces. A mesa-shaped groove is provided so that a pn junction consisting of an n-emitter region and a p-base region is exposed in a predetermined region from one main surface, and a high impurity concentration is formed on the surface of the p-base region at the bottom of the mesa portion. A p + type semiconductor region is formed, a cathode electrode is connected to an exposed surface of the n emitter region, a gate electrode is connected to an exposed surface of the p + type semiconductor region having a high impurity concentration, and an exposed surface of the p emitter region is formed. In a gate turn-off thyristor connected to an anode electrode, an n-type impurity is ion-implanted into a p-base surface interposed between the p + -type semiconductor region and the n-emitter region in the mesa portion. Or by performing a heat treatment after the formation of the mesa portion, outward diffusion of impurities on the surface of the p base region of the mesa portion to lower the impurity concentration from the inside, and the like. An n-type inversion layer is formed on the substrate.

Further, in the reverse voltage-current waveform between the gate and the cathode, at an arbitrary reverse applied voltage lower than the breakdown voltage, the leakage current is increased with respect to the reverse applied voltage as the reverse applied voltage increases. It has a two-stage waveform in which the increasing rate decreases.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of a gate turn-off thyristor (hereinafter abbreviated as GTO) according to the present invention.
It is sectional drawing which shows an Example. In the figure, 1 is an n-type semiconductor region serving as an n-base layer, 2 is a p + -type semiconductor region serving as a p-emitter layer, 3 is a p-type semiconductor region serving as a p-base layer, and 4 is an n-type semiconductor region serving as an n-emitter layer. The + type semiconductor regions 5 and 5 are p + type semiconductor regions for the p type semiconductor region 3 to make the gate electrode 30 in ohmic contact. Reference numeral 6 denotes an n-type inversion layer formed on the p-type semiconductor region between the n + -type semiconductor region 4 and the p + -type semiconductor region 5. Reference numeral 7 denotes an oxide film formed on at least a junction composed of the n + -type semiconductor region 4 and the n-type inversion layer 6, an n-type inversion layer 6, and a junction composed of the n-type inversion layer 6 and the p + -type semiconductor region 5. The oxide film 7 is a silicon dioxide film or a phosphorus glass film formed by thermal oxidation, a silicon dioxide film or a silicon nitride film formed by a CVD method, or a composite film thereof. An anode electrode 20 is ohmically connected to the p @ + -type semiconductor region 2 serving as a p-emitter layer, and the p-type semiconductor region 2 serves as a p-base layer.
A gate electrode 30 is ohmic-connected to the p + -type semiconductor region 5 formed on the type semiconductor region 3, and a cathode electrode 40 is connected to the n + -type semiconductor region 4 serving as an n emitter layer.

Next, the fact that the GTO shown in FIG. 1 is effective in reducing the minimum gate firing current will be described. When an anode voltage is applied such that the anode electrode 20 shown in FIG. 1 is positive and the cathode electrode 40 is negative and a gate current for firing from the gate electrode 30 to the cathode electrode 40 is applied, n Electrons are injected from the + type semiconductor region 4, and the injected electrons pass through the p type semiconductor region 3 and accumulate in the n type semiconductor region 1 adjacent to the p + type semiconductor region 2 of the p emitter layer. Lower. Therefore, the p + -type semiconductor region 2 and the n-type semiconductor region 1 are forward biased, and holes are injected from the p emitter. The injected holes accumulate in the p-type semiconductor region 3 and raise the potential there. Therefore, n
The + type semiconductor region 4 and the p type semiconductor region 3 are forward biased, and electrons are injected from the n + type semiconductor region 4 again. Thus, the n + type semiconductor region 4, the p type semiconductor region 3, and the n
Pnpn comprising a p-type semiconductor region 1 and a p + type semiconductor region 2
Positive feedback is applied to the structure, and the GTO transitions from the blocking state to the conducting state.

[0013] size of the components of the so-called ON state the minimum value of the gate current that can be fired and the minimum gate firing current I _GT, I _GT gate driver circuit this GTO moves in a conductive state, heat It is desirable to be as small as possible from the viewpoint of reduction of loss and the like.

Usually, a positive charge exists in the oxide film 7,
When the p-type semiconductor region 3 and the oxide film 7 are in contact with each other, opposite charges are induced on the surface of the p-type semiconductor region 3, and a depletion layer is formed on the surface of the p-type semiconductor region 3 in which acceptor-type impurities are ionized. . If a depletion layer is formed on the surface of p-type semiconductor region 3, even if a gate current flows, the surface recombination current that recombine in the depletion layer on this surface increases, and the true current flowing in the p base substantially increases. , The ratio of the gate current decreases. Therefore,
When the invalid surface recombination current among the gate currents flowing from the gate electrode 30 increases, there arises a problem that the minimum gate firing current _IGT increases.

If the impurity concentration on the surface of the p-type semiconductor region 3 is increased to reduce the surface recombination current, the breakdown voltage between the gate and the cathode is reduced, and the turn-off performance is reduced.

By interposing the n-type inversion layer 6 according to the present invention between the p-type semiconductor region 3 and the oxide film 7, the surface of the n-type inversion layer 6 is not depleted even when a gate current flows at the time of turn-on. not do so without recombination current flow surface, substantially the proportion of true gate current flowing through the p base is increased, it is possible to reduce the minimum gate firing current I _GT.

FIG. 2 is a cross-sectional view of each of the main steps for manufacturing the gate turn-off thyristor of the present invention shown in FIG. 1. Referring to FIG. 2, the manufacturing method of the first embodiment of the present invention will be described below. Will be described.

First, as shown in (a), FZ (111) is used as a silicon substrate to be an n-type semiconductor region 1, n-type single crystal silicon having a resistivity of 200 to 400 Ωcm, and B ( (Boron) or Ga (gallium) as impurities, and the surface impurity concentration is 5 × 10 ^{17 to} 3 × 10 ¹⁸
/ Cm ³ and a depth of 70 ± 10 μm are formed on the p-type semiconductor region 3. On the other main surface, B (boron) or Ga (gallium) is used as an impurity, and the surface impurity concentration is 1 ×.
10 ¹⁸ / cm ³ or more and depth should be 30 ± 10 μm.
+ Type semiconductor region 2 is formed, and the surface impurity concentration from the surface of p type semiconductor region 3 on one main surface is 5 × 10 ¹⁹ /
An n @ + -type semiconductor region 4 is formed by ion implantation or phosphorus hypochlorite to a depth of 15 ± 5 μm of P (phosphorus) of cm ³ or more. Next, although not shown, a silicon oxide film of about 2 to 3 μm is formed by dry oxidation or wet oxidation, and is etched by about 30 ± 10 μm by wet or dry etching by ordinary photolithography as shown in FIG. Then, a mesa groove is formed so that a pn junction composed of the p-type semiconductor region 3 and the n-type semiconductor region 1 is exposed. Thereafter, as shown in (c), n shown in FIG.
To form the pattern inversion layer 6, P
(Phosphorus) 6a is implanted at a dose of about 1 to 5 × 10 ¹¹ / cm ² . In this embodiment, when P (phosphorus) 6a is dosed, a thermal oxide film is not formed on the surface, but 0.05 to 0.5 mm.
After forming a thermal oxide film of about 5 μm, the above-described ion implantation may be performed.

Next, as shown in (d), annealing is performed at a high temperature to activate the implanted P (phosphorus) 6a. Thereafter, thermal oxidation is performed to form a silicon oxide film 7a of about 1 to 2 μm, and patterning is performed by ordinary photolithography.
A p + -type semiconductor region 5 is formed on the p base surface by ion implantation so that B (boron) has a surface impurity concentration of 5 × 10 ¹⁸ / cm ³ or more.

After that, as shown in FIG.
Is formed, and the oxide film 7 on the surfaces of the p + -type semiconductor region 5 and the n + -type semiconductor region 4 is partially removed by ordinary photolithography as shown in FIG.

Next, the exposed p + type semiconductor region 2, n +
An anode electrode 20, a cathode electrode 40, and a gate electrode 30 are formed on the surfaces of the p-type semiconductor region 4 and p-type semiconductor region 5, respectively (h).

(Embodiment 2) FIG. 3 is a sectional view of each step of another manufacturing method for manufacturing the gate turn-off thyristor of the present invention shown in FIG. 1. Referring to FIG. The manufacturing method of the second embodiment will be described. The main steps of the manufacturing method are the same as those shown in FIG. 2, and here, the description will be made with reference to cross-sectional views showing the main points relating to the present invention. FIG. 3A shows another method for forming the n-type inversion layer 6 shown in FIG. In other words, instead of forming the n-type impurity by the ion implantation method to form the n-type inversion layer 6, a method of utilizing the phenomenon of decreasing the surface impurity concentration due to outward diffusion of the p-type diffusion layer is used. FIG. 3A corresponds to step (c) in FIG. As shown in (a), the p-type semiconductor region 3 and n are etched by about 30 ± 10 μm by wet or dry etching by ordinary photolithography.
After forming a mesa groove so that the pn junction formed of the type semiconductor region 1 is exposed, a heat treatment is performed in an oxygen atmosphere at 1050 to 1150 ° C. for 2 to 10 hours to reduce the concentration of the p base surface impurity exposed by etching. By this heat treatment,
A p-type impurity such as boron or gallium diffuses outward to lower the impurity concentration on the surface, thereby forming the n-type inversion layer 61. However, phosphorus originally doped as an n-type impurity in the silicon substrate is reversed. The pile-up increases the impurity concentration on the surface. Therefore, to form the n-type inversion layer 61, the pile-up of phosphorus doped into the substrate may be used.

Thereafter, a gate turn-off thyristor is manufactured through the same steps as shown in FIGS. 2 (e) to 2 (h). FIG. 3B corresponds to step (h) in FIG.

Next, the operation of each embodiment will be described with reference to FIG. 4 showing an impurity concentration distribution in a cross section. The description of the reference numerals shown in FIGS. 2 and 3 among the reference numerals in FIG. 4 is omitted.

FIG. 4A is a sectional view taken along the line AA 'in FIG.
4 shows an impurity concentration distribution in a portion. As shown in FIG. 4A, in the mesa portion, the p-type semiconductor region 3 serving as a p-base on the surface of the n-type semiconductor region 1 has a maximum impurity concentration at an arbitrary distance from the surface, and the surface according to the present invention has An n-type inversion layer 6 is formed by ion implantation of n-type impurities. When a gate current is applied to the gate electrode 30, holes flow through the internal p-type semiconductor region 3, while electrons injected from the n + -type semiconductor region 4 first flow through the n-type inversion layer 6 on the surface. Since the surface of the inversion layer is not a depletion layer,
No surface recombination current flows. Therefore, it is possible to keep the minimum gate firing current of the GTO small.

FIG. 4B is a sectional view taken along line BB 'in FIG. 3B.
4 shows an impurity concentration distribution in a portion. As shown in FIG. 4B, in the mesa portion, the p-type semiconductor region 3 serving as a p-base on the surface of the n-type semiconductor region 1 shows the maximum impurity concentration at an arbitrary distance from the surface. ), Except that the p-base surface has either outward diffusion or n-type diffusion according to the invention.
By pile-up of the type impurities, the effective p-base surface impurity concentration is reduced to about 1 × 10 ¹⁵ / cm ³ . According to the study results of the present inventors, it is effective to reduce the effective p-base surface impurity concentration to 1 × 10 ¹⁶ / cm ³ or less. In order to facilitate understanding, an energy band structure is shown on the right side of FIG. During normal oxide film 7 is positively charged N _f is ^{5 × 10 10 ~3 × 10 11} / cm 2 exists, which the electrons of opposite polarity is induced in the p-type semiconductor region surface n-type inversion Layer 61 is formed. Note that the n-type inversion layer 61 has a positive charge N _f existing in the oxide film 7.
If the value has a certain value, it is desirable to lower the surface impurity concentration of the p-type semiconductor region 3 as much as possible. In this case as well, when a gate current is applied as described with reference to FIG. 4A, holes flow through the internal p-type semiconductor region 3, while electrons injected from the n + -type semiconductor region 4 first emit n Although it flows through the type inversion layer 61, no surface recombination current flows because the surface of the n-type inversion layer is not a depletion layer. Therefore, GT
It is possible to keep the minimum gate firing current of O small.

FIG. 5 shows a reverse voltage-current waveform between the gate and the cathode of the GTO manufactured by the gate turn-off thyristor and the method of manufacturing the same according to the present invention. A curve A in the figure shows a case where the n-type inversion layer 6 or 61 according to the present invention exists, and a curve C shows a case where the n-type inversion layer 6 or 61 does not exist. In the curve C, in a voltage region where the leak current increases rapidly, that is, a voltage region equal to or lower than the withstand voltage, p
The surface-generated current generated in the depletion layer on the base surface flows, causing a large leak current, and the curve A according to the present invention shows a two-stage waveform where an inflection point appears in a single-waveform at an arbitrary voltage lower than the breakdown voltage. This is, in the following voltage region arbitrary voltage V _p, a neutral state not be n-type inversion layer 6 or 61 according to the present invention becomes a depletion layer, n-type inversion layer in V _p higher voltage region 6 or This is because 61 becomes a depletion layer and a surface-generated current flows. Note that curve A is obtained from curve C
Although the withstand voltage has increased by about 4 V, the surface electric field is reduced because the entire surface of the n-type inversion layer 6 or 61 is a depletion layer. As described above, according to the present invention, not only the minimum gate firing current can be reduced, but also the withstand voltage between the gate and the cathode, which affects the turn-off performance, can be improved.

FIG. 6 shows a forward voltage-current waveform between the gate and the cathode of the GTO manufactured by the gate turn-off thyristor and the method of manufacturing the same according to the present invention. A curve A in the figure shows a case where the n-type inversion layer 6 or 61 according to the present invention exists, and a curve C shows a case where the n-type inversion layer 6 or 61 does not exist. In addition, the voltage dependence of the diffusion current having the slope q / kT and the recombination current having the slope q / 2kT as the forward current component is shown in FIG.
In the curve C, the recombination current is almost dominant in the forward current in a voltage region of 0.6 V or less, but is a surface recombination current in the depletion layer on the p base surface, and the gate flowing when the GTO is turned on is turned on. The current means that a large amount of reactive current that hardly contributes to turn-on flows. On the other hand, in the curve A according to the present invention, the recombination current is dominant in the forward region where the forward current is 0.5 V or less, and the forward current is 0.5 V.
The above shows an ideal waveform in which the diffusion current flowing inside the semiconductor is dominant, and no invalid surface recombination current flows. Therefore, it is possible to reduce the minimum gate firing current of the GTO.

In each of the above embodiments, the gate-cathode withstand voltage shows a value of about 29 V. In the case of 4500 V, 4000 A class or 6000 V, 6000 A class, the minimum gate firing current can be reduced from 8 A in the past to 3 to 4 A. In addition, downsizing and loss reduction of gate drive circuit components such as capacitors and resistors can be achieved.

[0030]

According to the gate turn-off thyristor and the method of manufacturing the same according to the present invention, the minimum gate firing current can be reduced and the loss and size of the gate drive circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first embodiment of a gate turn-off thyristor of the present invention.

FIG. 2 is a manufacturing process diagram of a first embodiment using a gate turn-off thyristor of the present invention.

FIG. 3 is a cross-sectional view of a gate turn-off thyristor according to a second embodiment of the present invention.

FIG. 4 shows impurity concentration distributions in the AA 'part of the first embodiment and the BB' part of the second embodiment by the gate turn-off thyristor of the present invention.

FIG. 5 is a reverse voltage-current waveform between the gate and the cathode of the gate turn-off thyristor of the present invention.

FIG. 6 shows a forward voltage-current waveform between a gate and a cathode of the gate turn-off thyristor of the present invention.

[Explanation of symbols]

1 ... n type semiconductor region, 2,3,5 ... p + type semiconductor region,
4 n + type semiconductor region, 6, 61 n type inversion layer, 7 oxide film, 20 anode electrode, 30 gate electrode, 40
Cathode electrode.

Claims (4)

[Claims] 1. A semiconductor device comprising: a pair of main surfaces;
An emitter region, a p base region, an n base region, and a p emitter region are sequentially laminated, and a mesa-shaped groove is provided in a predetermined region from one main surface so that a pn junction composed of the n emitter region and the p base region is exposed. , P at the bottom of this mesa
A p + type semiconductor region having a high impurity concentration is formed on the surface of the base region, a cathode electrode is connected to an exposed surface of the n emitter region, and a gate electrode is connected to an exposed surface of the p + type semiconductor region having a high impurity concentration. A gate turn-off thyristor having an anode electrode connected to an exposed surface of the p-emitter region, wherein an n-type inversion layer is formed on a surface of a p-base interposed between the p + -type semiconductor region and the n-emitter region of the mesa portion. A gate turn-off thyristor characterized in that: A step of forming a second semiconductor region of a second conductivity type extending inward from one main surface of the semiconductor substrate of the first conductivity type, and a step of forming a second semiconductor region of a second conductivity type extending inward from the other main surface. Forming a third semiconductor region; forming a first conductive type high impurity concentration fourth semiconductor region extending inward from the second semiconductor region surface on one main surface; Etching to form a plurality of isolated fourth semiconductor regions to form a mesa-shaped groove so as to expose a pn junction; and ion implantation or thermal diffusion of impurities of the first conductivity type from one main surface. A step of inverting the surface of the second semiconductor region of the mesa portion to the first conductivity type by at least introducing the semiconductor device into the mesa portion, and forming a fifth impurity of the second conductivity type having a high impurity concentration on the bottom surface of the second semiconductor region at the bottom of the mesa portion. Form semiconductor region and conduct second Forming a mold; forming a junction covering at least a fourth semiconductor region exposed on the surface and the inversion region; and forming an insulating film covering the inversion region and a junction surface including the inversion region and the fifth semiconductor region. Forming first and second main electrodes on the third semiconductor region and the fourth semiconductor region exposed to the outside, and forming a control electrode on the surface of the fifth semiconductor region. Manufacturing method. A step of forming a second semiconductor region of a second conductivity type extending inward from one main surface of the semiconductor substrate of the first conductivity type, and a step of forming a second semiconductor region of a second conductivity type extending inward from the other main surface. Forming a third semiconductor region; forming a first conductive type high impurity concentration fourth semiconductor region extending inward from the second semiconductor region surface on one main surface; Etching to form a plurality of isolated fourth semiconductor regions to form a mesa-shaped groove so as to expose a pn junction; and performing heat treatment to outwardly diffuse impurities on the surface of the second semiconductor region in the mesa portion. Forming a sixth semiconductor region having a lower impurity concentration than the inside by forming a fifth semiconductor region of a second conductivity type having a high impurity concentration on the surface of the second semiconductor region at the bottom of the mesa portion; At least the fourth semiconductor exposed on the surface In the film covering the junction consisting of the body region and the sixth semiconductor region, the sixth semiconductor region and the film covering the junction surface consisting of the sixth semiconductor region and the fifth semiconductor region,
Forming an insulating film having an electric charge of the same polarity as that of the semiconductor region; forming first and second main electrodes on the third and fourth semiconductor regions exposed on the surface; A method of manufacturing a gate turn-off thyristor, comprising a step of forming a control electrode. 4. The method according to claim 1, wherein the reverse voltage-current waveform between the gate and the cathode is such that the reverse current of the leak current increases with the increase of the reverse applied voltage at an arbitrary reverse applied voltage lower than the breakdown voltage. A gate turn-off thyristor having a two-stage waveform in which an increasing ratio with respect to an applied voltage decreases.