JPH03229418A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03229418A JPH03229418A JP2577090A JP2577090A JPH03229418A JP H03229418 A JPH03229418 A JP H03229418A JP 2577090 A JP2577090 A JP 2577090A JP 2577090 A JP2577090 A JP 2577090A JP H03229418 A JPH03229418 A JP H03229418A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- glass
- chips
- glass powder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000011521 glass Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000843 powder Substances 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 9
- 239000012298 atmosphere Substances 0.000 claims abstract description 7
- 239000000203 mixture Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000000725 suspension Substances 0.000 abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 35
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 10
- 238000010304 firing Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001962 electrophoresis Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000010412 perfusion Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、表面保護用バシイペーション膜を有する半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a surface-protecting vacillation film.
従来の技術
高耐圧を有する半導体装置は、従来、化学的腐食法によ
って1つ1つの半導体素子に分割後、pn接合を保護す
るためジャンクション・コーティング・レジンを塗布し
、活性ガス雰囲気中で、ハーメチック(いわゆるキャン
)封止されていた。また最近、CVD法で形成したSi
O2膜、或はZnO系もしくはPbO系被膜、または多
結晶シリコン膜を用いたバシイベーション技術の進歩に
より、樹脂封止された製品が実用化されている。Conventional technology Semiconductor devices with high withstand voltage are conventionally divided into individual semiconductor elements using a chemical corrosion method, then a junction coating resin is applied to protect the pn junction, and hermetic coating is performed in an active gas atmosphere. (so-called can) was sealed. Recently, Si formed by CVD method
Due to advances in vacillation technology using O2 films, ZnO-based or PbO-based films, or polycrystalline silicon films, resin-sealed products have been put into practical use.
発明が解決しようとする課題
しかしながら、ガラス被膜を用いたパシィべーション、
即ちCVD法で形成した5i02被膜では、SiO2膜
中の+イオンを避け、また、膜厚を211m以上で、ガ
ラスクラックの発生を避けるとすると、耐圧は約100
0Vが限界である。また、ZnO系、PbO系なとのガ
ラス粉末と電気泳動法、グレート法を利用して形成する
方法は、高耐圧化は比較的容易であるが、Wi細前加工
適さず、形成させる所望領域上外にもガラス粉末を付着
させてしまい、その結果、電極形成を困難とし、極端な
場合は、性能劣化や信頼低下を招くことになる。一方、
多結晶シリコン膜をパシイヘーション膜として用いた半
導体装置は、逆方向電流が高く、半導体装置の性能及び
信頼性に欠ける。このため、多結晶シリコン膜に酸素を
添加した被膜が実用化され、低い逆方向電流となってい
るが、それても充分ではない。Problems to be Solved by the Invention However, passivation using a glass coating,
In other words, in the 5i02 film formed by the CVD method, if + ions in the SiO2 film are avoided and the film thickness is 211 m or more to avoid glass cracks, the withstand voltage is approximately 100 m.
0V is the limit. In addition, methods of forming using ZnO-based or PbO-based glass powder, electrophoresis method, or grate method are relatively easy to achieve high voltage resistance, but are not suitable for Wi fine processing, and the desired area to be formed is Glass powder is deposited on the top and outside, making it difficult to form electrodes and, in extreme cases, leading to performance deterioration and reduced reliability. on the other hand,
A semiconductor device using a polycrystalline silicon film as a passivation film has a high reverse current, and the semiconductor device lacks performance and reliability. For this reason, a film in which oxygen is added to a polycrystalline silicon film has been put into practical use and has a low reverse current, but even this is not sufficient.
以上説明したように、従来の高耐圧装置のパシィべーシ
ョン法には、+イオンによる耐圧制限、微細加工技術遅
れ、更には逆方向電流の増大なとの3題かある。As explained above, the conventional passivation method for high voltage devices has three problems: voltage resistance limitation due to positive ions, delay in microfabrication technology, and increase in reverse current.
本発明は、この様な従来技術の課題を解決するものであ
って、バンイl\−ンヨン膜中の+イオンの少ないガラ
ス粉末を用いることにより、表面近傍で発生する耐圧低
下を防止し、低逆方向電流を実現させ、容易に高耐圧化
を実現させ、また、感光性のあるホトレジストと前記ガ
ラス粉末を混合させることにより、精密加工を可能にし
、電極形成でのトラアル、即ち順方向電圧の性能低下や
信頼性低下を防止できる半導体装置の製造方法を提供す
ることを目的とする。The present invention solves the problems of the prior art, and by using glass powder with fewer + ions in the vanyon film, it prevents a drop in breakdown voltage that occurs near the surface and reduces the It is possible to realize reverse current, easily realize high breakdown voltage, and by mixing the photosensitive photoresist with the glass powder, it is possible to perform precision processing. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent performance deterioration and reliability deterioration.
課題を解決するための手段
本発明は、ホトレジストにパシィべーション用ガラス粉
末を混合させた感光性液体を半導体基板に薄く塗布する
第1工程と、前記半導体基板に塗布した感光性薄膜をホ
トエツチング技術により部分的に除去する第2工程と、
前記半導体基板の感光性薄膜を750℃〜900℃の温
度で酸化性雰囲気中で熱処理する第3工程とを備えたこ
とを特徴とするものである。Means for Solving the Problems The present invention includes a first step of thinly applying a photosensitive liquid, which is a mixture of photoresist and glass powder for passivation, onto a semiconductor substrate, and a photoetching technique for the photosensitive thin film applied to the semiconductor substrate. A second step of partially removing the
The present invention is characterized by comprising a third step of heat-treating the photosensitive thin film of the semiconductor substrate at a temperature of 750° C. to 900° C. in an oxidizing atmosphere.
作用
木芹明は、前述したように感光性のホトレジストとガラ
ス粉末を混合させた懸濁液をpn接合が露出している半
導体基板に、例えは、スピン塗布することで均一な厚み
の被膜を得た後、ホトエツチングによっ−C電極形成を
行う領域部の被膜を選択的乙こ除去させる。その後、ガ
ラス被膜の存在する半導体基板を、酸化性雰囲気中で焼
成することにより、被膜中に含まれるレジストを燃焼さ
せ膜中から気体として除去すると同時に、ガラス焼結微
密化し、ガラスに一イオンを付加させる。しかる後、焼
成中に形成させる酸化膜をHFを含む水溶液で溶解除去
した後、A1膜を例えは真空蒸着によって形成する。再
びホトエツチングによって、所望の電極となるように、
A1膜を残し、約500℃の温度、不活性ガス雰囲気中
で熱処理することによって、シリコン基板とA1膜をオ
ーミック接触化させることができる。As mentioned above, Seraki Ki is able to spin-coat a suspension of a mixture of photosensitive photoresist and glass powder onto a semiconductor substrate with an exposed pn junction, for example, to form a film with a uniform thickness. After that, the film in the region where the -C electrode is to be formed is selectively removed by photoetching. After that, the semiconductor substrate on which the glass film is present is fired in an oxidizing atmosphere to burn the resist contained in the film and remove it from the film as a gas. Add. Thereafter, the oxide film formed during firing is dissolved and removed with an aqueous solution containing HF, and then the A1 film is formed, for example, by vacuum evaporation. By photo-etching again, make the desired electrode.
By performing heat treatment in an inert gas atmosphere at a temperature of about 500° C. while leaving the A1 film, the silicon substrate and the A1 film can be brought into ohmic contact.
実施例
以下に、本発明の実施例を、図面を参照しながら説明す
る。Examples Examples of the present invention will be described below with reference to the drawings.
第1図は、本発明法によるブレーナ型のpnトランジス
タの製造方法を示す。FIG. 1 shows a method for manufacturing a Brainer type pn transistor according to the method of the present invention.
既に全ての拡散が終了した三重拡散型+1 p n型プ
レーナトランジスタのシリコン基板l(比抵抗40Ωc
mの高抵抗領域を有する)に(a)、市販されている粘
度40cpホトレジスト2(例えは、東京応化社製、商
品名: OMR−87−40cp)logに、これも市
販されているガラス粉末3(例えは米国イノチック社製
、商品名:1P820)を加え、よく増拝させ懸濁液と
した後、回転速度300rpmで30g厚み60μmの
被膜4を形成塗布した(b)。得られた被膜4の厚みは
60μmである。この被膜4を130℃で30分間加熱
させた後(C)、ホトエツチングにより、ヘース5及び
エミッタ6の各々の電極部とするべく領域のガラス被膜
を除去した(d)。しかる後、800℃に加熱された酸
化性雰囲気の焼成部で30分間加熱、その後、弗酸:水
=1: 30の水溶液に10秒間浸漬し、焼成によって
形成されたシリコン基板上の酸化膜を除去した後(e)
、厚み3 It tnのA1膜を真空蒸着法で得た(f
)。その後、ホトエツチングにより、ヘース及びエミッ
タの電極部のみのA1膜を残した後(g)、窒素雰囲気
中で500℃、30分の熱処理を行った((ll)は(
g)の一部拡大図)。その後、コレクタ領域の電極を形
成し、ブイシンクソーにより1つ1つのチップここ分割
後、リードフレームにチップを接着、更に、外部リート
とを200μφのA1線を用いて結線後、樹脂封止した
。The silicon substrate of the triple diffusion type +1p n-type planar transistor (specific resistance 40Ωc) has already been completely diffused.
(a) A commercially available viscosity 40cp photoresist 2 (for example, manufactured by Tokyo Ohka Co., Ltd., trade name: OMR-87-40cp) (having a high resistance region of m), a glass powder also available commercially. 3 (for example, manufactured by Inochik, USA, trade name: 1P820) was added thereto, and the mixture was thoroughly multiplied to form a suspension, and a coating 4 of 30 g and 60 μm thick was formed and applied at a rotation speed of 300 rpm (b). The thickness of the obtained coating 4 is 60 μm. After heating this film 4 at 130° C. for 30 minutes (C), the glass film was removed by photoetching in areas to be used as electrode portions of each of the hese 5 and the emitter 6 (d). After that, the silicon substrate was heated for 30 minutes in a baking section heated to 800°C in an oxidizing atmosphere, and then immersed in an aqueous solution of hydrofluoric acid:water = 1:30 for 10 seconds to remove the oxide film formed on the silicon substrate by baking. After removal (e)
, an A1 film with a thickness of 3 It tn was obtained by vacuum evaporation (f
). Thereafter, after photoetching to leave only the A1 film on the electrode part of the base and emitter (g), heat treatment was performed at 500°C for 30 minutes in a nitrogen atmosphere ((ll) is (
Partially enlarged view of g). Thereafter, electrodes for the collector region were formed, and the chips were separated into individual chips using a buoy sink saw. The chips were bonded to a lead frame, and the chips were connected to an external lead using a 200 μΦ A1 wire, followed by resin sealing.
実施例では、ホトレジスト2をネガタイプで説明したが
、ポジタイプ(例えは、東京応化社製、商品名: 0F
PR−800−30cp)でもよい。In the examples, photoresist 2 was explained as a negative type, but a positive type (for example, manufactured by Tokyo Ohka Co., Ltd., product name: 0F)
PR-800-30cp) may also be used.
また、ホトレジスト2と懸濁されたガラス粉末3として
も、実施例では、Ph系ガラスで説明したが、Zn系ガ
ラス(例えば、日本電気硝子社製、商品名:C;P−0
30)でもよい。更に、所定のパシィべーション用ガラ
ス被膜4を、スピン回転数を変化させることで、厚みを
変化させることもてきる。Further, as the glass powder 3 suspended with the photoresist 2, although Ph-based glass was used in the embodiment, Zn-based glass (for example, manufactured by Nippon Electric Glass Co., Ltd., product name: C; P-0
30) is also acceptable. Furthermore, the thickness of the predetermined passivation glass film 4 can be changed by changing the spin rotation speed.
また、ガラス被膜4の焼成する温度は、被膜4中に含ま
れるレジストの種類と量、またガラスの種類によって変
えることが重要で、焼成時間を長くしたり、また、焼成
温度を高くしたり、史に、レジスト燃焼段階(比較的低
温500〜600℃)とガラスの焼成段階(比較的高温
750〜900°C’> (7) 2段階とすることも
、均一なパシィべーション用ガラス被1Il−7を得ろ
ために必要である。In addition, it is important to change the temperature at which the glass coating 4 is fired depending on the type and amount of resist contained in the coating 4 and the type of glass, such as increasing the firing time or increasing the firing temperature. Historically, a resist burning stage (relatively low temperature of 500 to 600°C) and a glass firing stage (relatively high temperature of 750 to 900°C') have been used in two stages. Necessary to get -7.
レジスト2とガラス粉末3の混合比は、ホトレジストに
対しガラス粉末か0.1〜11の範囲で良好であった。The mixing ratio of the resist 2 and the glass powder 3 was good in the range of 0.1 to 11 of the glass powder to the photoresist.
ガラス粉末がO01以下であると、焼成後のパシイベー
ション用ガラス被膜7中に気泡が多く発生し、半導体装
置の逆方向耐圧が不安定となり、逆に、ガラス粉末が1
1以上であると、スピン塗布後の被膜4がもろく、ホト
エッチ工程において、ガラスが欠落し半導体装置の逆方
向電流を増加させてしまう。また、半導体基板上のパシ
イヘーション用ガラス被膜7の厚さとしては、0.3〜
40μmが良好で、0.3μm以下であると半導体装置
の逆方向耐圧が不安定となり、逆に40um以上である
と、ガラス被膜7にクラックを生しやすくなり、半導体
装置の逆方向耐圧を低下させたり、逆方向電流を増大さ
せたりする。更には、本発明は、メサ型半導体装置のパ
シィべーションに連用できる。If the glass powder is O01 or less, many bubbles will be generated in the passivation glass film 7 after firing, and the reverse withstand voltage of the semiconductor device will become unstable.
If it is 1 or more, the film 4 after spin coating will be brittle, and the glass will be missing in the photoetching process, increasing the reverse current of the semiconductor device. Further, the thickness of the glass coating 7 for opacity on the semiconductor substrate is 0.3~
40 μm is good; if it is 0.3 μm or less, the reverse breakdown voltage of the semiconductor device becomes unstable; on the other hand, if it is 40 μm or more, cracks tend to occur in the glass coating 7, reducing the reverse breakdown voltage of the semiconductor device. or increase the reverse current. Furthermore, the present invention can be applied to passivation of mesa type semiconductor devices.
この様に本発明は、高耐圧の半導体の製造方向に適し、
例えは、従来法1 (熱酸化膜によるパシイヘーション
)、従来法2 (#素を添加した多結晶シリコン膜によ
るパシイヘーション)及び従来法3(ガラス粉末を電気
泳動法で得たバシイベーション膜)と比較して、次の特
徴を持つ。As described above, the present invention is suitable for manufacturing high-voltage semiconductors,
For example, comparisons are made with Conventional Method 1 (passivation using a thermal oxide film), Conventional Method 2 (passivation using a polycrystalline silicon film doped with # elements), and Conventional Method 3 (vacillation film obtained by electrophoresis of glass powder). and has the following characteristics.
従来法1に比べて高耐圧が得やすい。Compared to conventional method 1, it is easier to obtain a high withstand voltage.
従来法2に比へて低逆方向電流である。Compared to conventional method 2, the reverse current is lower.
従来法2及び3に比べて、特殊な装置、複雑な工程管理
を必要としない。Compared to conventional methods 2 and 3, special equipment and complicated process control are not required.
即ち、本発明は、従来法1、従来法2及び従来法3の短
所を解決し、長所のみを具現化させたパシイヘーション
法である。That is, the present invention is a perfusion method that solves the disadvantages of Conventional Method 1, Conventional Method 2, and Conventional Method 3, and embodies only their advantages.
第2図は、本発明の効果を示す一例として、比抵抗40
Ωcmのシリコン基板(有効厚6011m)を用いた時
のコレクターヘース間耐圧を、また、第3図は、逆方向
電流を従来法1〜3ど比較したグラフである。グラフか
ら明らかなように、本発明の方か耐圧力、逆方向電流の
双方で勝っている。FIG. 2 shows a specific resistance of 40% as an example of the effect of the present invention.
FIG. 3 is a graph comparing the breakdown voltage between collector heses when using a silicon substrate of Ωcm (effective thickness 6011 m), and reverse current for conventional methods 1 to 3. As is clear from the graph, the present invention is superior in both pressure resistance and reverse current.
発明の詳細
な説明したように、本発明にかかる半導体装置の製造方
法は、ホトレジストにガラス粉末を混合し、でいるので
、高耐圧で低逆方向電流の微細加工可能な効果を奏する
。As described in detail, the method for manufacturing a semiconductor device according to the present invention mixes glass powder with photoresist, and therefore has the advantage of being able to perform fine processing with high withstand voltage and low reverse current.
第1図は、本発明の一実施例を示す工程図、第2図及び
第3図は、本発明の一実施例の逆方向耐圧及び逆方向電
流を、従来例と比較して示したグラフである。
1・・・既に拡散終了したシリコン基板、2・・・ホト
レジスト、3・・・ガラス粉末、4・・・スピン塗布法
で形成したガラス被膜、5・・・ベース電極用窓、6・
・・エミッタ電極用窓、7・・・燃焼によって得たバシ
イベーション用ガラス被膜、8・・・AI[,9・・・
ヘース電極用A1膜、10・・・エミッタ電極用A1膜
。FIG. 1 is a process diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are graphs showing reverse breakdown voltage and reverse current of an embodiment of the present invention in comparison with a conventional example. It is. DESCRIPTION OF SYMBOLS 1... Silicon substrate which has already been diffused, 2... Photoresist, 3... Glass powder, 4... Glass film formed by spin coating method, 5... Window for base electrode, 6...
... Window for emitter electrode, 7... Glass coating for vacillation obtained by combustion, 8... AI [, 9...
A1 film for heath electrode, 10... A1 film for emitter electrode.
Claims (2)
混合させた感光性液体を半導体基板に薄く塗布する第1
工程と、前記半導体基板に塗布した感光性薄膜をホトエ
ッチング技術により部分的に除去する第2工程と、前記
半導体基板の感光性薄膜を750℃〜900℃の温度で
酸化性雰囲気中で熱処理する第3工程とを備えたことを
特徴とする半導体装置の製造方法。(1) The first step is to apply a thin layer of photosensitive liquid, which is a mixture of photoresist and glass powder for passivation, onto the semiconductor substrate.
a second step of partially removing the photosensitive thin film applied to the semiconductor substrate by photoetching; and heat-treating the photosensitive thin film of the semiconductor substrate in an oxidizing atmosphere at a temperature of 750°C to 900°C. A method for manufacturing a semiconductor device, comprising a third step.
記パシィベーション用ガラスが構成比で0.1〜11で
あり、且つ、前記半導体基板上のパシィべーション用ガ
ラス薄膜が0.3〜40μmであることを特徴とする請
求項1記載の半導体装置の製造方法。(2) In the first step, the passivation glass has a composition ratio of 0.1 to 11 with respect to the photoresist, and the passivation glass thin film on the semiconductor substrate has a thickness of 0.3 to 40 μm. 2. The method of manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2577090A JP2643001B2 (en) | 1990-02-05 | 1990-02-05 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2577090A JP2643001B2 (en) | 1990-02-05 | 1990-02-05 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03229418A true JPH03229418A (en) | 1991-10-11 |
JP2643001B2 JP2643001B2 (en) | 1997-08-20 |
Family
ID=12175081
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JP2577090A Expired - Fee Related JP2643001B2 (en) | 1990-02-05 | 1990-02-05 | Method for manufacturing semiconductor device |
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JP (1) | JP2643001B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114361011A (en) * | 2021-12-15 | 2022-04-15 | 安徽芯旭半导体有限公司 | Photoetching production process of PG (patterned conductor) chip |
-
1990
- 1990-02-05 JP JP2577090A patent/JP2643001B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114361011A (en) * | 2021-12-15 | 2022-04-15 | 安徽芯旭半导体有限公司 | Photoetching production process of PG (patterned conductor) chip |
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JP2643001B2 (en) | 1997-08-20 |
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