JPH0314234A - Titanium silicide wiring structure - Google Patents
Titanium silicide wiring structureInfo
- Publication number
- JPH0314234A JPH0314234A JP15106989A JP15106989A JPH0314234A JP H0314234 A JPH0314234 A JP H0314234A JP 15106989 A JP15106989 A JP 15106989A JP 15106989 A JP15106989 A JP 15106989A JP H0314234 A JPH0314234 A JP H0314234A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- titanium
- titanium silicide
- wiring
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021341 titanium silicide Inorganic materials 0.000 title claims abstract description 41
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010936 titanium Substances 0.000 claims abstract description 9
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims abstract 15
- 239000000203 mixture Substances 0.000 claims abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 2
- 239000011241 protective layer Substances 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims abstract 2
- 239000010703 silicon Substances 0.000 claims abstract 2
- 239000010409 thin film Substances 0.000 claims abstract 2
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 101100313164 Caenorhabditis elegans sea-1 gene Proteins 0.000 description 1
- GNKTZDSRQHMHLZ-UHFFFAOYSA-N [Si].[Si].[Si].[Ti].[Ti].[Ti].[Ti].[Ti] Chemical compound [Si].[Si].[Si].[Ti].[Ti].[Ti].[Ti].[Ti] GNKTZDSRQHMHLZ-UHFFFAOYSA-N 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
この発明は集積回路装置におけるチタンシリ勺イド配線
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a titanium silicate wiring structure in an integrated circuit device.
従来の集積回路装置において、ポリシリコンは例えばＭ
ＯＳ Ｆ Ｅ Ｔ （Ｍｅｔａｌ ０ｘｉｄｅ Ｓｅ
ｍ１ｃｏｎｄｕｃｔｏｒＦｉｅｌｄ Ｅｆｆｅｃｔ Ｔ
ｒａｎｓｉｓｔｏｒ）においてはゲート電極及び配線材
料として、また例えばバイポーラトランジスタにおいて
はエミッタ電極あるいはヘース電極として使用されてき
た。しかしながら、ポリシリコン配線は数１０Ω／口の
比較的高い抵抗値を持ち、集積回路の微細化に伴って電
極及び配線寸法が縮小されるに従って、集積回路の高速
化の妨げとなる。さらに集積回路の微細化に伴い、拡散
層深さを浅くする必要が生ずるが、これに伴い拡散配線
抵抗も増大してしまい、素子の高速化が困難となる。In conventional integrated circuit devices, polysilicon is e.g.
OS FET (Metal Oxide Se
m1conductorField Effect T
It has been used as a gate electrode and wiring material in transistors (transistors), and as an emitter electrode or heath electrode in bipolar transistors, for example. However, polysilicon wiring has a relatively high resistance value of several tens of Ω/hole, and as the dimensions of electrodes and wiring are reduced with the miniaturization of integrated circuits, this becomes an impediment to increasing the speed of integrated circuits. Furthermore, with the miniaturization of integrated circuits, it becomes necessary to reduce the depth of the diffusion layer, but this also increases the resistance of the diffusion wiring, making it difficult to increase the speed of the device.
そこで、ポリシリコン層及び拡散層の抵抗値を下げるこ
との可能な配線構造としてポリシリコン層及び拡散層の
上面を自己整合的にチタンシリサイド（ＴｉＳｉｚ）化
するものがある。Therefore, as a wiring structure capable of lowering the resistance values of the polysilicon layer and the diffusion layer, there is one in which the upper surfaces of the polysilicon layer and the diffusion layer are made of titanium silicide (TiSiz) in a self-aligned manner.
第３図は例えば特開昭５８−１３２９５１号公報に記載
されたこのような従来のチタンシリサイド配線構造を示
す断面図であり、図において、１はＳｔ基板、２はチタ
ンシリサイド層、４は５ｉＯｚ層である。FIG. 3 is a cross-sectional view showing such a conventional titanium silicide wiring structure described in, for example, Japanese Unexamined Patent Publication No. 58-132951. In the figure, 1 is an St substrate, 2 is a titanium silicide layer, and 4 is a 5iOz It is a layer.
第４図（ａ）〜（Ｃ）は第３図に示すチタンシリサイド
配線構造の作製工程を示す図であり、図において５はチ
タン層である。FIGS. 4(a) to 4(C) are diagrams showing the manufacturing process of the titanium silicide wiring structure shown in FIG. 3, and in the figures, 5 is a titanium layer.
次に作製工程について説明する。まず第４図（ａ）に示
すように配線以外の領域にＳｉＯ□膜４が形成されたウ
ェハ上に、スパックにより第４図（ｂ）に示すようにチ
タン層５を形成する。この後６００〜６５０°Ｃの温度
で所定時間熱処理を行なうことにより第４図（Ｃ）に示
すようにチタン層５のうちＳｉ基板１に接する部分、ま
たは図示しないポリシリコン膜に接する部分がシリサイ
ド化されてチタンシリサイド層２となる。この後、シリ
サイド化されていないチタン層を除去することにより第
３図に示す配線構造が得られる。Next, the manufacturing process will be explained. First, as shown in FIG. 4(a), a titanium layer 5 as shown in FIG. 4(b) is formed on a wafer on which a SiO□ film 4 has been formed in areas other than the interconnections by sppacking. After that, by performing heat treatment at a temperature of 600 to 650°C for a predetermined time, as shown in FIG. The titanium silicide layer 2 is formed as a titanium silicide layer 2. Thereafter, by removing the unsilicided titanium layer, the wiring structure shown in FIG. 3 is obtained.
上述の方法によりポリシリコン層及び拡散層の上面に１
Ω／口程度の低抵抗のチタンシリサイド層を容易に形成
することができ、集積回路装置の高速化をはかることが
できる。By the method described above, 1
It is possible to easily form a titanium silicide layer with a low resistance on the order of Ω/mm, and it is possible to increase the speed of integrated circuit devices.
従来のチタンシリサイド配線構造は以上のように構成さ
れており、配線の抵抗を低減することができるが、集積
回路装置の製造工程においては９００〜１０００°Ｃと
いう高温の熱処理を繰り返し行なうことが不可欠であり
、この高温熱処理によりチタンシリサイド配線層におい
てチタン（Ｔ ｉ ）の凝集が見られるなど、熱による
劣化が大きく、工程を経るに従って、抵抗チタンが増大
してしまうという問題点があった。The conventional titanium silicide wiring structure is configured as described above and can reduce the resistance of the wiring, but in the manufacturing process of integrated circuit devices, it is essential to repeatedly perform heat treatment at high temperatures of 900 to 1000°C. This high-temperature heat treatment causes agglomeration of titanium (T i ) in the titanium silicide wiring layer, resulting in significant thermal deterioration, and there is a problem in that the resistance of titanium increases as the process progresses.
この発明は上記のような問題点を解消するためになされ
たもので、チタンシリサイド配線層の耐熱性を向上させ
ることのできるチタンシリサイド配線構造を得ることを
目的とする。The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a titanium silicide wiring structure that can improve the heat resistance of the titanium silicide wiring layer.
この発明に係るチタンシリサイド配線層は、配線の表面
をチタン酸化物、シリコン酸化物あるいはこれらの混合
酸化物で被覆するようにしたものである。In the titanium silicide wiring layer according to the present invention, the surface of the wiring is coated with titanium oxide, silicon oxide, or a mixed oxide thereof.
この発明においては、チタンシリサイド配線表面をチタ
ンの凝集を抑える効果を持つ酸化物で被覆したから、熱
処理によるチタンシリサイド配線の劣化を抑制し、低抵
抗な配線層を安定して得ることができる。In this invention, since the surface of the titanium silicide wiring is coated with an oxide that has the effect of suppressing agglomeration of titanium, deterioration of the titanium silicide wiring due to heat treatment can be suppressed and a low-resistance wiring layer can be stably obtained.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例によるチタンシリサイド配
線構造を示す断面図であり、図において、半導体基板１
上に形成されたチタンシリサイド配線層２の表面に、チ
タン酸化物層３が上記チタンシリサイド層２の表面を覆
うように形成されている。FIG. 1 is a sectional view showing a titanium silicide wiring structure according to an embodiment of the present invention.
A titanium oxide layer 3 is formed on the surface of the titanium silicide wiring layer 2 formed above so as to cover the surface of the titanium silicide layer 2.
ここで、第１図に示したようなチタンシリサイド配線構
造を得るための方法としては、例えば先行技術として示
したチタンシリサイドの製造フローに従って、チタンシ
リサイド配線層を形成した後、８００〜１０００ ”Ｃ
程度の高温の０２雰囲気中で熱処理を行なう方法がある
。この０２雰囲気中での高温熱処理によってチタン酸化
物層３が形成される。Here, as a method for obtaining a titanium silicide wiring structure as shown in FIG. 1, for example, after forming a titanium silicide wiring layer according to the titanium silicide manufacturing flow shown as the prior art,
There is a method of performing heat treatment in an 02 atmosphere at a high temperature of about 100 ml. The titanium oxide layer 3 is formed by this high temperature heat treatment in the 02 atmosphere.
第２図はチタンシリ′す゛イド配線のシー１−抵抗値の
変化を９００°Ｃの熱処理時間に対してプロットしたも
のである。従来例によって作成したチタンシリサイド配
線は９００°ｃ、１．２０分の熱処理の後においては初
期の１０倍の抵抗値を示しており、劣化が著しい。それ
に対して本発明の実施例によるチタンシリサイド配線は
抵抗値の上昇がほとんど認められず、耐熱性は大幅に向
上している。FIG. 2 is a plot of the change in Sea 1 -resistance value of the titanium silicide wire with respect to the heat treatment time at 900°C. After heat treatment at 900° C. for 1.20 minutes, the titanium silicide interconnection fabricated according to the conventional example exhibits a resistance value ten times that of the initial value, showing significant deterioration. In contrast, in the titanium silicide wiring according to the embodiment of the present invention, almost no increase in resistance value was observed, and the heat resistance was significantly improved.
このように本実施例ではチタンシリサイド配線表面をチ
タン酸化物層で被覆したから、このチタン酸化物がチタ
ンシリサイドの熱処理によるチタン凝集を抑え、熱処理
によるチタンシリサイド配線の劣化を抑制し、低抵抗な
配線層を安定して得ることができる。In this example, since the surface of the titanium silicide wiring was covered with a titanium oxide layer, this titanium oxide suppressed the aggregation of titanium caused by the heat treatment of the titanium silicide, suppressed the deterioration of the titanium silicide wiring due to the heat treatment, and resulted in low resistance. A wiring layer can be stably obtained.
なお、上記実施例ではチタンシリサイド配線表面をチタ
ン酸化物で被覆するようにしたものについて述べたが、
シリコン酸化物層、あるいはチタン酸化物とシリコン酸
化物の混合層で被覆するようにしてもよく、上記実施例
と同様の効果を奏する。In addition, in the above embodiment, the surface of the titanium silicide wiring was coated with titanium oxide, but
It may be coated with a silicon oxide layer or a mixed layer of titanium oxide and silicon oxide, and the same effects as in the above embodiments can be obtained.
Ｃ発明の効果〕
以上のように、この発明によればチタンシリサイド配線
構造において、チタンシリサイド層の表面を酸化物層で
覆った構成としたから、配線の耐熱性が向上し、この結
果、集積回路の製造工程中の熱処理による配線抵抗の増
大を抑えることが可能となり、安定した素子特性を容易
に得ることができる効果がある。C Effects of the Invention As described above, according to the present invention, in the titanium silicide wiring structure, the surface of the titanium silicide layer is covered with an oxide layer, so the heat resistance of the wiring is improved, and as a result, the integration It is possible to suppress an increase in wiring resistance due to heat treatment during the circuit manufacturing process, and there is an effect that stable device characteristics can be easily obtained.
第１図はこの発明の一実施例によるチタンシリサイド配
線構造を示す断面図、第２図はこの発明の効果を示すた
めの特性図、第３図は従来のチタンシリサイド配線構造
の断面図、第４図は従来のチタンシリサイド配線構造の
作製工程を示す図である。
１は半導体基板、２ばチタンシリサイド層、３ば酸化物
層、４はＳ ｉＯ２層。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view showing a titanium silicide wiring structure according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the effects of the invention, and FIG. 3 is a sectional view of a conventional titanium silicide wiring structure. FIG. 4 is a diagram showing the manufacturing process of a conventional titanium silicide wiring structure. 1 is a semiconductor substrate, 2 is a titanium silicide layer, 3 is an oxide layer, and 4 is an SiO2 layer. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ン薄膜上にチタンを被着させ、熱処理によりチタンシリ
サイド化した配線層と、 上記シリサイド化工程後の、集積回路装置作製に必要な
熱処理工程前に上記配線層上を覆うように形成されたチ
タン酸化物、シリコン酸化物のいずれか、またはそれら
の混合物からなる保護層とを備えたことを特徴とするチ
タンシリサイド配線構造。(1) A wiring layer in which titanium is deposited on a silicon substrate or polysilicon thin film of an integrated circuit device and titanium silicide is formed by heat treatment; A titanium silicide wiring structure comprising a protective layer made of titanium oxide, silicon oxide, or a mixture thereof formed to cover the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15106989A JPH0314234A (en) | 1989-06-13 | 1989-06-13 | Titanium silicide wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15106989A JPH0314234A (en) | 1989-06-13 | 1989-06-13 | Titanium silicide wiring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0314234A true JPH0314234A (en) | 1991-01-22 |
Family
ID=15510628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15106989A Pending JPH0314234A (en) | 1989-06-13 | 1989-06-13 | Titanium silicide wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0314234A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6500759B1 (en) * | 1998-10-05 | 2002-12-31 | Seiko Epson Corporation | Protective layer having compression stress on titanium layer in method of making a semiconductor device |
-
1989
- 1989-06-13 JP JP15106989A patent/JPH0314234A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6500759B1 (en) * | 1998-10-05 | 2002-12-31 | Seiko Epson Corporation | Protective layer having compression stress on titanium layer in method of making a semiconductor device |
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