JP2643001B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2643001B2
JP2643001B2 JP2577090A JP2577090A JP2643001B2 JP 2643001 B2 JP2643001 B2 JP 2643001B2 JP 2577090 A JP2577090 A JP 2577090A JP 2577090 A JP2577090 A JP 2577090A JP 2643001 B2 JP2643001 B2 JP 2643001B2
Authority
JP
Japan
Prior art keywords
film
glass
passivation
semiconductor device
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2577090A
Other languages
Japanese (ja)
Other versions
JPH03229418A (en
Inventor
和彦 椿
英明 名倉
真覩 横沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2577090A priority Critical patent/JP2643001B2/en
Publication of JPH03229418A publication Critical patent/JPH03229418A/en
Application granted granted Critical
Publication of JP2643001B2 publication Critical patent/JP2643001B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 産業上の利用分野 本発明は、表面保護用パシィベーション膜を有する半
導体装置の製造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device having a passivation film for protecting a surface.

従来の技術 高耐圧を有する半導体装置は、従来、化学的腐食法に
よって1つ1つの半導体素子に分割後、pn接合を保護す
るためジャンクション・コーティング・レンジを塗布
し、活性ガス雰囲気中で、ハーメチック(いわゆるキャ
ン)封止されていた。また最近、CVD法で形成したSiO2
膜、或はZnO系もしくはPbO系被膜、または多結晶シリコ
ン膜を用いたパシィベーション技術の進歩により、樹脂
封止された製品が実用化されている。
2. Description of the Related Art Conventionally, a semiconductor device having a high breakdown voltage is divided into individual semiconductor elements by a chemical corrosion method, and then a junction coating range is applied to protect a pn junction. (So-called can) was sealed. Recently, SiO 2 formed by CVD method
With the progress of passivation technology using films, ZnO-based or PbO-based films, or polycrystalline silicon films, resin-sealed products have been put to practical use.

発明が解決しようとする課題 しかしながら、ガラス被膜を用いたパシィベーショ
ン、即ちCVD法で形成したSiO2被膜では、SiO2膜中の+
イオンを避け、また、膜厚を2μm以上で、ガラスクラ
ックの発生を避けるとすると、耐圧は約1000Vが限界で
ある。また、ZnO系、PbO系などのガラス粉末と電気泳動
法、グレード法を利用して形成する方法は、高耐圧化は
比較的容易であるが、微細加工に適さず、形成させる所
望領域上外にもガラス粉末を付着させてしまい、その結
果、電極形成を困難とし、極端な場合は、性能劣化や信
頼性の低下を招くことになる。一方、多結晶シリコン膜
をパシィベーション膜として用いた半導体装置は、逆方
向電流が高く、半導体装置の性能及び信頼性に欠ける。
このため、多結晶シリコン膜に酸素を添加した被膜が実
用化され、低い逆方向電流となっているが、それでも充
分ではない。
INVENTION Problems however to be Solved, Pashiibeshon using glass coating, i.e. in the SiO 2 film formed by a CVD method, SiO 2 film of the +
If ions are to be avoided, and if the film thickness is 2 μm or more and glass cracks are to be avoided, the withstand voltage is limited to about 1000 V. In addition, a method of forming by using a ZnO-based or PbO-based glass powder and an electrophoresis method or a grade method is relatively easy to achieve a high withstand voltage, but is not suitable for fine processing, and is not suitable for forming over a desired region. Glass powder is also adhered to the electrode, which makes it difficult to form an electrode. In an extreme case, performance degradation and reliability are reduced. On the other hand, a semiconductor device using a polycrystalline silicon film as a passivation film has a high reverse current and lacks the performance and reliability of the semiconductor device.
For this reason, a film obtained by adding oxygen to a polycrystalline silicon film has been put to practical use and has a low reverse current, but it is still insufficient.

以上説明したように、従来の高耐圧装置のパシィベー
ション法には、+イオンによる耐圧制限、微細加工技術
遅れ、更には逆方向電流の増大などの課題がある。
As described above, the passivation method of the conventional high breakdown voltage apparatus has problems such as limitation of breakdown voltage by + ions, delay of fine processing technology, and increase of reverse current.

本発明は、この様な従来技術の課題を解決するもので
あって、パシィベーション膜中の+イオンの少ないガラ
ス粉末を用いることにより、表面近傍で発生する耐圧低
下を防止し、低逆方向電流を実現させ、容易に高耐圧化
を実現させ、また、感光性のあるホストレジストと前記
ガラス粉末を混合させることにより、精密加工を可能に
し、電極形成でのトラブル、即ち順方向電圧の性能低下
や信頼性低下を防止できる半導体装置の製造方法を提供
することを目的とする。
The present invention is to solve such a problem of the prior art, and by using glass powder having a small amount of + ions in the passivation film, it is possible to prevent a decrease in withstand voltage generated near the surface and to reduce the reverse direction. By realizing a current, easily realizing a high withstand voltage, and by mixing a photosensitive host resist and the above-mentioned glass powder, it is possible to perform precision processing, and trouble in electrode formation, that is, performance of a forward voltage. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing a reduction and a reduction in reliability.

課題を解決するための手段 本発明は、ホトレジストにパシィベーション用ガラス
粉末を混合させた感光性液体を半導体基板に薄く塗布す
る第1工程と、前記半導体基板に塗布した感光性薄膜を
ホトエッチング技術により部分的に除去する第2工程
と、前記半導体基板の感光性薄膜を750℃〜900℃の温度
で酸化性雰囲気中で熱処理する第3工程とを備えたこと
を特徴とするものである。
Means for Solving the Problems The present invention comprises a first step of thinly applying a photosensitive liquid obtained by mixing a glass powder for passivation to a photoresist to a semiconductor substrate, and a step of photoetching the photosensitive thin film applied to the semiconductor substrate. A second step of partially removing the semiconductor substrate by a technique; and a third step of heat-treating the photosensitive thin film of the semiconductor substrate at a temperature of 750 ° C. to 900 ° C. in an oxidizing atmosphere. .

作用 本発明は、前述したように感光性のホトレジストとガ
ラス粉末を混合させた懸濁液をpn接合が露出している半
導体基板に、例えば、スピン塗布することで均一な厚み
の被膜を得た後、ホトエッチングによって電極形成を行
う領域部の被膜を選択的に除去させる。その後、ガラス
被膜の存在する半導体基板を、酸化性雰囲気中で焼成す
ることにより、被膜中に含まれるレジストを燃焼させ膜
中から気体として除去すると同時に、ガラス焼結微密化
し、ガラスに−イオンを付加させる。しかる後、焼成中
に形成させる酸化膜をHFを含む水溶液で溶解除去した
後、Al膜を例えば真空蒸着によって形成する。再びホト
エッチングによって、所望の電極となるように、Al膜を
残し、約500℃の温度、不活性ガス雰囲気中で熱処理す
ることによって、シリコン基板とAl膜をオーミック接触
化させることができる。
The present invention provides a coating having a uniform thickness by spin-coating a suspension obtained by mixing a photosensitive photoresist and a glass powder as described above, for example, on a semiconductor substrate on which the pn junction is exposed. Thereafter, the film in the region where the electrode is to be formed is selectively removed by photoetching. Thereafter, the semiconductor substrate on which the glass film is present is baked in an oxidizing atmosphere to burn the resist contained in the film and remove it as a gas from the film. Is added. Thereafter, the oxide film formed during firing is dissolved and removed with an aqueous solution containing HF, and then an Al film is formed by, for example, vacuum evaporation. The silicon film and the Al film can be brought into ohmic contact by photoetching again, leaving the Al film so as to form a desired electrode, and performing heat treatment at about 500 ° C. in an inert gas atmosphere.

実施例 以下に、本発明の実施例を、図面を参照しながら説明
する。
Examples Hereinafter, examples of the present invention will be described with reference to the drawings.

第1図は、本発明法によるプレーナ型のnpnトランジ
スタの製造方法を示す。
FIG. 1 shows a method of manufacturing a planar npn transistor according to the present invention.

既に全ての拡散が終了した三重拡散型npn型プレーナ
トランジスタのシリコン基板1(比抵抗40Ωcmの高抵抗
領域を有する)に(a)、市販されている粘度40cpホト
レジスト2(例えば、東京応化社製、商品名:OMR−87−
40cp)10gに、これも市販されているガラス粉末3(例
えば米国イノテック社製、商品名:IP820)を加え、よく
増拝させ懸濁液とした後、回転速度300rpmで30g厚み60
μmの被膜4を形成塗布した(b)。得られた被膜4の
厚みは60μmである。この被膜4を130℃で30分間加熱
させた後(c)、ホトエッチングにより、ベース5及び
エミッタ6の各々の電極部とするべく領域のガラス被膜
を除去した(d)。しかる後、800℃に加熱された酸化
性雰囲気の焼成部で30分間加熱後、その後、弗酸:水=
1:30の水溶液に10秒間浸漬し、焼成によって形成された
シリコン基板上の酸化膜を除去した後(e)、厚み3μ
mのAl膜を真空蒸着法で得た(f)。その後、ホトエッ
チングにより、ベース及びエミッタの電極部のみAl膜を
残した後(g)、窒素雰囲気中で500℃、30分の熱処理
を行った((h)は(g)の一部拡大図)。その後、コ
レクタ領域の電極を形成し、ダイシングソーにより1つ
1つのチップに分割後、リードフレームにチップを接
着、更に、外部リードとを200μφのAl線を用いて結線
後、樹脂封止した。
On a silicon substrate 1 (having a high resistance region of specific resistance 40 Ωcm) of a triple diffusion type npn type planar transistor in which all diffusion has already been completed (a), a commercially available viscosity 40 cp photoresist 2 (for example, manufactured by Tokyo Ohka Co., Ltd. Product name: OMR-87-
To 40 g) of 10 g, commercially available glass powder 3 (for example, product name: IP820, manufactured by Inotech Co., Ltd., USA) was added to form a suspension.
A coating 4 of μm was formed and applied (b). The thickness of the obtained coating 4 is 60 μm. After the coating 4 was heated at 130 ° C. for 30 minutes (c), the glass coating was removed by photoetching in an area to be used as the respective electrode portions of the base 5 and the emitter 6 (d). Then, after heating for 30 minutes in a firing section in an oxidizing atmosphere heated to 800 ° C., thereafter, hydrofluoric acid: water =
After immersion in an aqueous solution of 1:30 for 10 seconds to remove the oxide film on the silicon substrate formed by firing (e), a thickness of 3 μm was obtained.
m Al film was obtained by a vacuum evaporation method (f). Then, after the Al film was left only on the base and emitter electrodes by photoetching (g), heat treatment was performed at 500 ° C. for 30 minutes in a nitrogen atmosphere ((h) is a partially enlarged view of (g)). ). Thereafter, an electrode in the collector region was formed, the chip was divided into individual chips by a dicing saw, the chip was bonded to a lead frame, and external leads were connected with a 200 μφ Al wire, followed by resin sealing.

実施例では、ホトレジスト2をネガタイプで説明した
が、ホジタイプ(例えば、東京応化社製、商品名:OFPR
−800−30cp)でもよい。また、ホトレジスト2と懸濁
されたガラス粉末3としても、実施例では、Pb系ガラス
で説明したが、Zn系ガラス(例えば、日本電気硝子社
製、商品名:OP−030)でもよい。更に、所定のパシィベ
ーション用ガラス被膜4を、スピン回転数を変化させる
ことで、厚みを変化させることもできる。
In the embodiment, the photoresist 2 is described as a negative type, but a photoresist type (for example, a product name: OFPR manufactured by Tokyo Ohkasha Co., Ltd.)
−800-30 cp). Further, as the glass powder 3 suspended with the photoresist 2, a Pb-based glass has been described in the embodiment, but a Zn-based glass (for example, Nippon Electric Glass Co., Ltd., trade name: OP-030) may be used. Further, the thickness of the predetermined passivation glass coating 4 can be changed by changing the spin rotation speed.

また、ガラス被膜4の焼成する温度は、被膜4中に含
まれるレジストの種類と量、またガラスの種類によって
変えることが重要で、焼成時間を長くしたり、また、焼
成温度を高くしたり、更に、レジスト焼成段階(比較的
低温500〜600℃)とガラスの焼成段階(比較的高温750
〜900℃)の2段階とすることも、均一なパシィベーシ
ョン用ガラス被膜7を得るために必要である。
Further, it is important that the temperature at which the glass film 4 is fired is changed depending on the type and amount of the resist contained in the film 4 and the type of the glass, so that the firing time is lengthened, the firing temperature is increased, Further, a resist baking step (relatively low temperature of 500 to 600 ° C.) and a glass baking step (relatively high temperature of 750 ° C.)
(To 900 ° C.) is also necessary to obtain a uniform passivation glass coating 7.

レジスト2とガラス粉末3の混合比は、ホトレジスト
に対しガラス粉末が0.1〜11の範囲で良好であった。ガ
ラス粉末が0.1以下であると、焼成後のパシィベーショ
ン用ガラス被膜7中に気泡が多く発生し、半導体装置の
逆方向耐圧が不安定となり、逆に、ガラス粉末が11以上
であると、スピン塗布後の被膜4がもろく、ホトエッチ
工程において、ガラスが欠落し半導体装置の逆方向電流
を増加させてしまう。また、半導体基板上のパシィベー
ション用ガラス被膜7の厚さとしては、0.3〜40μmが
良好で、0.3μm以下であると半導体装置の逆方向耐圧
が不安定となり、逆に40μm以上であると、ガラス被膜
7にクラックを生じやすくなり、半導体装置の逆方向耐
圧を低下させたり、逆方向電流を増大させたりする。更
には、本発明は、メサ型半導体装置のパシィベーション
に適用できる。
The mixing ratio of the resist 2 to the glass powder 3 was good when the glass powder was 0.1 to 11 with respect to the photoresist. If the glass powder is 0.1 or less, many bubbles are generated in the passivation glass coating 7 after firing, and the reverse breakdown voltage of the semiconductor device becomes unstable. Conversely, if the glass powder is 11 or more, The coating 4 after the spin coating is brittle, and the glass is lost in the photoetching step, thereby increasing the reverse current of the semiconductor device. Further, the thickness of the passivation glass coating 7 on the semiconductor substrate is preferably 0.3 to 40 μm, and if it is 0.3 μm or less, the reverse breakdown voltage of the semiconductor device becomes unstable, and if it is 40 μm or more. In addition, cracks are likely to occur in the glass coating 7, which lowers the reverse breakdown voltage of the semiconductor device and increases the reverse current. Further, the present invention can be applied to passivation of a mesa semiconductor device.

この様に本発明は、高耐圧の半導体の製造方向に適
し、例えば、従来法1(熱酸化膜によるパシィベーショ
ン)、従来法2(酸素を添加した多結晶シリコン膜によ
るパシィベーション)及び従来法3(ガラス粉末を電気
泳動法で得たパシィベーション膜)と比較して、次の特
徴を持つ。
As described above, the present invention is suitable for the manufacturing direction of a semiconductor having a high breakdown voltage, and includes, for example, the conventional method 1 (passivation using a thermal oxide film), the conventional method 2 (passivation using an oxygen-added polycrystalline silicon film), and Compared with the conventional method 3 (a passivation film obtained by electrophoresis of glass powder), it has the following features.

従来法1に比べて高耐圧が得やすい。 High withstand voltage is easily obtained as compared with the conventional method 1.

従来法2に比べて低逆方向電流である。 The reverse current is lower than that of the conventional method 2.

従来法2及び3に比べて、特殊な装置、複雑な工程管
理を必要としない。
Compared with the conventional methods 2 and 3, a special device and complicated process control are not required.

即ち、本発明は、従来法1、従来法2及び従来法3の
短所を解決し、長所のみを具現化させたパシィベーショ
ン法である。
That is, the present invention is a passivation method that solves the disadvantages of the conventional method 1, the conventional method 2, and the conventional method 3 and realizes only the advantages.

第2図は、本発明の効果を示す一例として、比抵抗40
Ωcmのシリコン基板(有効厚60μm)を用いた時のコレ
クタ−ベース間耐圧を、また、第3図は、逆方向電流を
従来法1〜3と比較したグラフである。グラフから明ら
かなように、本発明の方が耐圧力、逆方向電流の双方で
勝っている。
FIG. 2 is a graph showing an example of the effect of the present invention.
FIG. 3 is a graph comparing the withstand voltage between the collector and the base when a silicon substrate of Ωcm (effective thickness 60 μm) is used, and FIG. As is clear from the graph, the present invention is superior in both the withstand pressure and the reverse current.

発明の効果 以上説明したように、本発明にかかる半導体装置の製
造方法は、ホトレジストにガラス粉末を混合しているの
で、高耐圧で低逆方向電流の微細加工可能な効果を奏す
る。
Effect of the Invention As described above, the method of manufacturing a semiconductor device according to the present invention has an effect of enabling fine processing with a high withstand voltage and a low reverse current, since glass powder is mixed with the photoresist.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、本発明の一実施例を示す工程図、第2図及び
第3図は、本発明の一実施例の逆方向耐圧及び逆方向電
流を、従来例と比較して示したグラフである。 1……既に拡散終了したシリコン基板、2……ホトレジ
スト、3……ガラス粉末、4……スピン塗布法で形成し
たガラス被膜、5……ベース電極用窓、6……エミッタ
電極用窓、7……燃焼によって得たパシィベーション用
ガラス被膜、8……Al膜、9……ベース電極用Al膜、10
……エミッタ電極用Al膜。
FIG. 1 is a process chart showing one embodiment of the present invention, and FIGS. 2 and 3 are graphs showing the reverse breakdown voltage and the reverse current of one embodiment of the present invention in comparison with the conventional example. It is. Reference Signs List 1 silicon substrate already diffused 2 photoresist photoresist 3 glass powder 4 glass coating formed by spin coating method 5 base electrode window 6 emitter electrode window 7 ...... Glass film for passivation obtained by combustion, 8 ... Al film, 9 ... Al film for base electrode, 10
..... Al film for emitter electrode.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭50−104572(JP,A) 特開 平1−187932(JP,A) 特開 昭56−27936(JP,A) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-50-104572 (JP, A) JP-A-1-187932 (JP, A) JP-A-56-27936 (JP, A)

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ホトレジストにパシィベーション用ガラス
粉末を混合させた感光性液体を半導体基板に薄く塗布す
る第1工程と、前記半導体基板に塗布した感光性薄膜を
ホトエッチング技術により部分的に除去する第2工程
と、前記半導体基板の感光性薄膜を750℃〜900℃の温度
で酸化性雰囲気中で熱処理する第3工程とを備えたこと
を特徴とする半導体装置の製造方法。
1. A first step of thinly applying a photosensitive liquid in which a glass powder for passivation is mixed to a photoresist to a semiconductor substrate, and partially removing the photosensitive thin film applied to the semiconductor substrate by a photoetching technique. And a third step of performing a heat treatment on the photosensitive thin film of the semiconductor substrate at a temperature of 750 ° C. to 900 ° C. in an oxidizing atmosphere.
【請求項2】第1工程において、前記ホトレジストに対
し、前記パシィベーション用ガラスが構成比で0.1〜11
であり、且つ、前記半導体基板上のパシィベーション用
ガラス薄膜が0.3〜40μmであることを特徴とする請求
項1記載の半導体装置の製造方法。
2. In the first step, the passivation glass is contained in a composition ratio of 0.1 to 11 with respect to the photoresist.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the passivation glass thin film on the semiconductor substrate has a thickness of 0.3 to 40 [mu] m.
JP2577090A 1990-02-05 1990-02-05 Method for manufacturing semiconductor device Expired - Fee Related JP2643001B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2577090A JP2643001B2 (en) 1990-02-05 1990-02-05 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2577090A JP2643001B2 (en) 1990-02-05 1990-02-05 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH03229418A JPH03229418A (en) 1991-10-11
JP2643001B2 true JP2643001B2 (en) 1997-08-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2577090A Expired - Fee Related JP2643001B2 (en) 1990-02-05 1990-02-05 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2643001B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114361011B (en) * 2021-12-15 2022-08-19 安徽芯旭半导体有限公司 Photoetching production process of PG (patterned conductor) chip

Also Published As

Publication number Publication date
JPH03229418A (en) 1991-10-11

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