JPS59129431A - Manufacture of semiconductor device protected by glass film - Google Patents
Manufacture of semiconductor device protected by glass filmInfo
- Publication number
- JPS59129431A JPS59129431A JP58004342A JP434283A JPS59129431A JP S59129431 A JPS59129431 A JP S59129431A JP 58004342 A JP58004342 A JP 58004342A JP 434283 A JP434283 A JP 434283A JP S59129431 A JPS59129431 A JP S59129431A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- film
- oxide film
- semiconductor device
- acid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製法に関するもので、特にパッ
シベーション膜にガラス材を使用するトランジスタ、サ
イリスタ、IC等の半導体装置の製法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device such as a transistor, a thyristor, or an IC using a glass material for a passivation film.
鉛ガラスまたは亜鉛ガラス等の低融点ガラスを半導体装
置に被着してパッシベーション膜として用いる場合、そ
の作製方法としては電気泳動法等種々の方法があるが、
フィールド酸化膜をフォトエツチング法によシ選択的に
窒を開け、ガラスを選択的に窒部分に被着させるときフ
ィールド酸化膜上にも若干のガラス微粒子が付着する。When a low-melting glass such as lead glass or zinc glass is used as a passivation film by depositing it on a semiconductor device, there are various methods for manufacturing it, such as electrophoresis.
When the field oxide film is selectively opened with nitrogen by photoetching and glass is selectively deposited on the nitrogen portion, some glass particles are also deposited on the field oxide film.
との不要なガラス粒子のため電極用室形成の際にエツチ
ングの精度が悪くなることがあり、特にトランジスタ、
IOなど微細パターンを形成する際には障害と外ってい
る。Etching accuracy may deteriorate when forming electrode chambers due to unnecessary glass particles, especially for transistors,
This is considered an obstacle when forming fine patterns such as IO.
本発明の目的は、パッシベーションガラス膜を形成した
あと酸化膜上に残るガラス微粒子を除去し、微細な電極
コンタクト室を形成することを可能にした半導体装置の
新規な製法を提供することにある。An object of the present invention is to provide a new method for manufacturing a semiconductor device that makes it possible to remove glass particles remaining on an oxide film after forming a passivation glass film and form a fine electrode contact chamber.
このような目的を達成するために本発明ではPN接合を
1つ以上有し全面にフィールド酸化膜を持つ半導体基体
上にシリコン窒化膜(SigN+)または多結晶シリコ
ン等の弗酸系の酸に反応しない膜を形成する工程と、さ
らにその上に弗酸系の酸に比較的溶解しやすいOVD法
によるシリコン酸化膜等を形成する工程と、前記シリコ
ン基体上の重畳膜の一部をフォトエツチング法により窓
を開はシリコン表面を露出させ電気泳動法等によりガラ
スを被着し熱処理を行う工程と、ガラス保護のためにO
VD酸化膜を全面に形成する工程と、微細パターン形成
部分に付着している。不要なガラス微粒子をフォトエツ
チング法によりOVD酸化膜と共に弗酸系のエツチング
液で窒化膜または多結晶シリコン層の上までエツチング
剥離し微細パターン形成部分には熱酸化膜および窒化膜
または多結晶シリコンの重畳した薄い膜を残す形にする
工程と、電極コンタクト窓を形成し全面に電極金属を被
膜しフォトエツチングにより微細電極パターンを形成す
る工程とからなることを特徴とする半導体装置の製造方
法とするものである。In order to achieve such an object, in the present invention, a silicon nitride film (SigN+) or polycrystalline silicon, etc., is reacted with hydrofluoric acid on a semiconductor substrate having one or more PN junctions and a field oxide film on the entire surface. a step of forming a silicon oxide film, etc., by an OVD method, which is relatively easily soluble in hydrofluoric acid, on the silicon oxide film, and a photoetching method of a part of the superimposed film on the silicon substrate. To open the window, the silicon surface is exposed, glass is applied by electrophoresis, heat treatment is performed, and O2 is applied to protect the glass.
In the process of forming a VD oxide film on the entire surface, it is attached to the fine pattern forming part. Unnecessary glass particles are removed by photo-etching together with the OVD oxide film using a hydrofluoric acid-based etching solution to the top of the nitride film or polycrystalline silicon layer, and a thermal oxide film and a nitride film or polycrystalline silicon layer are applied to the fine pattern formation area. A method for manufacturing a semiconductor device, comprising a step of leaving a superimposed thin film, and a step of forming an electrode contact window, coating the entire surface with electrode metal, and forming a fine electrode pattern by photo-etching. It is something.
以下本発明の具体的実施例としてNPN)ランジスタの
製法を図を参照しながら詳述する。なお本発明はこの他
にパッシベーションガラス戻を使用するトランジスタ、
サイリスタ、IO等にも適用できるものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing an NPN transistor as a specific embodiment of the present invention will be described below in detail with reference to the drawings. In addition, the present invention also relates to transistors using passivation glass backing,
It can also be applied to thyristors, IOs, etc.
第1図ニガラスパッシベーションをする素子の基体とな
るトランジスタの概略断面は第1図のような構造になっ
ている。NN+型シリコンウェハ1゜2に選択的に不純
物を拡散しペースとまる2層3とエミッタとなるN+層
4を形成したものであり表面はシリコン熱酸化膜5でお
おわれている。FIG. 1 A schematic cross-section of a transistor, which serves as the base of an element subjected to Niglass passivation, has a structure as shown in FIG. An NN+ type silicon wafer 1.degree. 2 has impurities selectively diffused therein to form two layers 3 to serve as a paste and an N+ layer 4 to serve as an emitter, and the surface is covered with a silicon thermal oxide film 5.
第2図:酸化膜5の上にOVD法等によりシリコン窒化
膜(81fiN4)6.を300〜500 ′7Lまた
は多結晶シリコン6を数千X形成しさらKその上にOV
D法によりシリコン酸化膜7を5oooX程度形成する
。次にフォトエツチング法によりガラス膜を形成する部
分の酸化膜および窒化膜または多結晶シリコンを除去し
さらにシリコンをエツチングし溝8を形成す石。FIG. 2: A silicon nitride film (81fiN4) 6. is formed on the oxide film 5 by OVD method or the like. 300~500'7L or several thousand x polycrystalline silicon 6 and then OV on top of it.
A silicon oxide film 7 having a thickness of about 500X is formed by method D. Next, the oxide film, nitride film, or polycrystalline silicon in the portion where the glass film will be formed is removed by photo-etching, and the silicon is further etched to form grooves 8.
第3図:電気泳動法により溝部8に鉛ガラスまたは亜鉛
ガラスを付着させ熱処理を行いガラス層9とする。この
ときガラスは溝部8のみでなく酸化膜7の上にもガラス
微粒子(1〜5μ径)10として付着している。この後
さらに全面にOVD法によりシリコン酸化膜11を70
00X程度形成する。これは後の工程でガラスを酸から
保護するためである。FIG. 3: Lead glass or zinc glass is deposited in the groove 8 by electrophoresis and heat treated to form a glass layer 9. At this time, the glass adheres not only to the groove portion 8 but also to the oxide film 7 as fine glass particles (1 to 5 μm in diameter) 10 . After this, a silicon oxide film 11 is further deposited over the entire surface by OVD method.
Form about 00X. This is to protect the glass from acids in later steps.
第4図:フォトエツチング法によシミ極コンタクト室と
なる微細パターン部分の0V7)酸化膜7゜11ととも
にガラス微粒子10を弗酸系の酸によりエツチング除去
し窓12を開ける。窓部分の表面は窒化膜または多結晶
シリコン6が露出している。FIG. 4: Stain by photo-etching method. Glass particles 10 are etched away together with 0V7) oxide film 7°11 in the fine pattern portion which will become the electrode contact chamber, using hydrofluoric acid, and window 12 is opened. The nitride film or polycrystalline silicon 6 is exposed on the surface of the window portion.
第5図:電極コンタクト窓をフォトエツチング法により
形成しこの後電極と彦るアルミニウムを蒸着法によって
全面に形成し、さらにフォトエツチング法を用いて電極
の微細パターン13を形成する。とのようにして表面の
電極を形成したのち裏面のコレクタ電極を形成し、分割
してトランジスタペレットを得る。FIG. 5: An electrode contact window is formed by photo-etching, and then aluminum, which will serve as an electrode, is formed on the entire surface by vapor deposition, and then a fine pattern 13 of the electrode is formed by photo-etching. After forming an electrode on the front surface, a collector electrode on the back surface is formed, and the transistor pellets are obtained by dividing.
上述したような製法をとることによりガラス微粒子のた
めにエツチング液等かにじむととなく精5一
度の良い微細パターンを得ることができガラスパッジベ
ージロンによる信頼性の高い、高性能の素子ができるよ
うになる。By using the above-mentioned manufacturing method, it is possible to obtain a fine pattern with a fineness of 5 degrees without leaking the etching liquid due to the glass particles, and it is possible to obtain a highly reliable and high-performance device using glass padding. It becomes like this.
第1図乃至第5図は本発明の一実施例を示す工程順の断
面図、である。
なお図において、1〜2・・・・・・NN+型シリコン
ウェハ、3・・・・・・P型ベース層、4・・・・・・
N+型エミッタ層、5・・・・・・フィールド熱酸化シ
リコン膜、6°旧°。
シリコン窒化膜または多結晶シリコン層、7・・・・・
・OVDシリコン酸化膜層、8・・・・・・ガラス被膜
溝部、9・・・・・・低融点ガラス膜、10・・・・・
・残留ガラス微粒子、11・・・・・・OVDシリコン
酸化膜層、12・・・・・・ガラス粒子除去室部、13
・・・・・・アルミニウム電標、である。
6−1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of steps. In the figure, 1 to 2...NN+ type silicon wafer, 3...P type base layer, 4...
N+ type emitter layer, 5...Field thermal oxidation silicon film, 6° old. Silicon nitride film or polycrystalline silicon layer, 7...
・OVD silicon oxide film layer, 8...Glass coating groove, 9...Low melting point glass film, 10...
・Residual glass particles, 11...OVD silicon oxide film layer, 12...Glass particle removal chamber section, 13
・・・・・・Aluminum electric sign. 6-
Claims (1)
の製造方法に於いて、ガラス膜形成の前に酸化膜上に弗
酸系の酸に対して反応しない膜を形成する工程と、さら
にその上に低温で形成するOVDシリコン酸化酸化形成
し、前記ガラス膜被着後該OVDシリコン酸化膜上に付
着したガラス微粒子を該酸化膜と共に弗酸系の酸で除去
する工程とを含むことを特徴とする半導体装置の製造方
法。In a method for manufacturing a semiconductor device in which the surface of an exposed portion of a PN junction is protected with glass, there is a step of forming a film that does not react with hydrofluoric acid on an oxide film before forming a glass film, and then OVD silicon oxide film is formed at a low temperature, and after the glass film is deposited, the glass particles adhering to the OVD silicon oxide film are removed together with the oxide film using hydrofluoric acid. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58004342A JPS59129431A (en) | 1983-01-14 | 1983-01-14 | Manufacture of semiconductor device protected by glass film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58004342A JPS59129431A (en) | 1983-01-14 | 1983-01-14 | Manufacture of semiconductor device protected by glass film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59129431A true JPS59129431A (en) | 1984-07-25 |
Family
ID=11581756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58004342A Pending JPS59129431A (en) | 1983-01-14 | 1983-01-14 | Manufacture of semiconductor device protected by glass film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59129431A (en) |
-
1983
- 1983-01-14 JP JP58004342A patent/JPS59129431A/en active Pending
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