JPS6084821A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6084821A JPS6084821A JP19274983A JP19274983A JPS6084821A JP S6084821 A JPS6084821 A JP S6084821A JP 19274983 A JP19274983 A JP 19274983A JP 19274983 A JP19274983 A JP 19274983A JP S6084821 A JPS6084821 A JP S6084821A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film
- wafer
- nitride film
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置の製造方法に係り、特に半導体装置
のウェハの裏面をミラーポリッシュする際に使用する半
導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device used when mirror polishing the back surface of a wafer of a semiconductor device.
（ロ）従来技術
例えば圧力センサを製造する場合、半導体装置のウェハ
の裏面に前記圧力センサを形成するための孔あけ加工を
するが、そのため半導体装置のウェハ裏面をまえもって
ミラーポリッシュしておくことがある。(b) Prior art For example, when manufacturing a pressure sensor, holes are formed on the back side of a semiconductor device wafer to form the pressure sensor. For this purpose, it is necessary to mirror-polish the back side of the semiconductor device wafer in advance. be.
かかるミラーポリッシュの工程では半導体装置を保護す
るため、その表面に保護用の膜を被覆する必要があり、
その膜として従来はワックスやテープに匹敵する高粘度
のレジスト膜が使用されている。In such a mirror polishing process, in order to protect the semiconductor device, it is necessary to coat the surface with a protective film.
Conventionally, a resist film with a high viscosity comparable to wax or tape has been used as the film.
しかし、上記の方法では、レジスト膜の周辺部分が剥離
したり、スクラッチ等により傷が発生ずることがあり、
その鼾通して種々の汚染源が半導体装置の中心部まで浸
透する結果、充分にはウェハの保護が出来ないという欠
点があった。However, with the above method, the peripheral portion of the resist film may peel off or damage may occur due to scratches, etc.
As a result of the snoring, various sources of contamination penetrate into the center of the semiconductor device, resulting in the disadvantage that the wafer cannot be sufficiently protected.
また、ＣＶＤでもってｐｓｃ股を形成する方法もあるが
、このＰＳＧ膜はドライまたはウェットエツチングする
場合、その条件ぎめが難しく場合によっては下地の酸化
シリコン膜までエツチングしてしまう虞があった。There is also a method of forming a psc layer by CVD, but when dry or wet etching is performed on this PSG film, it is difficult to set the conditions, and in some cases, there is a risk that the underlying silicon oxide film may be etched.
（ハ）目的
本発明に係る半導体装置の製造方法はミラーポリッシュ
の際にその表面を充分に保護しうる保護膜を提供するこ
とを目的としている。(c) Objective The method of manufacturing a semiconductor device according to the present invention aims to provide a protective film that can sufficiently protect the surface during mirror polishing.
（ニ）構成
本発明は半導体装置の表面をプラズマＣＶＤでもってシ
リ３コンナイトライド膜を被覆する工程と、前記シリコ
ンナイトライド膜の上にレジスト膜を被覆する工程と、
前記工程の後半導体装置のウェハの裏面をミラーポリッ
シュする工程と、前記ミラーポリッシュの後前記レジス
ト膜とシリ３コンナイトライド膜を除去する工程とを含
むことを特徴とする半導体装置の製造方法である。(d) Structure The present invention includes a step of coating the surface of a semiconductor device with a silicon nitride film by plasma CVD, and a step of coating a resist film on the silicon nitride film.
A method for manufacturing a semiconductor device, comprising the steps of mirror polishing the back side of the wafer of the semiconductor device after the step, and removing the resist film and the silicon nitride film after the mirror polishing. be.
（ポ）実施例
第１図はバイポーラトランジスタについて、本発明の製
造方法を通用するときの半導体装置の断面図をしめす。(P) Embodiment FIG. 1 shows a sectional view of a semiconductor device when the manufacturing method of the present invention is applied to a bipolar transistor.
ｌはポロンをドープしたＰ型のシリコン基板であるウェ
ハ、２は砒素またはアンチモンを熱拡散させて形成した
Ｎ型の埋込層、３はＮ型のエビタキシャｌし層、４はＰ
Ｉｉ！、５はＮ＋１優、６はシリコン酸化膜１輔であり
、７．８．９、はそれぞれアルミニュウム電極でコンタ
クトしたベース、エミッタおよびコレクタである。1 is a wafer which is a P-type silicon substrate doped with poron, 2 is an N-type buried layer formed by thermally diffusing arsenic or antimony, 3 is an N-type epitaxial layer, and 4 is a P-type silicon substrate.
Ii! , 5 is an N+1 layer, 6 is a silicon oxide film, and 7, 8, and 9 are a base, an emitter, and a collector, which are contacted with aluminum electrodes, respectively.
そして、１０は前記半導体装置の表面に被膜したシリコ
ンナイトライドの股、１１は前記シリコンナイトライド
膜の上にコートしたレジスト膜である。10 is a silicon nitride film coated on the surface of the semiconductor device, and 11 is a resist film coated on the silicon nitride film.
つぎに半導体装置の製造の手順について説明する。Next, the procedure for manufacturing a semiconductor device will be explained.
■ 半導体装置の表面にプラズマＣＶＤでもってシリコ
ンナイトライドの膜１０を形成する。(2) A silicon nitride film 10 is formed on the surface of the semiconductor device by plasma CVD.
■ 前記シリコンナイトライド膜１０の上に通常の手段
、すなわち高速回転ウェハチャックに■の工程を経た半
導体装置を乗せてレジスト液を適量滴下して上記膜を形
成する。(2) On the silicon nitride film 10, the semiconductor device which has gone through the step (2) is placed on a conventional means, that is, a high-speed rotating wafer chuck, and an appropriate amount of resist solution is dropped to form the film.
■ その後、レジスト膜を被覆したウエノ＼をベーキン
グして乾燥する。■ After that, the Ueno coated with the resist film is baked and dried.
■ その後、ウェハ裏面をドライまたはウェットエツチ
ングでもって、ミラーポリッシュを行う。■ After that, perform mirror polishing on the back side of the wafer by dry or wet etching.
■ 所定の洗浄後、前記レジスト膜およびシリコンナイ
トライド膜をドライエツチングにより除去する。(2) After prescribed cleaning, the resist film and silicon nitride film are removed by dry etching.
（へ）効果
本発明の半導体装置の製造方法は従来の方法とは異なり
、レジスト膜のみでなくプラズマＣＶＤで形成したシリ
コンナイトライドの膜が被膜されている。したがって、
かかるシリコンナイトライド膜は大変に高密度でしかも
硬い膜であるから、スクラッチによる傷の付着が充分防
止できる。(f) Effects The method for manufacturing a semiconductor device of the present invention differs from conventional methods in that it is coated not only with a resist film but also with a silicon nitride film formed by plasma CVD. therefore,
Since such a silicon nitride film has a very high density and is a hard film, it can sufficiently prevent damage caused by scratches.
また、上記したＰＳＧｌ＊と異なり膜の硬度が高いので
ピンホールやクランクを生じる虞が少ないので、下部に
あるジャンクション部に影響を与えることがない。Furthermore, unlike the above-mentioned PSGl*, the film has a high hardness, so there is little risk of pinholes or cranks occurring, so the junction section at the bottom will not be affected.
第１図はバイポーラトランジスタについて、本発明の製
造方法を適用するときの半導体装置の断面図をしめす。
１０・・・シリコンナイトライド膜、１１・・・レジス
ト膜。
特許出願人 ローム株式会社
代理人 弁理士 大 西 孝 治FIG. 1 shows a cross-sectional view of a semiconductor device when the manufacturing method of the present invention is applied to a bipolar transistor. 10... Silicon nitride film, 11... Resist film. Patent Applicant: ROHM Co., Ltd. Agent, Patent Attorney: Takaharu Ohnishi
Claims (1)
コンナイトライド膜を被覆する工程と、前記シリコンナ
イトライド膜の上にレジスト膜を被覆する工程と、前記
工程の後半導体装置のウェハの裏面をミラーポリッシュ
する工程とを含むことを特徴とする半導体装置の製造方
法。(1) A step of coating the surface of the semiconductor device with a silicon nitride film by plasma CVD, a step of coating the silicon nitride film with a resist film, and a mirroring process of the back surface of the wafer of the semiconductor device after the step. A method for manufacturing a semiconductor device, comprising the step of polishing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58192749A JPH0642472B2 (en) | 1983-10-15 | 1983-10-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58192749A JPH0642472B2 (en) | 1983-10-15 | 1983-10-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6084821A true JPS6084821A (en) | 1985-05-14 |
| JPH0642472B2 JPH0642472B2 (en) | 1994-06-01 |
Family
ID=16296410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58192749A Expired - Lifetime JPH0642472B2 (en) | 1983-10-15 | 1983-10-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642472B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS621234A (en) * | 1985-05-31 | 1987-01-07 | Sony Tektronix Corp | Silicon semiconductor device |
| JPS6230373A (en) * | 1985-05-31 | 1987-02-09 | サイエンティフィック・イメージング・テクノロジーズ・インコーポレイテッド | Silicon wafer reinforced body |
| JPS6251226A (en) * | 1985-08-30 | 1987-03-05 | Toshiba Corp | Polishing method |
| CN105097431A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer front protecting method |
| CN105643431A (en) * | 2014-12-02 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Wafer grinding method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710933A (en) * | 1980-06-25 | 1982-01-20 | Mitsubishi Electric Corp | Abrasive method for back of substrate of semiconductor device |
-
1983
- 1983-10-15 JP JP58192749A patent/JPH0642472B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710933A (en) * | 1980-06-25 | 1982-01-20 | Mitsubishi Electric Corp | Abrasive method for back of substrate of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS621234A (en) * | 1985-05-31 | 1987-01-07 | Sony Tektronix Corp | Silicon semiconductor device |
| JPS6230373A (en) * | 1985-05-31 | 1987-02-09 | サイエンティフィック・イメージング・テクノロジーズ・インコーポレイテッド | Silicon wafer reinforced body |
| JPS6251226A (en) * | 1985-08-30 | 1987-03-05 | Toshiba Corp | Polishing method |
| CN105097431A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer front protecting method |
| CN105643431A (en) * | 2014-12-02 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Wafer grinding method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0642472B2 (en) | 1994-06-01 |
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