JPH0758304A - Manufacture of semiconductor wafer and analysis thereof by sims - Google Patents

Abstract

PURPOSE:To accurately measure impurity on the surface of sample wafer by SIMS by solving problems accompanied in the manufacturing steps of a sample for analysis. CONSTITUTION:A cap wafer 11 having an SOI structure is placed in close contact on the surface 2 of a semiconductor substrate (sample wafer) 1 to form a coupled wafer 21 through the heat treatment for two hours at 350 deg.C under the N2 atmosphere. Thereafter, in regard to the cap wafer, the basic Si layer 12 is etched with a mixed solution of fluoric acid, nitric acid and pure water and the SiO layer 13 is then etched by fluoric acid to manufacture a semiconductor wafer 31 having the structure that a thin film Si layer 14 is provided on the surface 2 of the semiconductor substrate 1. This semiconductor wafer 31 is then subjected to analysis by SIMS. Since the semiconductor substrate is quickly capped, contamination of the semiconductor substrate surface can be prevented. Moreover, since coupling can be done with a low temperature heat treatment, impurity at the semiconductor substrate surface is never diffused into the inside and vaporization of substances which may be vaporized at a comparatively lower temperature during manufacture of sample can also be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects impurities (pollutants) on the surface of a semiconductor wafer by secondary ion mass spectrometry (hereinafter referred to as S).
The present invention relates to a method of analysis by an IMS method), and more specifically, to a method of manufacturing a semiconductor wafer to be subjected to SIMS analysis.

[0002]

2. Description of the Related Art Conventionally, SIM has been used as a method for analyzing impurities on the surface of a semiconductor wafer such as a silicon single crystal wafer.
The S method is widely used. In this analysis method, the sample surface is sputtered with a primary ion beam, and the secondary ions emitted from the sputtered surface are subjected to mass spectrometry.In addition to being able to analyze the type and concentration of elements on the semiconductor wafer surface, Due to the sputtering phenomenon, it is possible to measure the impurity element profile in the depth direction of the semiconductor wafer.

However, in this SIMS method, the secondary ionization rate on the outermost surface of the sample is unstable, and it takes some time for the secondary ions emitted from the sample to stabilize, so the secondary ions are stable. At that time, it was difficult to analyze the impurities on the outermost surface of the sample with good reproducibility, because the surface to be analyzed had already been scraped off by sputtering and became in a state of being dug inside the surface.

As a method for solving such a problem, for example, as shown in FIG. 6, the surface of a sample wafer 61, that is, the surface to be measured 62 [FIG.
When a polysilicon layer 63 having a predetermined film thickness is deposited by emi-cal vapor deposition, a sample is prepared by depositing under conditions of, for example, 650 ° C. and 2 hours [FIG. 6 (b)]. By earning a preliminary sputtering time,
It is known that a stable secondary ion is emitted from the outermost surface of the sample wafer 61 (hereinafter referred to as a PC-SIMS method).

As another method, Japanese Patent Application No. 2-253937
The specification (title of the invention: method for cleaning semiconductor wafer and method for analyzing semiconductor wafer surface) includes FIG.
As shown in (d), the mirror-polished surface (measurement surface)
In addition to the sample wafer 71 having 72, the surface 72
A cap wafer 81 having a mirror-polished surface 82 is prepared as a silicon wafer for coating [FIG. 7 (a)], the mirror-polished surface 82 is superposed on and closely adhered to the surface 72 of the sample wafer 71, and these are bonded by heat treatment. To form a bonded wafer 91 [FIG. 7 (b)], the upper half of the bonded wafer 91 is ground [FIG. 7 (c)], and then polished (polished) to make the cap wafer 81 thin [FIG.
(D)], a method of irradiating a primary ion beam from the surface of the thin film Si layer 83 (hereinafter referred to as a direct bonding method) has been proposed.

In this method, similarly to the PC-SIMS method, the time required for the secondary ions to be stably released from the outermost surface of the sample wafer 71 is obtained by the thin film Si layer 83. The secondary ion emission is already in a stable state at the time when the sputtering of the sample surface by the beam is started.

[0007]

However, the above-mentioned P
In the C-SIMS method, it takes time to load the sample into the CVD furnace, and there is a high possibility that the sample surface is contaminated during the growth of the CVD film. Although the contamination from the CVD furnace can be measured by depositing the polysilicon layer in two layers, there is a problem that it is difficult to measure the original impurities of the sample before charging the sample into the furnace. Further, since a substance having a property of being vaporized at a relatively low temperature before polysilicon is coated on the surface of the sample wafer is easily vaporized, it is difficult to accurately analyze a component which is originally vaporizable in the sample. .

On the other hand, in the direct bonding method, it is necessary to make the bonding strength sufficient to prevent peeling at the bonding surface during the grinding or polishing, and for that purpose, the heat treatment is performed under conditions of high temperature and long time ( For example, it should be performed at 1100 ° C. or higher for about 2 hours. However, such heat treatment under severe conditions has a problem that impurities on the surface of the sample diffuse into the inside of the sample, making it impossible to accurately measure the original concentration, which is particularly important for elements with a high diffusion rate such as hydrogen and copper. There was a problem.

According to the present invention, a semiconductor substrate (sample wafer) and a cap wafer having an SOI structure are joined by a low temperature heat treatment, the base Si layer and SiO ₂ layer of the cap wafer are removed by etching with a chemical solution, and the sample surface is It is an object of the present invention to solve the above-mentioned conventional problems associated with the step of manufacturing a wafer sample to be subjected to the SIMS method by using a wafer having a form in which only the Si structure SOI layer of the cap wafer is left as a sample.

Further, according to the present invention, a semiconductor substrate (sample wafer) and an epitaxial growth wafer as a cap wafer are joined by a low temperature heat treatment, and the cap wafer is removed by etching with a chemical solution leaving an epitaxial growth layer of the cap wafer, By using a wafer whose surface is covered with the epitaxial growth layer as a sample, the above conventional problems are solved.

[0011]

According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor wafer, wherein a cap wafer composed of two or more layers having different characteristics is superposed on the surface of a semiconductor substrate, and the cap wafer is bonded by heat treatment. After that, the cap wafer portion is etched with an appropriate chemical solution to leave a thin film on the bonding surface, and a semiconductor wafer having a semiconductor thin film on a semiconductor substrate is obtained.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor wafer, wherein an S wafer is used as a cap wafer on the surface of a semiconductor substrate.
Wafers having an OI structure are superposed and adhered to each other and bonded by heat treatment, and the base Si layer of the cap wafer in this bonded wafer is removed by etching with an appropriate chemical solution, and then the SiO ₂ layer is removed by etching with a SiO ₂ layer removing etchant. Then, the SOI structure Si is formed on the bonding surface.
It is characterized in that a thin film is left and a semiconductor wafer having a Si thin film on a semiconductor substrate is obtained.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor wafer, wherein a cap wafer having a high-concentration boron-doped Si layer epitaxially grown on a Si epitaxial substrate doped with boron at a low concentration is formed on the surface of the semiconductor substrate, and the high-concentration boron-doped Si layer is formed. The layers are superposed and closely contacted with each other via a layer and bonded by a heat treatment, and the low-concentration boron-doped Si epitaxial substrate portion of the cap wafer in the bonded wafer is removed by etching with a KOH solution to leave a high-concentration boron-doped Si layer on the semiconductor substrate. A semiconductor wafer having a Si thin film layer on a semiconductor substrate is obtained.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor wafer according to the third aspect, the Si epitaxial substrate has a boron concentration of less than 10 ¹⁹ atoms / cm ³ , and the high-concentration boron-doped Si layer has a boron concentration of 10 ¹⁹ atoms. / cm ³ or more.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor wafer according to the first, second or third aspects, wherein the outer peripheral portion of the joint surface of the joint wafer is sealed with a chemical resistant sealant and then the cap wafer portion is etched. It is characterized by performing.

The analysis method by SIMS described in claim 6 is characterized in that a primary ion beam is irradiated from the surface of the thin film layer of the semiconductor wafer manufactured in claims 1, 2 and 3 to perform mass spectrometry.

The inventions described in claims 1, 2 and 6 will be described in more detail below with reference to FIGS. 1 (a) to 1 (d). FIG. 1 shows a procedure for preparing a sample for SIMS analysis. First, a semiconductor substrate (sample wafer) 1
And a cap wafer 11 having an SOI structure are prepared [FIG. 1 (a)]. In this case, the surface of the semiconductor substrate 1, that is, the surface to be measured 2 is a mirror-polished surface. The cap wafer 11 is made of SiO 2 with a film thickness of 1 μm on the base Si layer 12.
₂ layer 13 and Si layer 14 with a thin film thickness on this SiO ₂ layer
And the surface of this thin film Si layer 14 is mirror-polished. As a method for producing such a cap wafer 11, the above-mentioned Japanese Patent Application No. 2-253937.
Similar to the method described in Example 2 of the specification, that is, a silicon wafer having a thermal oxide film formed on one surface and a silicon wafer having no thermal oxide film are bonded together, and this bonded wafer is heat treated. Then, after increasing the bonding strength, one of the Si layers sandwiching the thermal oxide film can be thinned by grinding and polishing.

Then, the surface 2 of these semiconductor substrates 1 and
The thin film Si layer 14 of the cap wafer 11 is quickly overlapped and adhered to prevent contamination from the outside air, and then heat-treated in a nitrogen atmosphere at 350 ° C. for 2 hours to bond the sample wafer 1 and the cap wafer 11 together. Then, a bonded wafer 21 having a structure in which the surface 2 of the semiconductor substrate 1 is covered with the cap wafer 11 is formed (FIG. 1B).

If desired, an appropriate sealant (silicone sealant wax or the like) is applied to the outer peripheral portion of the bonding surface of the bonding wafer 21.
After applying the sealant to seal the joint surface (not shown),
For example, the base Si layer 12 of the cap wafer 11 of the bonded wafer 21 is completely removed by etching with a mixed solution of hydrofluoric acid, nitric acid and acetic acid (3: 5: 3) [FIG.
(C)]. In this case, since the etching rate of the SiO ₂ layer 13 is small, the etching stop is automatically applied when the removal of the Si layer 12 by etching is completed. Then SiO ₂ layer 1
3 is etched with diluted hydrofluoric acid or the like [FIG. 1 (d)].

As a result, the semiconductor substrate (sample wafer)
A semiconductor wafer 31 having a structure in which the thin film Si layer 14 is formed on the surface 2 of 1 is obtained. Using the semiconductor wafer 31 thus manufactured as a sample, SIMS
Perform an analysis.

Next, claim 1, claim 3, claim 4,
Explaining the invention of claim 6 in detail, first, a semiconductor substrate (sample wafer) and a cap wafer in which a high-concentration boron-doped Si layer is epitaxially grown on a Si epitaxial substrate doped with boron at a low concentration are prepared. . In this case, the surface of the semiconductor substrate is a mirror-polished surface. On the other hand, the cap wafer, boron is epitaxially grown silicon layer containing boron degree concentration 10 ¹⁹ atoms / cm ³ or more concentrations 10 ¹⁹ atoms / cm ³ less than about a doped Si epitaxial substrate in a thickness of 1.0μm It is assumed that the surface of this epitaxial layer is mirror-polished.

Then, the surfaces of these semiconductor substrates and the epitaxial layer of the cap wafer are quickly superposed and brought into close contact with each other to prevent contamination from the outside air, and then heat-treated in a nitrogen atmosphere at 350 ° C. for 2 hours, for example. A semiconductor wafer and a cap wafer are bonded to each other, and the cap wafer is used to cover the surface of the semiconductor substrate to form a bonded wafer.

If desired, an appropriate sealing agent is applied to the outer peripheral portion of the joint surface of the joint wafer to seal the joint surface,
The low-concentration boron-doped Si epitaxial substrate portion of the cap wafer in the bonded wafer is completely removed by etching with a KOH aqueous solution having a concentration of 10% or more. in this case,
Since the KOH aqueous solution has a small etch rate for the high-concentration boron-doped Si epitaxial layer,
When the i-epitaxial substrate is completely removed by etching, an etch stop is automatically applied.

As a result, the semiconductor substrate (sample wafer)
A semiconductor wafer having a structure in which a thin film high concentration boron-doped Si epitaxial layer is formed on the surface of is obtained. Using the semiconductor wafer thus manufactured as a sample,
SIMS analysis is performed by a conventional method.

[0025]

In the method for manufacturing a semiconductor wafer according to claim 1, unlike the conventional direct bonding method, the cap wafer covering the surface of the semiconductor substrate is not removed by grinding or polishing, but is etched by a chemical solution. , The bonding strength of the bonded wafer does not have to be so great, therefore,
High-temperature heat treatment is not required in the bonded wafer manufacturing process, and bonding can be performed by low-temperature processing. Therefore, it is possible to prevent impurities on the surface of the semiconductor substrate from diffusing inward in the process of manufacturing the bonded wafer. Moreover, since the cap wafer is composed of two or more layers having different characteristics (etch rates), an etching stop is applied when the etching removal of the layer having a high etching rate is completed, and the etching of the layer having a low etching rate does not substantially progress. The etching time can be easily controlled, and the thickness of the thin film on the semiconductor substrate of the semiconductor wafer can be set to a desired value by setting the thickness of the layer of the cap wafer to be joined to the semiconductor substrate in advance.

In the method for manufacturing a semiconductor wafer according to claim 2, unlike the conventional direct bonding method, the cap wafer having the SOI structure for covering the surface of the semiconductor substrate is not removed by grinding / polishing, but a chemical solution. Since the etching is carried out by the above method, high temperature heat treatment is not required in the manufacturing process of the bonded wafer, and bonding can be carried out by the low temperature processing. Therefore, it is possible to prevent impurities on the surface of the semiconductor substrate from diffusing inward in the process of manufacturing the bonded wafer. Moreover,
At the same time as the etching removal of the base Si layer on the cap wafer is completed, the etch stop is automatically applied to
_Since the etching of _two layers is not performed, the management of the etching time is simplified, and the SOI of the cap wafer is prepared in advance.
By setting the film thickness of the Si layer (corresponding to the portion indicated by reference numeral 14 in FIG. 1) of the structure portion, the film thickness of the thin film Si layer in the semiconductor wafer can be set to a desired value.
Further, unlike the conventional PC-SIMS method, the semiconductor substrate can be quickly capped by bonding.
Further, since the surface of the semiconductor substrate is heat-treated in a capped state, it is possible to prevent vaporization of substances that are likely to vaporize at a relatively low temperature.

The operation in the method of manufacturing a semiconductor wafer according to claim 3 is the same as that of the invention of claim 1, and since the cap wafer covering the surface of the semiconductor substrate is etched with a chemical solution, a high temperature is used in the manufacturing process of the bonding wafer. No heat treatment is required, and bonding can be performed by low temperature treatment. Therefore, it is possible to prevent impurities on the surface of the semiconductor substrate from diffusing inward in the process of manufacturing the bonded wafer. In addition, since the etching of the cap wafer is automatically stopped and the high-concentration boron-doped Si epitaxial layer is not etched, the etching time can be easily controlled, and the thickness of the high-concentration boron-doped Si epitaxial layer of the cap wafer can be controlled in advance. By setting, the film thickness of the Si thin film layer on the semiconductor substrate in the semiconductor wafer can be set to a desired value.

In the method of manufacturing a semiconductor wafer according to claim 4, the boron concentration of the Si epitaxial substrate is less than 10 ¹⁹ atoms / cm ³ , and the high-concentration boron-doped Si is used.
Since the boron concentration of the layer is 10 ¹⁹ atoms / cm ³ or more and the difference in boron concentration between the high-concentration boron-doped Si epitaxial layer and the low-concentration boron-doped Si epitaxial substrate is clear, the etch rate is between the two layers. Since the difference is clearly different, it is possible to surely realize the etching stop after the etching of the low-concentration boron-doped Si epitaxial substrate is completed.

In the method of manufacturing a semiconductor wafer according to the fifth aspect, since the bonding outer peripheral surface (side surface) of the bonding wafer is sealed with a sealant having durability against the etching chemical, etching is performed. Even if the bonding strength is somewhat low, the chemical solution does not enter the bonding surface, so that the semiconductor substrate and the cap wafer are not separated.

The analysis method by SIMS according to claim 6 is suitable for SIMS analysis, because mass spectrometry is performed by irradiating a primary ion beam from the surface of the thin film layer of the semiconductor wafer manufactured in claims 1, 2 and 3. SIM by the sample
The S analysis becomes possible, and the impurities on the surface of the semiconductor substrate (sample wafer) can be analyzed more accurately.

According to the semiconductor wafer manufacturing method of the first to third aspects, it is possible to manufacture a semiconductor wafer suitable as a sample for the analysis method by SIMS.

[0032]

EXAMPLES Next, examples of the present invention will be described in comparison with the conventional method. Example 1 A plurality of semiconductor wafers (sample wafers) that have been processed up to single-sided mirror polishing by a normal processing step and a plurality of cap wafers each having an SOI structure are prepared, and after cleaning these wafers under the following conditions, A semiconductor wafer was prepared according to the procedure shown in FIG. 1 and used as a sample, and what impurity light element remained on the cleaned surface of the wafer was measured. (1) HF cleaning: Concentration is 5% by weight, temperature is normal temperature (2) SC1 cleaning: Composition is NH ₄ OH: H ₂ O ₂ : H
₂ O = 1: 1: 6, temperature is 80 ° C. (3) SC2 cleaning: Composition is HCl: H ₂ O ₂ : H ₂ O
= 1: 1: 6, temperature is 80 ℃

An N-type silicon wafer is used as the semiconductor substrate (sample wafer) and the cap wafer,
Bonding for bonding wafer is about 1 after cleaning.
It took less than a minute in a class 1000 clean room.
The heat treatment for bonding is performed at 600 ° C. for 2 hours in an N ₂ atmosphere in any of the cleaned products, and the cap wafer in the bonding wafer is etched to form a film on the surface of the semiconductor substrate (sample wafer). 1.5
A μm thin film Si layer was provided.

Comparative Example 1 (PC-SIMS Method) On the surface of the semiconductor substrate (sample wafer) after the cleaning,
According to the process shown in FIG. 6, a polysilicon layer having a film thickness of 1.5 μm was formed by CVD at 650 ° C. for 2 hours.

The standard SIMS measurement conditions are shown in [Table 1]. In addition, RSF (Relative Sensitivity Fact
or) calculation formula (PMkahora and FAStevei, in SIMS
VII, pp.143)) and converted to the surface concentration.
The conversion formula is shown in [Equation 1].

[0036]

[Table 1]

[0037]

[Equation 1]

RSF: Conversion factor in volume concentration (atoms / cm ³ ) D: Measurement depth (cm) ΣIi: Total count of impurity ions Ib: Background of impurities (CPS) C: Measurement cycle Im: Strength of matrix element (CPS)

FIG. 2 shows a SIMS chart according to Example 1, and FIG. 3 shows a SIMS chart according to Comparative Example 1. As is clear by comparing these, Example 1
In comparison with Comparative Example 1, a chart having a considerably sharper peak was obtained. The sharp peak means that the SN ratio is good and the detection sensitivity is extremely high. Such a sharp peak is considered to be because the Si layer covering the surface of the semiconductor substrate (sample wafer) is a single crystal, not polysilicon, and thus the roughness of the crater bottom is suppressed.

The analysis results according to Example 1 are shown in FIG. An oxide film is formed at the joint between the mirror-polished surface of the semiconductor substrate (sample wafer) and the mirror-polished surface of the cap wafer. B is detected from the joint of the SC1 and SC2 cleaned joint wafers. , B was not detected in the HF washed sample having no oxide film. The contact time with the atmosphere in the clean room depends on the HF cleaning sample, SC1 and S
Since it is the same as the sample of C2 cleaning, B is S without oxide film.
It is considered that it is hard to adhere to the i surface. A large amount of F was detected in the HF washed sample and the SC1 washed sample. Al
Was detected only in SC1 washed samples, and other analyzes (VPD
-AAS) method showed the same result. Cl was detected from the SC2 washed sample, but it is considered that this is because Cl from HCl was mixed in the oxide film.

Example 2 A plurality of semiconductor substrates (sample wafers) and cap wafers identical to those used in Example 1 were prepared. The former was cleaned with a chemical solution and then left in a clean room, and the latter was cleaned with a chemical solution. I went. Using these wafers, the semiconductor wafer shown in FIG. 1 (d) was produced by the procedure shown in FIG. 1, and boron (B) contamination was evaluated by leaving it in a clean room.

That is, the semiconductor substrate (sample wafer) was cleaned in the order of SC1 cleaning, SC2 cleaning and SC1 cleaning (the composition of the chemical solution and the like are the same as those in Example 1).
After drying, the sample was left in a class 1000 clean room with various periods of time. Further, the cap wafer was subjected to HF cleaning (the composition and the like are the same as those in Example 1), and a semiconductor wafer was manufactured from these wafers by the procedure shown in FIG.

Since the bonding was carried out immediately after the HF cleaning of the cap wafer was completed, it is considered that the film thickness of the cap wafer surface oxide film on each bonded wafer was substantially constant. The heat treatment for joining was performed in an RTA furnace in an N ₂ atmosphere at 600 ° C. for 2 hours. Then, the cap wafer portion of the bonded wafer was etched to form a thin film Si layer having a thickness of 1.5 μm on the surface of the semiconductor substrate (sample wafer).

FIG. 5 shows the relationship between the time during which the semiconductor substrate is left in a clean room and the boron concentration at the bonding interface of the bonding wafer. From this figure, it was confirmed that the boron concentration increased with the increase of the standing time and that there was pollution from the clean room atmosphere. In addition, a considerably large amount of boron, 4 × 10 ¹⁰ atoms / cm ² , was detected even after being left for a short time of 25 seconds. From this, it is considered that the wafer bonding should be performed in the environment where the boron contamination countermeasure is taken when the surface boron of 4 × 10 ¹⁰ atoms / cm ² or less is measured also in the analysis method according to the present invention. .

When the surface boron is measured by the PC-SIMS method, boron of 1 × 10 ¹² atoms / cm ² or more is usually detected. In addition, since it takes 5 minutes or more to expose the sample wafer to the clean room atmosphere at the time of measurement, the boron concentration that can be measured by the PC-SIMS method is approximately the shaded area in FIG.

As described above, in the PC-SIMS method, since high-concentration boron contamination occurs during the manufacturing process of the polysilicon-deposited wafer, the original low-concentration surface boron of the sample wafer before the deposition of the polysilicon layer cannot be measured. It is impossible. On the other hand, in the present invention, the detection limit of surface boron can be significantly reduced as compared with the PC-SIMS method as described above, and light elements such as C, Cl and F can be measured. Further, the same result as above was obtained even when the sample was prepared under the heat treatment condition for joining at 350 ° C. for 2 hours.

[0047]

As is clear from the above description, according to the method of manufacturing a semiconductor wafer of the first aspect, a cap wafer composed of two or more layers having different characteristics is bonded to a semiconductor substrate and then a chemical solution is used. A semiconductor wafer is formed by etching to form a thin film on the surface of the semiconductor substrate. Further, according to the method of manufacturing a semiconductor wafer according to claim 2, after the wafer having the SOI structure is bonded to the semiconductor substrate, the chemical solution is used. The method for producing a semiconductor wafer according to claim 3, wherein the semiconductor wafer is provided with a high concentration boron-doped Si epitaxial layer on the surface of the semiconductor substrate. These wafers are bonded together and then etched with a chemical solution to form the epitaxial layer on the surface of the semiconductor substrate. When the SIMS analysis using a semiconductor wafer is obtained excellent effects as follows. (1) Since the required bonding strength of the bonded wafer can be significantly reduced as compared with the case of the direct bonding method, high temperature heat treatment is not necessary in the manufacturing process, and bonding by low temperature treatment is sufficient. Impurities on the surface of the semiconductor substrate can be prevented from diffusing inside during the process of manufacturing the bonded wafer. Therefore, highly sensitive analysis can be performed, and hydrogen that easily diffuses can also be analyzed. (2) Since the semiconductor substrate surface can be prevented from being contaminated by quickly capping the semiconductor substrate by bonding, accurate analysis is possible. (3) Since the heat treatment is performed with the surface of the semiconductor substrate being capped, it is possible to prevent vaporization of substances that are likely to vaporize at a relatively low temperature, and therefore accurate analysis is possible. (4) Unlike the PC-SIMS method, in the method of claim 1, since the Si layer covering the surface of the semiconductor substrate is a single crystal, a SIMS chart having a sharp peak with a high SN ratio can be obtained. The detection limit of elements can be significantly reduced. (5) Unlike the PC-SIMS method, the diffusion of impurities on the surface of the semiconductor substrate is extremely small, and the contamination during the semiconductor wafer manufacturing process is also extremely small. Therefore, the analysis on the measurement surface is accurate. (6) It is also possible to measure light elements such as C, Cl and F. According to the method for manufacturing a semiconductor wafer according to any one of claims 3 and 4, the boron concentration of the Si epitaxial substrate is 10 or less.
Less than ¹⁹ atoms / cm ³ , the boron concentration of the high-concentration boron-doped Si layer is 10 ¹⁹ atoms / cm ³ or more, the high-concentration boron-doped Si epitaxial layer and the low-concentration boron-doped S
Since the difference in boron concentration between the i-epitaxial substrate and the i-epitaxial substrate is clear, the etch rate is clearly different between the two layers, and an etch stop after the removal of the low-concentration boron-doped Si epitaxial substrate is surely achieved. it can. According to the method of manufacturing a semiconductor wafer according to claim 5, since the outer peripheral surface (side surface) of the bonded wafer is sealed with a sealant having durability against the etching chemical solution and etched, even if the bonding strength of the bonded surface is Even if it is slightly low, the chemical solution will not enter the joint surface. Therefore, the accuracy and reproducibility of the measurement data can be improved, and the heat treatment in the manufacturing process of the bonded wafer can be carried out at a lower temperature than the case where no sealant is used, if desired. According to the method of manufacturing a semiconductor wafer according to any one of claims 1 to 5, a semiconductor wafer suitable for a sample for SIMS analysis can be manufactured. Claim 6
The analysis method by SIMS according to claim 1,
Since the mass spectrometry is performed by irradiating the primary ion beam from the surface of the thin film layer of the semiconductor wafer manufactured in
SIMS analysis with a sample suitable for S analysis becomes possible,
The impurities on the surface of the semiconductor substrate can be analyzed more accurately.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a sample manufacturing process according to the present invention, and is a sectional view of a wafer.

FIG. 2 is a SIMS chart according to Example 1 of the present invention.

FIG. 3 SIMS according to Comparative Example 1 (PC-SIMS method)
Is a chart of.

FIG. 4 is a graph showing analysis results of various elements according to Example 1.

FIG. 5 is a graph showing the results of analyzing boron according to Example 2.

FIG. 6 is an explanatory diagram of a sample preparation process by a PC-SIMS method, and is a sectional view of a wafer.

FIG. 7 is an explanatory diagram of a sample manufacturing process by a conventional direct bonding method, and is a sectional view of a wafer.

[Explanation of symbols]

1, 61, 71 Semiconductor substrate (sample wafer) 2, 62, 72 Surface (measurement surface) 11, 81 Cap wafer 12 Base Si layer 13 SiO ₂ layer 14, 83 Thin film Si layer 21, 91 Bonding wafer 31 Semiconductor wafer 63 Polysilicon layer 82 Mirror polished surface

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/66 L 7630-4M (72) Inventor Takuo Takenaka 2-13, Isobe, Annaka-shi, Gunma No. 1 Shin-Etsu Semiconductor Co., Ltd. Semiconductor Isobe Laboratory

Claims (6)

[Claims] 1. A surface of a semiconductor substrate, a cap wafer composed of two or more layers having different characteristics are superposed and adhered to each other, bonded by heat treatment, and then the cap wafer portion is etched with an appropriate chemical solution to form a bonded surface. A method of manufacturing a semiconductor wafer, which comprises leaving a thin film on the top and obtaining a semiconductor wafer having a semiconductor thin film on a semiconductor substrate. 2. A wafer having an SOI structure as a cap wafer is superposed on and adhered to the surface of a semiconductor substrate and bonded by heat treatment, and the base Si layer of the cap wafer in the bonded wafer is removed by etching with an appropriate chemical solution. then leaving the SOI structure Si thin SiO ₂ layer on the bonding surface on the etched away by the SiO ₂ layer removing etchant according to claim 1, characterized in that to obtain a semiconductor wafer having a Si thin film on a semiconductor substrate Manufacturing method of semiconductor wafer. 3. A cap wafer, which is obtained by epitaxially growing a high-concentration boron-doped Si layer on a Si epitaxial substrate lightly doped with boron, is superposed on the surface of a semiconductor substrate via the high-concentration boron-doped Si layer so as to be in close contact therewith, and then heat treated. And the low-concentration boron-doped Si of the cap wafer on the bonded wafer.
The semiconductor wafer according to claim 1, wherein the epitaxial substrate portion is removed by etching with a KOH solution to leave a high-concentration boron-doped Si layer on the semiconductor substrate, and a semiconductor wafer having a Si thin film layer on the semiconductor substrate is obtained. Production method. 4. The high-concentration boron-doped Si having a boron concentration of the Si epitaxial substrate of less than 10 ¹⁹ atoms / cm ^3.
The method for producing a semiconductor wafer according to claim 3, wherein the boron concentration of the layer is 10 ¹⁹ atoms / cm ³ or more. 5. The semiconductor wafer according to claim 1, wherein the outer peripheral portion of the joint surface of the joint wafer is sealed with a chemical-resistant sealant, and then the cap wafer portion is etched. Manufacturing method. 6. An analysis method by SIMS, which comprises irradiating a primary ion beam from the surface of the thin film layer of the semiconductor wafer manufactured in any one of claims 1, 2 and 3 to perform mass spectrometry.