JPH0642472B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0642472B2 JPH0642472B2 JP58192749A JP19274983A JPH0642472B2 JP H0642472 B2 JPH0642472 B2 JP H0642472B2 JP 58192749 A JP58192749 A JP 58192749A JP 19274983 A JP19274983 A JP 19274983A JP H0642472 B2 JPH0642472 B2 JP H0642472B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film
- silicon nitride
- nitride film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は半導体装置の製造方法に係り、特に半導体装置
のウエハの裏面とミラーポリッシュする際に使用する半
導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device used for mirror polishing the back surface of a wafer of a semiconductor device.
（ロ）従来技術 例えば圧力センサを製造する場合、半導体装置のウエハ
の裏面に前記圧力センサを形成するための孔あけ加工を
するが、そのため半導体装置のウエハ裏面をまえもって
ミラーポリッシュしておくことがある。(B) Conventional Technology For example, when manufacturing a pressure sensor, a hole is formed on the back surface of a semiconductor device wafer to form the pressure sensor. Therefore, the back surface of the semiconductor device wafer may be mirror-polished in advance. is there.
かかるミラーポリッシュを行うに際しては、研磨台等の
上に松やに等を塗布し、これに半導体基板の表面側を貼
り付けて保持した状態で半導体の裏面をミラーポリッシ
ュするので、すでに素子領域等が形成された半導体の表
面に保護用の膜を被覆する必要があり、その膜として従
来はワックスやテープに１匹敵する高粘度のレジスト膜
が使用されている。When performing such mirror polishing, the back surface of the semiconductor is mirror-polished while applying the pine or the like on a polishing table or the like, and the front surface side of the semiconductor substrate is attached and held on this, so that the element region or the like is already formed. It is necessary to coat the surface of the formed semiconductor with a protective film, and as the film, a high-viscosity resist film which is comparable to wax or tape is conventionally used.
しかし、上記の方法では、レジスト膜の周辺部分が剥離
したり、スクラッチ等により傷が発生することがあり、
その傷を通して種々の汚染源が半導体装置の中心部まで
浸透する結果、充分にはウエハの保護が出来ないという
欠点があった。However, in the above method, the peripheral portion of the resist film may be peeled off, or scratches may occur due to scratches,
As a result of various contaminants penetrating to the center of the semiconductor device through the scratches, there is a drawback that the wafer cannot be sufficiently protected.
また、ＣＶＤでもってＰＳＧ膜を形成する方法もある
が、このＰＳＧ膜はドライまたはウエットエッチングす
る場合、その条件ぎめが難しく場合によっては下地の酸
化シリコン膜までエッチングしてしまう虞があった。There is also a method of forming a PSG film by CVD, but when this PSG film is dry or wet-etched, it may be difficult to determine the conditions, and in some cases the underlying silicon oxide film may be etched.
（ハ）目的 本発明に係る半導体装置の製造方法はその裏面のミラー
ポリッシュの際にその表面を充分に保護しうる保護膜を
提供することを目的としている。(C) Objective The object of the method for manufacturing a semiconductor device according to the present invention is to provide a protective film capable of sufficiently protecting the front surface of the rear surface of the device during mirror polishing.
（ニ）構成 本発明に係る半導体装置の製造方法は、素子領域が形成
された半導体基板の表面をシリコンナイトライド膜で被
覆する工程と、前記シリコンナイトライド膜の上にレジ
スト膜を被覆する工程と、前記工程の後半導体基板の裏
面をミラーポリッシュする工程と、このミラーポリッシ
ュの後前後レジスト膜とシリコンナイトライド膜とを除
去する工程と、素子領域の該当部分に孔明けを行う工程
とを有している。(D) Configuration A method of manufacturing a semiconductor device according to the present invention includes a step of coating a surface of a semiconductor substrate having an element region with a silicon nitride film, and a step of coating a resist film on the silicon nitride film. A step of mirror polishing the back surface of the semiconductor substrate after the step, a step of removing the resist film and the silicon nitride film before and after the mirror polishing, and a step of forming a hole in a corresponding portion of the element region. Have
（ホ）実施例 第１図はバイポーラトランジスタについて、本発明の製
造方法を適用するときの半導体装置の断面図をしめす。(E) Example FIG. 1 shows a cross-sectional view of a semiconductor device when a manufacturing method of the present invention is applied to a bipolar transistor.
１はボロンをドープしたＰ型のシリコン基板であるウエ
ハ、２は砒素またはアンチモンを熱拡散させて形成した
Ｎ型の埋込層、３はＮ型のエピタキシャル層、４はＰ
層、５はＮ＋層、６はシリコン酸化膜層であり、７、８
および９はそれぞれＰ層４であるベース、Ｎ＋層５であ
るエミッタおよびＮ型のエキタピシャル層３であるコレ
クタにコンタクトしたアルミニウム電極である。1 is a wafer that is a P-type silicon substrate doped with boron, 2 is an N-type buried layer formed by thermally diffusing arsenic or antimony, 3 is an N-type epitaxial layer, and 4 is P
Layers, 5 is an N + layer, 6 is a silicon oxide film layer, 7 and 8
Aluminum electrodes 9 and 9 are in contact with the base, which is the P layer 4, the emitter, which is the N + layer 5, and the collector, which is the N-type epitaxial layer 3.
このようなトランジスタ領域が形成された半導体基板の
裏面のミラーポリッシュは次の順序で行われる。The mirror polishing of the back surface of the semiconductor substrate on which such a transistor region is formed is performed in the following order.
半導体装置の表面にプラズマＣＶＤでもってシリコン
ナイトライドの膜10を形成する。A silicon nitride film 10 is formed on the surface of the semiconductor device by plasma CVD.
前記シリコンナイトライド膜10の上に通常の手段、す
なわち高速回転ウエハチャックにの工程を経た半導体
装置を乗せてレジスト液を適量滴下してレジスト膜11を
形成する。レジスト膜11はもろいシリコンナイトライド
膜10に対するクッション材として働く。The resist film 11 is formed on the silicon nitride film 10 by placing an ordinary means, that is, a semiconductor device that has undergone the process of a high speed rotation wafer chuck, and dropping an appropriate amount of resist solution. The resist film 11 acts as a cushioning material for the brittle silicon nitride film 10.
その後、レジスト膜を被膜したウエハをベキングして
乾燥する。Then, the wafer coated with the resist film is baked and dried.
その後、ウエハ裏面をドライまたはウエットエッチン
グでもって、ミラーポリッシュを行う。After that, mirror polishing is performed on the back surface of the wafer by dry or wet etching.
所定の洗浄後、前記レジスト膜およびシリコンナイト
ライド膜をドライエッチングにより除去する。After the predetermined cleaning, the resist film and the silicon nitride film are removed by dry etching.
その後、素子領域の該当部分に孔明けを行う。After that, perforation is performed on the corresponding portion of the element region.
（ヘ）効果 本発明の半導体装置の製造方法は従来の方法とは異な
り、レジスト膜のみでなくプラズマＣＶＤで形成したシ
リコンナイトライドの膜が被膜されている。したがっ
て、かかるシリコンナイトライド膜は大変に高密度でし
かも硬い膜であるから、スクラッチにより傷の付着が充
分防止できるので、半導体装置の素子が異物の侵入によ
って汚染される恐れがない利点を有する。(F) Effect The semiconductor device manufacturing method of the present invention is different from the conventional method in that not only the resist film but also the silicon nitride film formed by plasma CVD is coated. Therefore, since the silicon nitride film has a very high density and is hard, scratches can be sufficiently prevented from adhering to the semiconductor device, and thus there is an advantage that the element of the semiconductor device is not contaminated by foreign matter.
また、上記したＰＳＧ膜と異なり、シリコンナイトライ
ド膜は膜の高度が高いのでピンホールやクラックを生じ
る恐れが少ないのみならず、エッチングの制御が容易で
あり、また半導体装置の素子内部に対する汚染源となら
ないので、下部にあるジャンクション部に影響を与える
ことがない。Further, unlike the above-mentioned PSG film, the silicon nitride film has a high film height, so that it is less likely to cause pinholes and cracks, etching is easy to control, and it is a source of contamination to the inside of the element of the semiconductor device. Therefore, it does not affect the lower junction part.
第１図はバイポーラトランジスタについて、本発明の製
造方法を適用するときの半導体装置の断面図をしめす。 10……シリコンナイトライド膜、11……レジスト膜。FIG. 1 shows a sectional view of a semiconductor device when a manufacturing method of the present invention is applied to a bipolar transistor. 10 …… Silicon nitride film, 11 …… Resist film.
Claims (1)
シリコンナイトライド膜で被覆する工程と、前記シリコ
ンナイトライド膜の上にレジスト膜を被覆する工程と、
前記工程の後半導体基板の裏面をミラーポリッシュする
工程と、このミラーポリッシュの後前記レジスト膜とシ
リコンナイトライド膜とを除去する工程と、素子領域の
該当部分に孔明けを行う工程とを具備したことを特徴と
する半導体装置の製造方法。1. A step of coating a surface of a semiconductor substrate on which an element region is formed with a silicon nitride film, and a step of coating a resist film on the silicon nitride film.
After the step, the step of mirror-polishing the back surface of the semiconductor substrate, the step of removing the resist film and the silicon nitride film after the mirror-polishing, and the step of making a hole in the corresponding portion of the element region are provided. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58192749A JPH0642472B2 (en) | 1983-10-15 | 1983-10-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58192749A JPH0642472B2 (en) | 1983-10-15 | 1983-10-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6084821A JPS6084821A (en) | 1985-05-14 |
| JPH0642472B2 true JPH0642472B2 (en) | 1994-06-01 |
Family
ID=16296410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58192749A Expired - Lifetime JPH0642472B2 (en) | 1983-10-15 | 1983-10-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642472B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS621234A (en) * | 1985-05-31 | 1987-01-07 | Sony Tektronix Corp | Silicon semiconductor device |
| KR970000416B1 (en) * | 1985-05-31 | 1997-01-09 | 사이언티픽 이매징 테크놀로지시 이코포레이티드 | Silicon wafer reinforcing materials |
| JPS6251226A (en) * | 1985-08-30 | 1987-03-05 | Toshiba Corp | Polishing method |
| CN105097431A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer front protecting method |
| CN105643431B (en) * | 2014-12-02 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Wafer grinding method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710933A (en) * | 1980-06-25 | 1982-01-20 | Mitsubishi Electric Corp | Abrasive method for back of substrate of semiconductor device |
-
1983
- 1983-10-15 JP JP58192749A patent/JPH0642472B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6084821A (en) | 1985-05-14 |
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