JP2535957B2 - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JP2535957B2
JP2535957B2 JP62245014A JP24501487A JP2535957B2 JP 2535957 B2 JP2535957 B2 JP 2535957B2 JP 62245014 A JP62245014 A JP 62245014A JP 24501487 A JP24501487 A JP 24501487A JP 2535957 B2 JP2535957 B2 JP 2535957B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
semiconductor substrate
substrates
outer peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62245014A
Other languages
Japanese (ja)
Other versions
JPS6489346A (en
Inventor
伸幸 伊沢
弘 佐藤
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62245014A priority Critical patent/JP2535957B2/en
Publication of JPS6489346A publication Critical patent/JPS6489346A/en
Application granted granted Critical
Publication of JP2535957B2 publication Critical patent/JP2535957B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、単体半導体装置あるいは半導体集積回路装
置等の各種半導体装置を作製する場合に用いられる半導
体基板、特に第1及び第2の半導体基板が貼り合わされ
てなる半導体基板に関わる。
Description: TECHNICAL FIELD The present invention relates to a semiconductor substrate used when manufacturing various semiconductor devices such as a single semiconductor device or a semiconductor integrated circuit device, and particularly first and second semiconductor substrates. Related to a semiconductor substrate formed by bonding.

〔発明の概要〕[Outline of Invention]

本発明は、2枚の半導体基板が貼り合わされてなる半
導体基板において、その少くとも第1の半導体基板の外
周端が第2の半導体基板の外周端より内側にあるように
して2枚の半導体基板の貼り合わせにおいて問題となる
周縁部の貼り合わせ部における不良部が排除され、しか
もその有効使用面積の増大化とまた半導体基板としての
規格に合致した半導体基板を得ることができるようにし
て取り扱いの簡便化を図る。
The present invention relates to a semiconductor substrate in which two semiconductor substrates are bonded together, so that at least the outer peripheral edge of the first semiconductor substrate is inside the outer peripheral edge of the second semiconductor substrate. The defective part in the bonding part at the peripheral part which is a problem in the bonding is eliminated, the effective use area is increased, and the semiconductor substrate conforming to the standard as the semiconductor substrate can be obtained. Make it simple.

〔従来の技術〕[Conventional technology]

従来、第4図にその一部の拡大断面図を示すように第
1及び第2の例えばシリコン単結晶半導体基板(1)及
び(2)が直接的にあるいは酸化物膜を介して接合され
て各種大電力用ないしは高耐圧用半導体装置、あるいは
いわゆるSOI型(セミコンダクタ オン インシュレー
タ)等の半導体基板(3)を構成することが行われてい
る。この種の第1及び第2のシリコン半導体基板(1)
及び(2)の直接的接合あるいは酸化膜介存による接合
等については例えば特開昭60−121776号公報,特開昭60
−121777号公報,電子通信学会技術研究報告SDM87−25
第9〜14頁,同報告SDM87−24第5〜8頁、あるいはア
プライド フィジックス レター(Appl.Phys.Lett.)V
ol.48,No.1,6,1月1986第78〜第80頁等にその開示があ
る。
Conventionally, as shown in a partially enlarged cross-sectional view of FIG. 4, first and second silicon single crystal semiconductor substrates (1) and (2) are bonded directly or through an oxide film. BACKGROUND ART Various semiconductor devices for high power or high breakdown voltage, or a semiconductor substrate (3) such as a so-called SOI type (semiconductor on insulator) or the like is constructed. This kind of first and second silicon semiconductor substrates (1)
Regarding the direct joining or (2) joining by means of an oxide film or the like, for example, JP-A-60-121776 and JP-A-60-
-121777, IEICE Technical Report SDM87-25
Pages 9-14, SDM 87-24, pages 5-8, or Applied Physics Letter (Appl.Phys.Lett.) V
ol.48, No.1,6, January 1986, pages 78 to 80, etc.

これら第1及び第2の半導体基板が接合合体された半
導体基板においては、第4図に示すようにそれぞれその
第1の半導体基板(1)及び第2の半導体基板(2)自
体の研磨等に際して積極的にあるいは必然的にその外周
肩部が丸味を帯びた形状とされていることによって、こ
れら2枚の半導体基板(1)及び(2)を接合合体した
場合、その外周端の互いの合体部には、隙間が生じ、ま
た両基板(1)及び(2)のいずれかによる不均一な段
違いが発生し、この半導体基板(3)に対する各種半導
体素子の製造過程において塵埃の付着、汚損の発生、機
械的取扱いの不確実性等を招来するために、半導体装置
の製造プロセス前にこの隙間ないしは段差(4)を有す
る部分の排除がなされる。この排除すべき幅W1は、例え
ば第1及び第2の半導体基板として直径6インチの半導
体基板同士の接合である場合、例えばW1=0.4インチ程
度となる。したがって、この隙間ないしは段差(4)を
排除する目的のみで接合半導体基板の外周端の排除を行
う場合には直径6インチの半導体基板が直径5.6インチ
程度に減少させればよいことになる。ところが、実際上
半導体装置の製造において半導体基板を取り扱う各種装
置においては、その取り扱う半導体基板の直径が規定さ
れていて例えば標準サイズの3インチ,4インチ,5イン
チ,6インチ,8インチ…等に決められてしまうために必要
最小限の切削幅W1が0.4インチ程度であっても、これよ
り充分大きな幅W2をもって外周端からの切削を行って、
例えば両基板(1)及び(2)の初期の径が6インチの
基板である場合、接合後には、5インチの標準サイズの
基板にする必要が生じ、半導体材料の無駄が大となり、
またこのような大なる幅のW2をもって接合基板の周辺を
大きく排除することはその加工作業に長時間を要し、技
術的にも面倒で作業性が低下するなどの問題点がある。
In the semiconductor substrate in which the first and second semiconductor substrates are joined and combined, as shown in FIG. 4, when polishing the first semiconductor substrate (1) and the second semiconductor substrate (2) themselves, etc. When these two semiconductor substrates (1) and (2) are joined and joined by positively or inevitably having a rounded outer peripheral shoulder, the outer peripheral ends are joined together. A gap is formed in the portion, and uneven steps are generated due to either of the substrates (1) and (2), which may cause dust adhesion and contamination during the manufacturing process of various semiconductor elements on the semiconductor substrate (3). In order to cause generation and uncertainties in mechanical handling, the gap or the portion having the step (4) is eliminated before the manufacturing process of the semiconductor device. The width W 1 to be excluded is, for example, W 1 = 0.4 inch in the case of joining semiconductor substrates having a diameter of 6 inches as the first and second semiconductor substrates. Therefore, when the outer peripheral edge of the bonded semiconductor substrate is removed only for the purpose of eliminating the gap or the step (4), the diameter of the semiconductor substrate having a diameter of 6 inches should be reduced to about 5.6 inches. However, in various devices that actually handle semiconductor substrates in the manufacture of semiconductor devices, the diameter of the semiconductor substrate to be handled is regulated, and for example, standard sizes of 3 inches, 4 inches, 5 inches, 6 inches, 8 inches ... Even if the minimum required cutting width W 1 is about 0.4 inch because it is decided, by cutting from the outer peripheral edge with a width W 2 that is sufficiently larger than this,
For example, when the initial diameter of both substrates (1) and (2) is a 6-inch substrate, it is necessary to make a standard-sized substrate of 5 inches after joining, which results in a large waste of semiconductor material.
Further, if the periphery of the bonded substrate is largely excluded with such a large width W 2, the processing work requires a long time, which is technically troublesome and the workability is deteriorated.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

本発明は、上述した第1及び第2の半導体基板の接合
によって形成される半導体基板において、半導体材料の
無駄をできるだけ小さくし、かつ標準サイズを取り扱う
従来の半導体装置の製造装置をそのまま使用することを
可能にした半導体基板を提供するものである。
According to the present invention, in a semiconductor substrate formed by joining the above-described first and second semiconductor substrates, waste of semiconductor material is reduced as much as possible, and a conventional semiconductor device manufacturing apparatus that handles a standard size is used as it is. The present invention provides a semiconductor substrate that enables the above.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、第1図に示すように第1及び第2の半導体
基板(1)及び(2)が貼り合わされてなり、かつ少く
ともその第1の半導体基板(1)の外周端が第2の半導
体基板(2)の外周端より内側にあるような構成とす
る。
According to the present invention, as shown in FIG. 1, first and second semiconductor substrates (1) and (2) are attached to each other, and at least the outer peripheral edge of the first semiconductor substrate (1) is second. The semiconductor substrate (2) is located inside the outer peripheral edge.

〔作用〕[Action]

上述の本発明による半導体基板によれば、一方の半導
体基板(2)についてはその少くとも一部の外周端が残
されていることによって標準サイズの規格を有するもの
であり、一方の基板(1)についてのみその外周端が排
除された小径構成をとることによって第1及び第2の基
板(1)及び(2)間に隙間ないしはずれによる不均一
な段差を回避でき、これによって、上述した半導体装置
の製造過程における汚損等の問題を回避でき、しかも全
体としての直径は初期状態の標準サイズを有することか
ら、標準サイズを取り扱う製造装置の使用が可能になり
半導体材料の排除、すなわち無駄を最小限に留めること
ができる。
According to the above-described semiconductor substrate of the present invention, one semiconductor substrate (2) has a standard size standard because at least a part of the outer peripheral edge thereof is left, and one semiconductor substrate (1) ), A non-uniform step due to gaps or deviations between the first and second substrates (1) and (2) can be avoided by adopting a small diameter configuration in which the outer peripheral edge is excluded. It is possible to avoid problems such as fouling in the manufacturing process of the device, and since the diameter as a whole has the standard size of the initial state, it is possible to use the manufacturing device that handles the standard size, eliminating the semiconductor material, that is, minimizing the waste. It can be limited.

〔実施例〕〔Example〕

第2図を参照して本発明の一例をその理解を容易にす
るためにその製造方法の一例とともに説明する。まず、
第2図Aに示すようにそれぞれ例えば単結晶シリコン半
導体よりなる第1及び第2の半導体基板(1)及び
(2)を例えば酸化処理を伴うSiO2酸化膜(5)の介存
によって周知の技術によって一体に接合合体する。そし
て、この接合合体された半導体基板の一方例えば図にお
いては第1の基板(1)上に第4図で説明した隙間なし
いは段差(4)の排除等に必要な幅W1に相当する外周端
からの幅Wを残して全表面にフォトレジスト等のエッチ
ングマスク(6)を被着する。
An example of the present invention will be described together with an example of a manufacturing method thereof in order to facilitate understanding thereof with reference to FIG. First,
As shown in FIG. 2A, the first and second semiconductor substrates (1) and (2) each made of, for example, a single crystal silicon semiconductor are known by the presence of an SiO 2 oxide film (5) accompanied by, for example, an oxidation treatment. It is joined and united by a technique. One of the joined semiconductor substrates, for example, corresponds to the width W 1 necessary for eliminating the gap or the step (4) described in FIG. 4 on the first substrate (1) in the figure. An etching mask (6) such as a photoresist is deposited on the entire surface, leaving a width W from the outer peripheral edge.

その後、第2図Bに示すようにエッチングマスク
(6)をマスクとして、これによって覆われていない部
分の基板(1)の表面に形成されているSiO2酸化膜
(5)を例えば異方性エッチング例えば反応性イオンチ
エッチング(RIE)によって基板(1)の基板(2)と
接合される側とは反対側の主面の周辺部のSiO2酸化膜
(5)をエッチング除去する。
Then, as shown in FIG. 2B, the SiO 2 oxide film (5) formed on the surface of the substrate (1) which is not covered with the etching mask (6) is used as an anisotropy. Etching, for example, reactive ion etching (RIE), the SiO 2 oxide film (5) on the peripheral portion of the main surface of the substrate (1) opposite to the side bonded to the substrate (2) is removed by etching.

次に、第2図Cに示すように絶縁層の除去されたシリ
コン基板(1)をその外周端において幅Wをもって化学
的エッチング等によって排除する。例えばKOH水溶液で
エッチングする。この場合、このエッチング液のSiとSi
O2とに対するエッチング速度RsiとRsio2との比、Rsi/Rs
io2=103〜104であることから、基板(1)側からのエ
ッチングが両基板(1)及び(2)間のSiO2酸化膜
(5)に達するとき、急激にそのエッチングの進行度が
低下してそのエッチングが実質的に停止するので、この
時そのエッチング作業をやめれば、基板(1)について
のみ、SiO2酸化膜(5)によって覆われていない周辺部
が幅Wに相当する幅をもってエッチング除去され隙間な
いしは段差(4)の排除がなされ基板(2)について
は、初期状態の径のまま残される。つまり、基板(1)
及び(2)の接合合体された基板(3)の全体的な直径
は、エッチングされない第2の基板(2)の外径によっ
て設定されるので、この外径が例えば6インチのものを
使用する場合においては、最終的に得た半導体基板
(3)においてもその外径は6インチとなり、6インチ
基準サイズの基板を取り扱う半導体装置の製造用の取り
扱い装置を使用することができる。
Next, as shown in FIG. 2C, the silicon substrate (1) from which the insulating layer has been removed is removed by chemical etching or the like with a width W at the outer peripheral edge thereof. For example, etching is performed with a KOH aqueous solution. In this case, Si and Si
The ratio of the etching rate Rsi and RSiO 2 against the O 2, Rsi / Rs
Since io 2 = 10 3 to 10 4 , when the etching from the substrate (1) side reaches the SiO 2 oxide film (5) between both substrates (1) and (2), the etching progresses rapidly. However, if the etching operation is stopped at this time, only the substrate (1) has a width W corresponding to the peripheral portion not covered with the SiO 2 oxide film (5). The width of the substrate (2) is removed by etching to remove the gap or step (4), and the diameter of the substrate (2) is left as it is. That is, the substrate (1)
Since the overall diameter of the bonded and combined substrate (3) of (2) and (2) is set by the outer diameter of the second substrate (2) which is not etched, this outer diameter is used, for example, 6 inches. In this case, the finally obtained semiconductor substrate (3) also has an outer diameter of 6 inches, and a handling device for manufacturing a semiconductor device handling a 6-inch standard size substrate can be used.

上述の第2図の例においては、第1及び第2の半導体
基板(1)及び(2)が絶縁層の介存によって接合する
態様をとる場合についての例を示したが、第1及び第2
の基板(1)及び(2)が直接的に鏡面接合されるよう
にした接合態様をとる場合に本発明を適用することもで
き、この場合の一例を第3図を参照してその理解を容易
にするために製造方法とともに説明する。この場合にお
いても、例えばシリコン単結晶体よりなる第1及び第2
の半導体基板(1)及び(2)を周知の直接的接合、す
なわち両基板(1)及び(2)の接合面を鏡面平坦化
し、両者を合わせた状態で所要の温度に加熱することに
よって第3図Aに示すように、両基板(1)及び(2)
の接合合体基板を作製する。
In the example of FIG. 2 described above, an example is shown in which the first and second semiconductor substrates (1) and (2) are joined by the interposition of the insulating layer. Two
The present invention can be applied to the case where the substrates (1) and (2) are directly mirror-bonded to each other. An example of this case can be understood with reference to FIG. For ease of explanation, the manufacturing method will be described. Also in this case, for example, the first and second silicon single crystal bodies are used.
The well-known direct bonding of the semiconductor substrates (1) and (2), that is, the bonding surfaces of the two substrates (1) and (2) are mirror-planarized, and both are combined and heated to a required temperature. As shown in FIG. 3A, both substrates (1) and (2)
A bonded united substrate is manufactured.

次に、この例においては第3図Bに示すように両基板
(1)及び(2)が合体された基板の表面を例えば熱酸
化してSiO2等の酸化膜(5)を形成する。その後、第2
図Bで説明したと同様にエッチングマスク(6)を基板
(1)上の外周端より幅Wを除いて内側に全面的に被着
し、第3図Cに示すようにエッチング処理を施して基板
(1)の表面の酸化膜(5)を選択的にエッチング除去
する。
Next, in this example, as shown in FIG. 3B, the surface of the substrate on which both substrates (1) and (2) have been combined is thermally oxidized to form an oxide film (5) such as SiO 2 . Then the second
Similarly to the case described with reference to FIG. B, the etching mask (6) is entirely deposited on the inner side of the outer peripheral edge of the substrate (1) except for the width W, and the etching treatment is performed as shown in FIG. 3C. The oxide film (5) on the surface of the substrate (1) is selectively removed by etching.

次に、第3図Dに示すように基板(1)の酸化膜
(5)が除去された部分からKOH等のエッチング液によ
ってエッチングを例えば基板(2)の一部に跨るように
すなわち基板(1)及び(2)の接合面を横切る位置ま
でかつ基板(2)をできるだけ大なる厚さをもって残す
ようにエッチングする。
Next, as shown in FIG. 3D, the portion of the substrate (1) from which the oxide film (5) has been removed is etched by an etching solution such as KOH so as to extend over a part of the substrate (2), that is, the substrate (2). The substrate (2) is etched to the position where it crosses the joining surface of (1) and (2) and leaving the substrate (2) as thick as possible.

このようにすれば第1及び第2の基板(1)及び
(2)が接合された半導体基板(3)が得られ、両基板
(1)及び(2)間に生ずる外周端の隙間の段差(4)
が排除され、全体としては基板(2)の外周径によって
決まる外径寸法を有する前述したと同様の半導体基板
(3)を得ることができる。
In this way, the semiconductor substrate (3) in which the first and second substrates (1) and (2) are joined is obtained, and the step difference in the gap at the outer peripheral edge between the two substrates (1) and (2) is obtained. (4)
Can be eliminated, and the same semiconductor substrate (3) as described above having an outer diameter dimension as a whole determined by the outer diameter of the substrate (2) can be obtained.

尚、第2図及び第3図で説明した例においては基板
(1)に対する外周端のエッチングを化学的エッチング
によって行う場合について説明したが、これを基板
(1)に対する外周端の切除をラッピング等による機械
的研磨、ダイヤモンドカップホイール等による機械的研
削、ダイヤモンドバイト等による機械切削方法によって
排除するようにすることもできる。
In the examples described with reference to FIGS. 2 and 3, a case has been described in which the outer peripheral edge of the substrate (1) is etched by chemical etching, but this is cut by lapping the outer peripheral edge of the substrate (1). It is also possible to eliminate it by mechanical polishing with, a mechanical grinding with a diamond cup wheel or the like, or a mechanical cutting method with a diamond bite or the like.

〔発明の効果〕〔The invention's effect〕

上述したように本発明によれば、第1及び第2の基板
(1)及び(2)の接合によって半導体基板(3)を構
成するものであるが、第1の基板(1)についてのみそ
の外周端を切除して半導体装置の製造において問題とな
る基板(1)及び(2)の接合外周部における隙間等の
不要部分の排除を行うようにし、全体としては初期の状
態における直径すなわち規格の標準サイズの直径の基板
として形成するので半導体材料の無駄を最小限に留める
ことができ、しかも標準サイズの半導体基板を取り扱う
半導体製造装置を適用することができるのでコスト高を
招来することなく目的とする半導体装置を得ることがで
き例えば接合型半導体基板を適用するパワーないしは高
耐圧半導体装置、あるいはSOI型集積回路等に本発明を
適用してその工業的利益は甚大である。
As described above, according to the present invention, the semiconductor substrate (3) is formed by bonding the first and second substrates (1) and (2), but only the first substrate (1) is The outer peripheral edge is cut off to eliminate unnecessary portions such as gaps in the outer peripheral portion of the bonding of the substrates (1) and (2), which poses a problem in the manufacture of the semiconductor device. Since it is formed as a substrate of a standard size diameter, it is possible to minimize the waste of semiconductor materials, and since it is possible to apply a semiconductor manufacturing apparatus that handles a standard size semiconductor substrate, it is possible to achieve the objective without increasing the cost. The present invention is applied to a power or high breakdown voltage semiconductor device to which a junction type semiconductor substrate is applied, or an SOI type integrated circuit, etc. It is enormous.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明による半導体基板の一例の略線的断面
図、第2図は本発明による半導体基板の一例のその説明
に供する製造工程図、第3図は本発明基板の他の例のそ
の説明に供する製造工程図、第4図は従来基板の要部の
略線的拡大断面図である。 (1)は第1の半導体基板、(2)は第2の半導体基
板、(3)は第1及び第2の半導体基板の合体による半
導体基板である。
1 is a schematic cross-sectional view of an example of a semiconductor substrate according to the present invention, FIG. 2 is a manufacturing process diagram for explaining the example of a semiconductor substrate according to the present invention, and FIG. 3 is another example of a substrate of the present invention. FIG. 4 is a manufacturing process diagram used for the explanation, and FIG. (1) is a first semiconductor substrate, (2) is a second semiconductor substrate, and (3) is a semiconductor substrate obtained by combining the first and second semiconductor substrates.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】第1及び第2の半導体基板が貼り合わされ
てなり、かつ少くとも上記第1の半導体基板の外周端
が、上記第2の半導体基板の外周端より内側にあること
を特徴とする半導体基板。
1. A first semiconductor substrate and a second semiconductor substrate are bonded together, and at least the outer peripheral edge of the first semiconductor substrate is inside the outer peripheral edge of the second semiconductor substrate. Semiconductor substrate.
JP62245014A 1987-09-29 1987-09-29 Semiconductor substrate Expired - Lifetime JP2535957B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245014A JP2535957B2 (en) 1987-09-29 1987-09-29 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245014A JP2535957B2 (en) 1987-09-29 1987-09-29 Semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS6489346A JPS6489346A (en) 1989-04-03
JP2535957B2 true JP2535957B2 (en) 1996-09-18

Family

ID=17127292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245014A Expired - Lifetime JP2535957B2 (en) 1987-09-29 1987-09-29 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JP2535957B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7208058B2 (en) 2003-06-09 2007-04-24 Sumitomo Mitsubishi Silicon Corporation SOI substrate and manufacturing method thereof

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0719737B2 (en) * 1990-02-28 1995-03-06 信越半導体株式会社 Manufacturing method of S01 substrate
JP2565440B2 (en) * 1991-09-30 1996-12-18 信越半導体株式会社 Method for manufacturing SOI substrate
JPH10223497A (en) * 1997-01-31 1998-08-21 Shin Etsu Handotai Co Ltd Manufacture of laminated substrate
JP3635200B2 (en) * 1998-06-04 2005-04-06 信越半導体株式会社 Manufacturing method of SOI wafer
JP2004281878A (en) * 2003-03-18 2004-10-07 Seiko Epson Corp Method for manufacturing semiconductor substrate, semiconductor substrate to be manufactured by the method, electro-optical device, and electronic apparatus
FR2860842B1 (en) * 2003-10-14 2007-11-02 Tracit Technologies PROCESS FOR PREPARING AND ASSEMBLING SUBSTRATES
FR2899594A1 (en) 2006-04-10 2007-10-12 Commissariat Energie Atomique METHOD FOR ASSEMBLING SUBSTRATES WITH THERMAL TREATMENTS AT LOW TEMPERATURES
JP2009071128A (en) * 2007-09-14 2009-04-02 Naoetsu Electronics Co Ltd Method of manufacturing semiconductor-bonded wafer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54116888A (en) * 1978-03-03 1979-09-11 Hitachi Ltd Manufacture of dielectric separate substrate
JPS61144839A (en) * 1984-12-18 1986-07-02 Toshiba Corp Bonding method for semiconductor wafer
JPS61256621A (en) * 1985-05-08 1986-11-14 Toshiba Corp Production of bound-type semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54116888A (en) * 1978-03-03 1979-09-11 Hitachi Ltd Manufacture of dielectric separate substrate
JPS61144839A (en) * 1984-12-18 1986-07-02 Toshiba Corp Bonding method for semiconductor wafer
JPS61256621A (en) * 1985-05-08 1986-11-14 Toshiba Corp Production of bound-type semiconductor substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7208058B2 (en) 2003-06-09 2007-04-24 Sumitomo Mitsubishi Silicon Corporation SOI substrate and manufacturing method thereof

Also Published As

Publication number Publication date
JPS6489346A (en) 1989-04-03

Similar Documents

Publication Publication Date Title
KR101291086B1 (en) Method for trimming a structure obtained by the assembly of two plates
JPH0719737B2 (en) Manufacturing method of S01 substrate
JPH0719739B2 (en) Bonded wafer manufacturing method
JPH0636414B2 (en) Manufacturing method of semiconductor element forming substrate
JP2535957B2 (en) Semiconductor substrate
JPH06112451A (en) Manufacture of soi substrate
JPH10223497A (en) Manufacture of laminated substrate
JPH0917984A (en) Bonded soi substrate manufacturing method
JP2662495B2 (en) Method for manufacturing bonded semiconductor substrate
JPH0485827A (en) Manufacture of semiconductor device
JP3352129B2 (en) Semiconductor substrate manufacturing method
JPH07297377A (en) Semiconductor device and manufacture thereof
JP2000243942A (en) Semiconductor substrate and manufacture thereof
US5214001A (en) Method of manufacturing semiconductor device having planar single crystal semiconductor surface
JPH05226305A (en) Manufacture of laminated wafer
JP2000030993A (en) Manufacture of soi wafer and soi wafer
JP2779659B2 (en) Method for manufacturing semiconductor device
JPS62132324A (en) Removing method for chamfered grinding damage layer of wafer and removing jig
JPH0389519A (en) Manufacture of semiconductor substrate
JPH01305534A (en) Manufacture of semiconductor substrate
JP2857456B2 (en) Method for manufacturing semiconductor film
JP3996557B2 (en) Manufacturing method of semiconductor junction wafer
JPS63127531A (en) Manufacture of semiconductor device
JPS6278829A (en) Manufacture of semiconductor device
JPH09162087A (en) Production of laminated substrate