KR930005240B1 - Tungsten thin film manufacture method using multicrystal silicon buffing level - Google Patents
Tungsten thin film manufacture method using multicrystal silicon buffing level Download PDFInfo
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- KR930005240B1 KR930005240B1 KR1019900002351A KR900002351A KR930005240B1 KR 930005240 B1 KR930005240 B1 KR 930005240B1 KR 1019900002351 A KR1019900002351 A KR 1019900002351A KR 900002351 A KR900002351 A KR 900002351A KR 930005240 B1 KR930005240 B1 KR 930005240B1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 39
- 239000010937 tungsten Substances 0.000 title claims abstract description 39
- 239000010409 thin film Substances 0.000 title claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 6
- 239000010703 silicon Substances 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims abstract description 31
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims abstract description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 3
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
제1a~e도는 종래의 텅스텐 박막 제조의 공정도.1a to e is a process chart of the conventional tungsten thin film production.
제2a~g도는 본 발명에 의한 다결정 실리콘 완충층을 이용한 텅스텐 박막 제조의 공정도.2a to g is a process chart of the production of tungsten thin film using the polycrystalline silicon buffer layer according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 소자 2 : 산화막1: silicon element 2: oxide film
3 : 접착성 향상층 4 : 텅스텐 박막3: adhesion improvement layer 4: tungsten thin film
5 : 폴리막 6 : 접촉창5: poly film 6: contact window
본 발명은 텅스텐 박막 제조방법에 관한 것으로 특히 고밀도 집적을 필요로 하는 VLSI, ULSI 급의 소자에 적당하도록 한 다결정 실리콘 완충층을 이용한 텅스텐 박막 개조방법에 관한 것이다.BACKGROUND OF THE
종래의 텅스텐 박막 제조방법을 첨부된 도면 제1a~e도를 참조하여 설명하면 다음과 같다.A conventional tungsten thin film manufacturing method will be described with reference to the accompanying drawings, FIGS. 1A through E.
웨이퍼를 제작한 후 금속과 전도성층을 격리시키기 위하여 산화막(2 ; BPSG, PSG)을 실리콘 소자(1)위에 증착시키는 산화막 증착공정을 한후(제1a도 참조), 금속과 실리콘 또는 금속과 금속을 연결하기 위하여 접촉창(6 ; Contact)을 사진 식각법에 의하여 형성하는 접촉창 마스크 식각 공정을 하고(제1b도 참조), 텅스텐과 산화물의 접착성은 좋지 못하므로 산화막 위에 형성된 텅스텐 박막이 산화막으로 부터 분리되며 불순한 입자로 존재하여 수율저하를 초래하게 되는데 이와같은 수율저하의 초래를 방지하기 위하여 텅스텐 박막과 산화막의 접착성을 향상시킬 수 있는 티타늄 나이트라이드(TiN), 티타늄 텅스텐(TiW), 메탈 실리사이드(Metal Silicide)등으로 접착성 향상층(3)을 입히는 접착성 향상층 형성공정을 하고(제1c도 참조), 가스(WF6-H2, WF6-SiH4)의 조합에 의하여 상기 공정을 거친 웨이퍼의 전면에 균일하게 텅스텐 박막(4)을 입히는 전면 텅스텐 박막부공정을 하고(제1d도 참조), 접촉창(6)의 내부에만 텅스텐 박막(4)을 남기고 그외의 텅스텐 박막을 제거하기 위하여 식각을 하는 건식 식각 공정을 하는데(제1e도 참조), 상기 공정을 거쳐 텅스텐 박막을 만들게 된다.After the wafer is fabricated, an oxide film deposition process is performed in which an oxide film (2; BPSG, PSG) is deposited on the
그러나 상기 설명된 종래의 텅스텐 박막 제조방법은 텅스텐 박막(4)과 산화막(2)의 사이에 접착성 향상층(3)을 형성시키므로 텅스텐 박막이 실리콘 산화막 및 질화막에 대하여 접착이 잘되지 않는 것을 개선하려 하였으나 이들은 웨이퍼의 앞면에만 형성시키게 되므로 텅스텐 박막(4)을 입히는 과정중에 웨이퍼의 뒷면에 형성된 텅스텐에 대해서는 접착성을 향상시키는 작용을 할 수 없으므로, 웨이퍼 뒷면의 텅스텐들이 떨어지게 되어 반도체 공정중 수율을 저하시키게 되고, 또한 텅스텐 박막(4)은 표면이 매우 거칠음에도 불구하고 전면 막박부 공정의 후에 건식 식각공정을 하게 되므로 텅스텐 박막(4)의 거칠은 표면정도가 그대로 산화막(2)의 표면으로 전달되므로 이어지는 공정들을 어렵게하는 문제점이 있었다.However, the conventional tungsten thin film manufacturing method described above forms an
본 발명은 상기한 문제점을 해결하기 위하여 안출되었으며, 그의 제조방법을 첨부된 도면 제2a~g도를 참조하여 설명하면 다음과 같다.The present invention has been made in order to solve the above problems, it will be described with reference to the accompanying drawings, the manufacturing method 2a ~ g as follows.
금속과 그 아래의 전도성층을 격리시키기 위하여 산화막(2 ; BPSG, PSG)을 입히는 산화막부 공정을 하고(제2a도 참조), 웨이퍼의 앞면과 뒷면에 폴리막(5)을 충분히 입히는 폴리부 공정을 하고(제2b도 참조), 금속과 실리콘, 금속과 금속을 연결하기 위하여 사진 식각법에 의하여 접촉창(6)을 형성하는 접촉창 형성공정을 하고(제2c도 참조), 접착성을 향상시키기 위하여 박막을 입히는 접착성 향상층 형성 공정을 하고(제2d도 참조), 웨이퍼의 전면에 텅스텐 박막(4)을 입히는 전면 텅스텐 증착 공정을 하고(제2e도 참조), 접촉창(6)의 내부 텅스텐만 남기고 그외의 텅스텐을 제거하기 위하여 건식 식각을 하는 건식식각 공정을 하고(제2f도 참조), 상기 폴리부공정시 완충용으로 사용된 폴리막(5)을 산화막(2)에 영향을 적게 주면서 없앨 수 있는 용액(HNO3, CH3COOH, HF 혼합액)을 사용하여 폴리막(5)을 제거하는 폴리 실리콘 제거 공정을 하게 되는데(제2g도 참조), 상기 공정을 거쳐 텅스텐 박막 공정을 하게 된다.An oxide film process for coating an oxide film (2; BPSG, PSG) to isolate the metal and the conductive layer below it (see FIG. 2a), and a polycoat process for sufficiently coating the poly film 5 on the front and back surfaces of the wafer. (See FIG. 2b), and a contact window forming process for forming the contact window 6 by photolithography to connect the metal and the silicon and the metal and the metal (see FIG. 2c), and improve adhesion. A film-forming adhesive enhancement layer forming process is performed (see FIG. 2D), a front-side tungsten deposition process is applied to the entire surface of the wafer (see FIG. 2E), and the contact window 6 A dry etching process is performed in which dry etching is performed to remove other tungsten, leaving only the internal tungsten (see FIG. 2f), and the poly film 5 used as a buffer during the poly-sub-process is applied to the
따라서 본 발명에 의한 텅스텐 박막 제조방법은 폴리부 공정시 폴리막을 사용하고, 텅스텐의 건식 식각공정시 폴리막(5)이 제거되도록 하여 텅스텐의 표면거칠기가 산화막에 전달되지 않도록 하므로 계속 이어지는 공정들을 쉽게 할 수 있고, 또한 폴리부공정시 웨이퍼의 뒷면에도 폴리막(5)이 덮히게 되므로 공정중 텅스텐이 웨이퍼로 부터 떨어지지 않게 되어 수율을 향상시키는 효과를 갖게 된다.Therefore, the method for manufacturing a tungsten thin film according to the present invention uses a poly film during the poly part process, and the poly film 5 is removed during the dry etching process of tungsten so that the surface roughness of the tungsten is not transferred to the oxide film. In addition, since the poly film 5 is also covered on the back surface of the wafer during the poly part process, tungsten does not fall from the wafer during the process, thereby improving the yield.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019900002351A KR930005240B1 (en) | 1990-02-23 | 1990-02-23 | Tungsten thin film manufacture method using multicrystal silicon buffing level |
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| KR1019900002351A KR930005240B1 (en) | 1990-02-23 | 1990-02-23 | Tungsten thin film manufacture method using multicrystal silicon buffing level |
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| KR930005240B1 true KR930005240B1 (en) | 1993-06-16 |
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