JPS5852830A - High withstand voltage semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device having high withstand voltage, high reliability and moreover having the high current amplification factor according to an extremely simple passivation process by a method wherein windows are opened at the prescribed parts of a passivation film having three layers structure using etchants corresponding respectively to a silicon oxide film and to a polycrystalline silicon film. CONSTITUTION:The silicon oxide film 15 at the part to expose the main rectification junction Jc on the surface is etched to be removed with the mixed liquid of fluoric acid and ammonium fluoride at first, and moreover etching is performed with the mixed liquid of fluoric acid and nitric acid to remove the distortion layer on the surface of a silicon single crystal substrate 10. A silicon oxide film 17 is etched similarly with the mixed liquid of fluoric acid and ammonium fluoride, then a polycrystalline silicon film 16 is etched with the mixed liquid of fluoric acid, nitric acid and acetic acid, and the silicon oxide film 15 is etched once more with the liquid mentioned above. Accordingly etching of the polycrystalline silicon film 16 with the mixed liquid of fluoric acid, nitric acid and acetic acid can be stopped by the silicon oxide film 15 existing thereunder, and contact holes 18, 19 can be opened applying no damage to the silicon single crystal substrate 10, especially to high concentration diffusion layers 12, 13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage semiconductor device and its manufacturing method, and particularly to a highly reliable bancivation structure using a polycrystalline silicon film.

There is a passivation method using a polycrystalline silicon film as a surface protection film for a pn junction of a silicon semiconductor element. A semi-insulating polycrystalline silicon film that is doped with oxygen or nitrogen to increase its resistivity generates less strain and has a low surface state density.

It is highly reliable by shielding the influence of external charges, has good mass productivity, and is applied to various semiconductor devices. However, the passivation method using a polycrystalline silicon film has problems in that selective etching is difficult in terms of process and in terms of device characteristics, the current amplification factor hFE of the transistor is reduced. That is, selective etching is required to form contact holes after the bubbling process of the polycrystalline silicon film, but since the polycrystalline silicon film requires the same etchant as the silicon single crystal substrate (semiconductor element), it is not suitable for single crystal substrates. It is difficult to stop etching at the boundary. Too much or too little amount of etching will cause electrode contact failure. For this reason, both the composition of the polycrystalline silicon film and the etching method have been studied, but it is extremely difficult to selectively etch a polycrystalline silicon film with a low dopant concentration that is effective even with a trowel in view of device characteristics. On the other hand 1. The decrease in the current amplification factor hFE of the transistor is caused by the large leakage current in the passivation film on the surface of the emitter junction.

As a countermeasure for this, methods have been proposed for passivation of the emitter junction, such as using a thermal oxide film or removing the polycrystalline silicon film and then covering it with a silicon oxide film using a gas phase reaction. The process is complicated due to the problem of selective etching of the film.

An object of the present invention is to provide a high voltage semiconductor device passivated with a polycrystalline silicon film, which is characterized by high voltage resistance and high reliability, has a high current amplification factor, and is easy to manufacture, and a method for manufacturing the same.

The present invention is characterized by removing the silicon oxide film in the portion where the main rectifying junction is exposed to the surface of the silicon single crystal substrate after the diffusion process is completed, and removing the silicon oxide film in the portion where the contact region and the emitter junction are exposed to the surface. After leaving the film, a polycrystalline silicon film and a silicon oxide film are sequentially formed on the surface of the silicon single crystal substrate, and contact holes are formed at predetermined positions through the silicon oxide film, polycrystalline silicon, and silicon oxide film, and the exposed silicon single crystal substrate is The purpose is to contact the electrode with the

The present invention will be described in detail below based on drawings showing embodiments.

FIG. 1(a) is a schematic cross-sectional view of a state in which the diffusion process for obtaining an npn planar transistor with a breakdown voltage of 1600V has been completed. Resistivity is 90-1000m, thickness is 28
A silicon single crystal substrate 10 with a thickness of 0 μm has a phosphorus diffusion layer 11 for a highly concentrated collector, a poron diffusion layer 12 for a base with a depth of 35 μm, and a phosphorus diffusion layer 13 for an emitter with a depth of 10 μm.
was formed. A p+ guard ring layer 14 is formed around the base layer 12 to reduce the electric field strength during reverse bias of the main rectifying junction Jc which maintains a breakdown voltage. A silicon oxide film 15 is formed on the surface of the silicon single crystal substrate 10 by diffusion heat treatment.

In FIG. 1(b), the part of the silicon oxide film 15 where the main rectifying junction Jc is exposed to the surface is etched away using a mixed solution of ammonium fluoride and fluoride, and the strained layer on the surface of the silicon single crystal substrate 10 is further removed. The state shown is etched with a hydrofluoric acid/nitric acid mixture. The region where the silicon oxide film 15 is removed is a region where the end of the region where the depletion layer expands when the main rectifying junction Jc is reverse biased is exposed to the surface.

FIG. 1C shows a state in which a polycrystalline silicon film 16 and a silicon oxide film 17 are sequentially formed on the surface of the silicon single crystal substrate 10 and baked. Here, polycrystalline silicon film 16
is formed by a gas phase reaction using monosilane and nitrous oxide at 630-640C, contains 20% (atomic ratio) of oxygen, and has a thickness of about 0.5. It is um. The silicon oxide film 17 is 380
It is formed by a gas phase reaction using monosilane and oxygen at ~410C, and has a thickness of about 0.2 μm. Polycrystalline silicon 16 and silicon oxide film 17 can be successively formed in the same gas phase reactor. The baking process was performed at 950C for 130 minutes in a nitrogen stream.

Figure 1(d) shows the pattern for the emitter and base electrodes.
.

The three layers of silicon oxide film 17, polycrystalline silicon film 16 and silicon oxide film 15 are photo-etched to form contact holes 18 and 19'i.

t f - / IJ Con Oxide Film 172ii - Hydrofluoric acid/ammonium fluoride mixed solution (capacity ratio of 1:6), then polycrystalline silicon film was treated with hydrofluoric acid/nitric acid/acetic acid mixed solution (1:2:
The silicon oxide film 15 was etched once again with the above solution at a capacitance ratio of 6). With this method, the etching of the polycrystalline silicon film 16 by the hydrofluoric acid/nitric acid/acetic acid mixture can be stopped at the underlying silicon oxide film 15, without damaging the silicon single crystal substrate 10, especially the high concentration diffusion layers 12 and 13. I was able to open contact holes 18 and 19.

FIG. 1(e) shows a state in which a base electrode 20 and an emitter electrode 21 are formed by the lift-off method. The electrode materials are chromium, nickel, and silver deposited in sequence, and then 47
Heat treatment was performed in a 5C nitrogen stream for sintering and lift-off.

Thereafter, as in the conventional assembly process, the transistor is completed through pelletizing, mounting on a heat sink, soldering of emitter electrodes and heat sink electrodes, and packaging.

FIG. 2 shows the relationship between the collector current Ic of the transistor and the current amplification factor hFE. The curved person is according to the present invention,
Curve B is based on the conventional method in which the entire surface of the semiconductor substrate, that is, the emitter junction is also passivated with a polycrystalline silicon film. In the conventional method, the hrg was significantly lowered, but in the semiconductor device of the present invention, hFK similar to that of the thermal oxide film-phosphorus glass film passivation was obtained. Further, the transistor according to the present invention has a collector-emitter breakdown voltage of B
VCEO is 1850V at temperature 150C and leakage current 0.1 mA, DC 1600V at 150C 11000 hours.
There was no change in leakage current even in the blocking test.

FIG. 3 shows a schematic cross-sectional view of a Brener-type thyristor 30 having a withstand voltage of 600 V according to the present invention. The diffusion process similar to that of the conventional Brenna type thyristor has been completed, and the P emitter layer 31,
After forming the n base layer 32, the p base layer 33, and the n emitter layer 34, a part of the thermal oxide film 35 formed in the diffusion process is removed, and a polycrystalline silicon film 36. A silicon oxide film 37 was formed. Here, the main rectifying junctions are 38 and 39 that maintain voltage resistance in both the reverse and forward directions.

A polycrystalline silicon film 36 is deposited directly on the portion where the region where the depletion layer spreads during reverse bias of this junction is exposed to the surface. On the other hand, the junction 4 between the n emitter layer 34 and the p base layer 33
The surface of 0 is a silicon oxide film 35/polycrystalline silicon film 3
6-It has a three-layer structure of silicon oxide film 37. The cathode and gate electrodes 41 and 42 were formed by photoetching a passivation film having a 3Ji structure, and then forming an aluminum vapor deposition film by a lift-off method.

FIG. 4 shows the distribution of gate trigger current of the Brainer type thyristor shown in FIG. The graph of group a is based on the present invention, and has high sensitivity and small variation. For comparison, the graph of group b is a graph in which the entire surface of a silicon single crystal substrate was directly passivated with a polycrystalline silicon film according to a conventional method. Thyristor gate sensitivity is poor and variation is large. This is because the sensitivity deteriorates due to leakage current in the passivation film, and also because the end point cannot be clearly determined when etching the polycrystalline silicon film to form contact holes, resulting in variations in etching on the surface of the p-paste layer. .

As described above, according to the present invention, a semiconductor device with high breakdown voltage, high reliability, and high current amplification factor can be manufactured using an extremely -Uu+i passivation process.

Similarly, in the present invention, the same effect can be obtained even if the conductivity type of each layer of the transistor and thyristor shown in FIGS. 1 and 3 is reversed.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are schematic cross-sectional views showing each manufacturing process of a high-voltage semiconductor device according to an embodiment of the present invention, and FIG. 2 shows the characteristics of the high-voltage semiconductor device shown in FIG. FIG. 3 is a cross-sectional schematic diagram showing a high voltage semiconductor device according to another embodiment of the present invention, and FIG.
FIG. 2 is a comparison diagram of the characteristics of the high voltage semiconductor device shown in the figure and the conventional semiconductor device. DESCRIPTION OF SYMBOLS 10...Silicon single crystal base, 11...High concentration phosphorus diffusion layer for collector, 12...Boron diffusion layer for base. 13... Phosphorus diffusion layer for emitter, 14... P+ guard ring layer, 15... Silicon oxide film, 16... Polycrystalline silicon film, 17... Silicon oxide film, 18.1
9... Contact hole, 20... Base i [pole,
21... Emitter electrode, Jc... Main rectifier junction.鵠 tn '1/J 2 Figure n t / /D Kore 77 current rccA) No. J Figure 1,! ! mouth υ

Claims (1)

[Claims] 1. A silicon single crystal substrate exposed on the main surface of the main rectifying junction that maintains withstand voltage, an exposed portion %-fl of the main rectifying junction of the silicon single crystal substrate; Silicon oxide film, the above-mentioned -.11 dielectric film and the exposed part of the main rectifying junction VCU, the kt polycrystalline 11.1 silicon film, the above-mentioned polycrystalline silicon〉ν opening a window in a predetermined portion of a passivation film having a three-layer structure consisting of the silicon oxide film No. 2, the first silicon oxide film, the polycrystalline silicon film, and the silicon oxide film No. 2 to expose the silicon single crystal substrate; A high breakdown voltage semiconductor device characterized by contacting an electrode from here. 2. A step of diffusing impurities into a silicon single crystal substrate so that a main rectifying junction that maintains a breakdown voltage is exposed on one main surface of the silicon single crystal substrate. a step of providing a first silicon oxide film except for the exposed portion of the rectifying junction; a step of providing a polycrystalline silicon film on the exposed portion of the main rectifying junction and the first silicon oxide film; Step 2 of providing a silicon oxide film, a predetermined portion of the passivation film having a three-layer structure of the first silicon oxide film, a polycrystalline silicon film, and a second silicon oxide film, to each of the silicon oxide film and the polycrystalline silicon film. 1. A method for manufacturing a high voltage semiconductor device, comprising the steps of: opening a window using an Elachantra; and contacting an electrode to the silicon single crystal substrate exposed by the window opening.