JPS6156617B2 - - Google Patents
Info
- Publication number
- JPS6156617B2 JPS6156617B2 JP3886277A JP3886277A JPS6156617B2 JP S6156617 B2 JPS6156617 B2 JP S6156617B2 JP 3886277 A JP3886277 A JP 3886277A JP 3886277 A JP3886277 A JP 3886277A JP S6156617 B2 JPS6156617 B2 JP S6156617B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- groove
- mesa
- photoresist film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000008188 pellet Substances 0.000 claims description 9
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010959 steel Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000002779 inactivation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Dicing (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、特に
メサ型半導体装置に於いて、露出したP−N接合
を硝子で被覆した半導体装置の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device in which an exposed PN junction in a mesa type semiconductor device is covered with glass.
従来のメサ型半導体装置はPN接合形成後、化
学エツチング法によつて、メサ溝を形成し、この
溝側面に接合端を露出し、これを適当な絶縁膜に
て被覆し、半導体基板表面を不活性化にすること
は半導体装置の信頼性を高める上で非常に重要で
あり、いわゆるパツシベイテツド・メサ型が多く
用いられてきた。 In conventional mesa-type semiconductor devices, after forming a PN junction, a mesa groove is formed using a chemical etching method, the junction end is exposed on the side surface of this groove, and this is covered with an appropriate insulating film to cover the semiconductor substrate surface. Inactivation is very important in increasing the reliability of semiconductor devices, and so-called passivated mesa types have been widely used.
このような、絶縁膜を被覆せしめたメサ溝を有
する半導体装置をメサ溝に沿つて半導体ペレツト
を破断分離する際は、一般的にレーザービームに
よつてメザ溝部の絶縁膜を通して半導体基板部に
切削溝を形成した後、鋼製ローラ等により押圧し
て前記の切削溝から切断して半導体ペレツトが得
られるのである。 When a semiconductor device having such a mesa groove covered with an insulating film is separated by fracture along the mesa groove, a laser beam is generally used to cut the semiconductor substrate through the insulating film in the mesa groove. After the grooves are formed, semiconductor pellets are obtained by pressing with a steel roller or the like and cutting from the grooves.
しかしながら、前記切削溝を形成した半導体基
板を鋼製ローラ等により押圧する際に、相隣接す
る半導体ペレツト相互間で接触が起り、これによ
つて絶縁膜にクラツクやカケ等を生じせしめる。 However, when the semiconductor substrate with the cut grooves formed thereon is pressed by a steel roller or the like, contact occurs between adjacent semiconductor pellets, thereby causing cracks, chips, etc. in the insulating film.
この為、外観不良が多発し、歩留を低下させた
り後の電気的特性チエツクで高耐圧特性やリーク
電流の劣化が顕著となり、その結果信頼度が低下
するという欠点を有している。 For this reason, defects in appearance occur frequently, which lowers yield, and deterioration of high voltage characteristics and leakage current becomes noticeable in later electrical characteristic checks, resulting in a decrease in reliability.
上記のような問題点を排除する為に従来は幾つ
かの対策が講じられている。例えば、絶縁膜を被
着せしめたメサ溝以外の半導体基板部に切削溝を
設けることによつて絶縁膜のダメージを避けるこ
とが試みられているが、しかしこの方法を半導体
ペレツトの構造設計上、ペレツトが大型化とな
り、ペレツトの収率が悪く原価高となる欠点を有
している。 Conventionally, several measures have been taken to eliminate the above problems. For example, attempts have been made to avoid damage to the insulating film by providing cutting grooves in parts of the semiconductor substrate other than the mesa grooves covered with the insulating film. This method has the drawback that the pellets become larger, resulting in poor pellet yield and high cost.
本発明はこれら従来技術の欠点を除去した有効
な半導体装置の製造方法を提供することである。 The object of the present invention is to provide an effective method for manufacturing a semiconductor device that eliminates the drawbacks of these conventional techniques.
本発明の特徴は、絶縁膜を被覆したメサ型半導
体基板の全面にフオトレジスト膜を被着せしめた
後、フオトレジスト膜及び絶縁膜を通して半導体
基板にレーザービームによつて切削溝を形成せし
め、その後、フオトレジスト膜をマスクとして、
絶縁膜の熔融部及びビームによつて生じた熱ひず
みやフラツク等を化学エツチング除去したことで
ある。 The feature of the present invention is that after a photoresist film is deposited on the entire surface of a mesa-shaped semiconductor substrate coated with an insulating film, cutting grooves are formed in the semiconductor substrate by a laser beam through the photoresist film and the insulating film, and then , using a photoresist film as a mask,
Thermal strain and flakes caused by the melted part of the insulating film and the beam are removed by chemical etching.
このような製造方法は、レーザビームによる熱
みずみ、クラツク、カケ等を除去してから、各ペ
レツトを切断分離したものであるから、本発明の
半導体装置は高歩留及び信頼度の高いメサ型半導
体装置となる。 In this manufacturing method, each pellet is cut and separated after removing thermal deformities, cracks, chips, etc. caused by the laser beam, so the semiconductor device of the present invention can produce mesas with high yield and high reliability. type semiconductor device.
次に本発明の一実施例を図面により詳細に説明
する。 Next, one embodiment of the present invention will be described in detail with reference to the drawings.
第1図A〜Fは本発明をダイオードに適用した
場合のダイオードの製造工程断面図を示したもの
である。第1図Aに於いて、例えばN導電型のシ
リコン基板1の片面よりP型不純物を拡散して、
P+型領域2を設けPN接合3を形成せしめた後、
熱酸化法によつて酸化膜4を被着する。 FIGS. 1A to 1F are cross-sectional views showing the manufacturing process of a diode in which the present invention is applied. In FIG. 1A, for example, a P-type impurity is diffused from one side of an N-conductivity type silicon substrate 1,
After providing the P + type region 2 and forming the PN junction 3,
An oxide film 4 is deposited by thermal oxidation.
次いで、第1図Bの如く前記酸化膜4にフオト
エツチング法により窓を選択的に形成せしめ、硝
酸及びフツ酸より成る混酸を用いて前記酸化膜4
をマスクとして化学的エツチングを施し、耐圧を
もたらすPN接合3を貫くメサ溝5を形成すると
共にPN接合3を露出する。 Next, as shown in FIG. 1B, windows are selectively formed in the oxide film 4 by photoetching, and the oxide film 4 is etched using a mixed acid consisting of nitric acid and hydrofluoric acid.
Using this as a mask, chemical etching is performed to form a mesa groove 5 that penetrates the PN junction 3 that provides withstand voltage, and to expose the PN junction 3.
次いで、第1図Cの如く前記メサ溝5を有する
シリコン基板表面に硼硅酸を主成分とする硝子粒
子を例えば電気泳効法によつて被着せしめ硝子粒
子層6を形成する。次に第1図Dに於いて、上述
した半導体基板を500〜800℃で約1〜2時間焼成
し、前記硝子粒子層6を熔融し絶縁膜7を形成せ
しめた後、局部的に残存する酸化膜4を希フツ酸
系のエツチング液により選択的に除去した後、電
極形成部の表面及び裏面をサンドブラスト又は化
学エツチ等により軽く処理した後、一般的なメツ
キ法或は蒸着法により金属電極層9と9′を形成
せしめる。 Next, as shown in FIG. 1C, glass particles containing borosilicate as a main component are deposited on the surface of the silicon substrate having the mesa grooves 5 by, for example, electrophoresis to form a glass particle layer 6. Next, in FIG. 1D, the semiconductor substrate described above is fired at 500 to 800° C. for about 1 to 2 hours to melt the glass particle layer 6 and form an insulating film 7, which partially remains. After selectively removing the oxide film 4 with a dilute hydrofluoric acid-based etching solution, the front and back surfaces of the electrode formation area are lightly treated by sandblasting or chemical etching, and then a metal electrode is formed using a general plating method or vapor deposition method. Layers 9 and 9' are formed.
次に前記半導体基板の表裏面の全面にフオトレ
ジスト膜10,10′を被着せしめる。このフオ
トレジスト膜10の被着は、後にレーザービーム
によつて各素子相互間に切削溝を形成するに際
し、切削溝部の熔融絶縁膜の切削部のエツチング
用マスクとして非常に重要である。次に、第1図
Eに於いて、メサ溝5部の絶縁膜7上に被着せし
めたフオトレジスト膜10面から各ダイオード素
子が分離されるが如く、可素子相互間の中心にレ
ーザービームによつて切削溝11を形成せしめ
る。しかし、レーザービームによつて形成された
切削溝11は絶縁膜7或はシリコン基板1等の物
質が熔融した、いわゆる溶融層となつている為、
熱ひずみやクラツク等が多発している。このよう
な絶縁膜中の欠陥は信頼性の低下に結びつく事は
言うまでもない。 Next, photoresist films 10 and 10' are deposited on the entire front and back surfaces of the semiconductor substrate. The deposition of this photoresist film 10 is very important as a mask for etching the cut portions of the molten insulating film in the cut groove portions when cutting grooves are later formed between the respective elements using a laser beam. Next, in FIG. 1E, a laser beam is applied to the center between the diode elements so that each diode element is separated from the surface of the photoresist film 10 deposited on the insulating film 7 in the mesa groove 5. Cutting grooves 11 are formed by the following steps. However, since the cut groove 11 formed by the laser beam is a so-called molten layer in which the material such as the insulating film 7 or the silicon substrate 1 is melted,
Heat strain and cracks are occurring frequently. Needless to say, such defects in the insulating film lead to a decrease in reliability.
次に第1図Fに示すように、前記のフオトレジ
スト膜10をエツチング用マスクとして、例えば
フツ酸及びフツ化アンモニウムの混合液によつて
熔融した絶縁膜の切削溝を選択的にエツチング
し、エツチング溝12を形成せしめる。 Next, as shown in FIG. 1F, using the photoresist film 10 as an etching mask, for example, the cut grooves of the melted insulating film are selectively etched with a mixed solution of hydrofluoric acid and ammonium fluoride. Etching grooves 12 are formed.
次に前記半導体基板上のフオトレジスト膜1
0,10′を熱分解法によつて除去した後、該半
導体基板をこのまま鋼製ローラ等により押圧して
切削溝11から破断せしめれば、第2図に示すよ
うなダイオードペレツトが得られるのである。 Next, the photoresist film 1 on the semiconductor substrate is
After removing 0 and 10' by pyrolysis, the semiconductor substrate is pressed with a steel roller or the like to break it from the cut groove 11, and a diode pellet as shown in FIG. 2 is obtained. It is.
以上のように本発明は、PN接合を有する半導
体基板にメサ溝を形成し、該メサ溝に絶縁膜を被
着せしめ、該絶縁膜上にフオトレジスト膜を形成
する工程と、前記一主面側のフオトレジスト膜の
表面からレーザービームによつてフオトレジスト
膜を通して絶縁膜及び半導体基板部に切削溝を設
ける工程と、前記フオトレジスト膜をマスクとし
て切削溝部の絶縁膜をエツチングして前記切削溝
より破断分離して半導体ペレツトを形成する工程
とを含むものであるから、メサ溝部の絶縁膜にレ
ーザービームにより形成した切削溝部の熱ひずみ
やクラツク、そしてカケ等の欠陥は解消される同
時に、鋼製ローラ等により押圧して半導体基板を
破断分離する際、相隣接する半導体ペレツト相互
間で接触が起つても、絶縁膜相互間での接触が起
きない為、新たに絶縁膜にはクラツクやカケ等が
発生しなくなり、いわゆる外観不良は皆無とな
る。その結果、特性の安定した信頼性の高いメサ
型半導体装置の量産が容易であり、従つて製造原
価も大幅に低減されるという効果が得られる。 As described above, the present invention includes the steps of forming a mesa groove in a semiconductor substrate having a PN junction, depositing an insulating film on the mesa groove, and forming a photoresist film on the insulating film; A step of forming a cutting groove from the surface of the side photoresist film through the photoresist film through the photoresist film into the insulating film and the semiconductor substrate portion, and etching the insulating film in the cut groove portion using the photoresist film as a mask to form the cut groove. Since this process includes the step of further breaking and separating the chips to form semiconductor pellets, defects such as thermal distortion, cracks, and chips in the cut grooves formed by the laser beam on the insulating film in the mesa grooves are eliminated, and at the same time, the steel roller When the semiconductor substrate is broken and separated by pressing, etc., even if contact occurs between adjacent semiconductor pellets, contact between the insulating films does not occur, so new cracks, chips, etc. occur in the insulating film. This will no longer occur, and there will be no so-called appearance defects. As a result, it is easy to mass-produce mesa-type semiconductor devices with stable characteristics and high reliability, and the manufacturing cost is also significantly reduced.
第1図A乃至第1図Fは本発明の一実施例を工
程順に示した断面図であり、第2図は本発明の一
実施例により製造された半導体装置の断面図であ
る。
尚、図面に於いて、1はN型シリコン基板、3
はPN接合、5はメサ溝、6は硝子粒子層、7は
絶縁膜、9は金属電極層、10はフオトレジスト
膜、11は切削溝、12はエツチング溝である。
1A to 1F are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a semiconductor device manufactured according to an embodiment of the present invention. In the drawing, 1 is an N-type silicon substrate, 3
5 is a PN junction, 5 is a mesa groove, 6 is a glass particle layer, 7 is an insulating film, 9 is a metal electrode layer, 10 is a photoresist film, 11 is a cutting groove, and 12 is an etching groove.
Claims (1)
するメサ溝を形成し、該メサ溝に絶縁膜を被覆
し、該メサ溝に沿つてペレツトに切断分割する半
導体装置の製造方法に於いて、メサ溝に絶縁膜を
被覆した後メサ溝を除く半導体基板の表裏面に金
属電極層を形成する工程と、前記絶縁膜上および
前記金属電極層上にフオトレジスト膜を形成する
工程と、前記絶縁膜上のフオトレジスト膜の表面
からビームを照射して切削溝を形成する工程と、
前記フオトレジスト膜をマスクとして前記切削溝
部の絶縁膜をエツチングする工程とを含むことを
特徴とする半導体装置の製造方法。1 In a method for manufacturing a semiconductor device, a mesa groove in which a PN junction is exposed is formed in a semiconductor substrate having a PN junction, the mesa groove is coated with an insulating film, and the mesa groove is cut into pellets along the mesa groove. forming a metal electrode layer on the front and back surfaces of the semiconductor substrate except for the mesa groove after coating the groove with an insulating film; forming a photoresist film on the insulating film and the metal electrode layer; and forming a photoresist film on the insulating film and the metal electrode layer; a step of irradiating a beam from the surface of the upper photoresist film to form a cutting groove;
A method of manufacturing a semiconductor device, comprising the step of etching an insulating film in the cut groove portion using the photoresist film as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3886277A JPS53123657A (en) | 1977-04-04 | 1977-04-04 | Production of semiconductor unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3886277A JPS53123657A (en) | 1977-04-04 | 1977-04-04 | Production of semiconductor unit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS53123657A JPS53123657A (en) | 1978-10-28 |
JPS6156617B2 true JPS6156617B2 (en) | 1986-12-03 |
Family
ID=12537004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3886277A Granted JPS53123657A (en) | 1977-04-04 | 1977-04-04 | Production of semiconductor unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS53123657A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5762536A (en) * | 1980-10-01 | 1982-04-15 | Nec Corp | Manufacture of semiconductor device |
KR940016546A (en) * | 1992-12-23 | 1994-07-23 | 프레데릭 얀 스미트 | Semiconductor device and manufacturing method |
JP4590174B2 (en) * | 2003-09-11 | 2010-12-01 | 株式会社ディスコ | Wafer processing method |
JP2006203251A (en) * | 2004-10-07 | 2006-08-03 | Showa Denko Kk | Production method for semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4852374A (en) * | 1971-11-02 | 1973-07-23 | ||
JPS49122278A (en) * | 1973-03-22 | 1974-11-22 | ||
JPS5629383A (en) * | 1979-08-17 | 1981-03-24 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of tunnel-junction type josephson element |
-
1977
- 1977-04-04 JP JP3886277A patent/JPS53123657A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4852374A (en) * | 1971-11-02 | 1973-07-23 | ||
JPS49122278A (en) * | 1973-03-22 | 1974-11-22 | ||
JPS5629383A (en) * | 1979-08-17 | 1981-03-24 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of tunnel-junction type josephson element |
Also Published As
Publication number | Publication date |
---|---|
JPS53123657A (en) | 1978-10-28 |
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