JPS61253829A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61253829A JPS61253829A JP60094907A JP9490785A JPS61253829A JP S61253829 A JPS61253829 A JP S61253829A JP 60094907 A JP60094907 A JP 60094907A JP 9490785 A JP9490785 A JP 9490785A JP S61253829 A JPS61253829 A JP S61253829A
- Authority
- JP
- Japan
- Prior art keywords
- glass protective
- bumps
- semiconductor
- wafer
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、メサ溝部にガラス保護膜を有する半導体装置
の製造方法に関し、特にレーザー光線によるガラス保護
膜のスクライブ工程の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device having a glass protective film in a mesa groove, and particularly to an improvement in the scribing process of the glass protective film using a laser beam.
従来、この株の半導体装置は、第３図（ａ） 、 （ｂ
）に示すように、一枚の半導体ウェーハ１に拡散等でＰ
型ゲート領域２．Ｐ型アノード領域４．Ｎ型カンード領
域３を形成することによって多数の半導体素子を形成し
、各半導体素子間にメサ溝６を形成し、メサ溝６に露出
するＰＮ接合部５をガラス絶縁体９で被榎保護したのち
、このガラス絶縁体９の中央部からレーザー光線によっ
てスクライブし、さらに各素子片に分離し溶量に封入す
ることによって第４図に示すような半導体装置が製造さ
れていた。Conventionally, this type of semiconductor device has been manufactured as shown in Figs. 3(a) and (b).
), P is applied to one semiconductor wafer 1 by diffusion, etc.
Type gate region 2. P-type anode region4. A large number of semiconductor elements are formed by forming an N-type cando region 3, a mesa groove 6 is formed between each semiconductor element, and a PN junction 5 exposed in the mesa groove 6 is covered and protected with a glass insulator 9. Thereafter, a semiconductor device as shown in FIG. 4 was manufactured by scribing the glass insulator 9 from the center with a laser beam, separating it into each element piece, and enclosing it in a melt.
上述した従来の半導体装置は、ガラス保護膜９によりて
メサ溝６に露出するＰＮ接合５を十分に保護するために
はガラス保Ｓ膜９の厚さをある程度厚くする必要がある
。しかしながら、ガラス保護膜７が厚いとレーザー光線
によるスクライブが困難になるため、レーザーの出力を
上げてスクライブするか又はレーザースクライブの速度
を下けてスクライブする必要があった。しかしながらレ
ーザーの出力を上けてスクライブすると溝部に露出して
いるＰＮ接合の耐圧の劣化が観測される。In the conventional semiconductor device described above, in order to sufficiently protect the PN junction 5 exposed in the mesa groove 6 with the glass protective film 9, it is necessary to increase the thickness of the glass S retaining film 9 to some extent. However, if the glass protective film 7 is thick, scribing with a laser beam becomes difficult, so it is necessary to increase the output of the laser for scribing or to decrease the speed of laser scribing. However, when the laser output is increased and scribing is performed, a deterioration in the withstand voltage of the PN junction exposed in the groove is observed.
又、レーザースクライブの速度を下げてスクライブする
と接合の耐圧劣化は防止できるが、作業能率が極端に低
下するという欠点がある。Furthermore, if the laser scribing speed is lowered and the scribing is performed, deterioration of the breakdown voltage of the joint can be prevented, but there is a drawback that the working efficiency is extremely reduced.
本発明によれば、半導体ウェーハに多数の半導体素子を
形成後、半導体素子上および半導体素子間の一部にエツ
チングマスクを形成し、半導体ウェーハをエツチングし
て半導体素子間に底部に突起部を有する凹部を形成し、
との凹部にガラス保護膜を形成した後、凹部内の突起部
上をガラス保護膜上からレーザー光線によるスクライブ
を施して、しかる後各半導体素子片に分離する半導体装
置の製造方法を得る。According to the present invention, after forming a large number of semiconductor elements on a semiconductor wafer, an etching mask is formed on the semiconductor elements and a portion between the semiconductor elements, and the semiconductor wafer is etched to form protrusions on the bottom between the semiconductor elements. forming a recess;
A method for manufacturing a semiconductor device is obtained in which a glass protective film is formed in the recessed portion, and then a laser beam is used to scribe the protrusion in the recessed portion from above the glass protective film, and then the semiconductor device is separated into each semiconductor element piece.
〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第１図（ａ） 、 （ｂ） 、 （Ｃ）は本発明の一実
施例による製造方法の各工程の縦断面図である。Ｎ型の
半導体ウェーハ１にＰ型不純物を両面拡散してゲート領
域２とアノード領域４を作り、その後Ｎ型不純物を拡散
して互いに分離した多数のカソード領域３を作る。その
後ウェーハの両面で半導体素子部とこの半導体素子部間
の中央部にエツチングマスクとして絶縁膜７，７′を形
成し、ウェーハをエツチングしてメサ溝６を形成する。FIGS. 1(a), 1(b), and 1(C) are longitudinal cross-sectional views of each step of a manufacturing method according to an embodiment of the present invention. P-type impurities are diffused on both sides of an N-type semiconductor wafer 1 to form gate regions 2 and anode regions 4, and then N-type impurities are diffused to form a number of mutually separated cathode regions 3. Thereafter, insulating films 7 and 7' are formed as an etching mask on both sides of the wafer between the semiconductor element parts and the central part between the semiconductor element parts, and the wafer is etched to form a mesa groove 6.
この時半導体素子間の絶縁膜７′はエツチングの進行と
ともに除去されるが、その後に突起部８が残る。メサ溝
６の深さはＮ型半導体ウェーハ１とＰ型のゲート領域２
とアノード領域４とがそれぞれ形成するＰＮ接合が露出
するような深さとする。次いでメサ溝６内に例えば電気
泳動法によりガラス粉末を被着せしめ、その後ガラス粉
末を加熱溶融してガラス保護膜９を形成する。この時、
メサ溝６内には中央突起部８が形成されているので、こ
の中央突起部８以外の所はＰＮ接合５がメサ溝６に露出
する部分を含めて十分厚いガラス保護膜９ができるが、
中央突起部８上には極端に薄いガラス保護膜９が形成さ
れる。したがって、その後中央突起部８上からレーザー
光線を照射してスクライブし、第２図に示すような半導
体素子片に分離すると、ガラス保護膜の保護作用を十分
高く保ちながら、低い出力のレーザー光線によってスク
ライブすることができる。At this time, the insulating film 7' between the semiconductor elements is removed as the etching progresses, but the protrusions 8 remain. The depth of the mesa groove 6 is the same as that of the N-type semiconductor wafer 1 and the P-type gate region 2.
The depth is set such that the PN junction formed by the anode region 4 and the anode region 4 is exposed. Next, glass powder is deposited in the mesa groove 6 by, for example, electrophoresis, and then the glass powder is heated and melted to form a glass protective film 9. At this time,
Since a central protrusion 8 is formed within the mesa groove 6, a sufficiently thick glass protective film 9 is formed in areas other than the central protrusion 8, including the portion where the PN junction 5 is exposed to the mesa groove 6.
An extremely thin glass protective film 9 is formed on the central projection 8. Therefore, when the central protrusion 8 is then irradiated with a laser beam and scribed, and the semiconductor elements are separated into pieces as shown in FIG. be able to.
この時、レーザー光線の出力は小さいので、スクライブ
後ＰＮ接合の耐圧劣化という現象も生じないし、薄いガ
ラス保護膜を介してレーザースクライブをしているので
、スクライブを高速度で行うことができる。At this time, since the output of the laser beam is small, the phenomenon of breakdown voltage deterioration of the PN junction after scribing does not occur, and since laser scribing is performed through a thin glass protective film, scribing can be performed at high speed.
以上説明したように、本発明によれば、メサ溝に中央突
起部を設けているので、このメサ溝内に露出するＰＮ接
合部には厚いガラス保Ｍ膜が形成され、かつ凸部には薄
いガラス保護膜が形成される。このためガラス保護膜形
成後のレーザー光線によるスクライブが低出力で高速に
行なえる。したがって従来より問題となっていたレーザ
ースクライブによる耐圧劣化や作業能率の低下という問
題はなくなり、しかもメサ溝内に無比するＰＮ接合部は
厚いガラス保護膜によって被榎保護されているから、特
性変動のない良好で高歩留な半導体装置が得られるとい
う効果がある。As explained above, according to the present invention, since the central protrusion is provided in the mesa groove, a thick glass M retention film is formed on the PN junction exposed in the mesa groove, and the protrusion is A thin glass protective film is formed. Therefore, scribing with a laser beam after forming the glass protective film can be performed at low output and at high speed. Therefore, the conventional problems of breakdown voltage deterioration and reduction in work efficiency due to laser scribing are eliminated.Furthermore, since the unique PN junction inside the mesa groove is protected by a thick glass protective film, characteristic fluctuations are avoided. This has the effect that a semiconductor device with good quality and high yield can be obtained.
第１図（ａ） 、 （ｂ） ｔ （Ｃ）は本発明の一実
施例による製造方法を示す各工程での断面図、第２図は
その結果得られる半導体素子の断面図である。第３図は
従来の製造方法を示す各工程での断面図、第４図はその
結果得られる半導体素子の断面図である。
１・・・・・・Ｎ型半導体ウェーハ、２・・・・・・ゲ
ート領域、３・・・・・・カソード領域、４・・・・・
・アノード領域、５・・。
・・−ＰＮ接合、６・・・・・・メサ溝、７，７／・・
・・・・絶縁膜、８・・・・・・突起部、９・・；・・
・ガラス保護膜。
８ＩＱ！Ｊ
第 ３ 凶
８４図FIGS. 1(a) and 1(b)t(C) are cross-sectional views at each step showing a manufacturing method according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device obtained as a result. FIG. 3 is a cross-sectional view of each step of a conventional manufacturing method, and FIG. 4 is a cross-sectional view of a semiconductor element obtained as a result. 1... N-type semiconductor wafer, 2... gate region, 3... cathode region, 4...
-Anode area, 5... ...-PN junction, 6... Mesa groove, 7,7/...
... Insulating film, 8 ... Protrusion, 9 ...; ...
・Glass protective film. 8IQ! J No. 3 Kyou 84
Claims (1)
前記半導体ウェーハの各半導体素子上および半導体素子
間の一部上にエッチングマスクを形成する工程と、前記
半導体ウェーハを前記エッチングマスクを用いてエツチ
ングし前記半導体素子間に突起部を有するメサ溝を形成
する工程と、該メサ溝にガラス保護膜を形成する工程と
、前記突起部上の前記ガラス保護膜上からレーザー光線
によってスクライブし、その後各半導体素子片に分離す
る工程とを含むことを特徴とする半導体装置の製造方法
。a step of forming a large number of semiconductor elements on a semiconductor wafer;
forming an etching mask on each semiconductor element of the semiconductor wafer and a portion between the semiconductor elements; etching the semiconductor wafer using the etching mask to form a mesa groove having a protrusion between the semiconductor elements; forming a glass protective film in the mesa groove; and scribing the glass protective film on the protrusion with a laser beam, and then separating it into individual semiconductor element pieces. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60094907A JPS61253829A (en) | 1985-05-02 | 1985-05-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60094907A JPS61253829A (en) | 1985-05-02 | 1985-05-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61253829A true JPS61253829A (en) | 1986-11-11 |
Family
ID=14123083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60094907A Pending JPS61253829A (en) | 1985-05-02 | 1985-05-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61253829A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8435869B2 (en) | 2010-01-22 | 2013-05-07 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
| US8507302B1 (en) * | 2005-10-11 | 2013-08-13 | SemiLEDs Optoelectronics Co., Ltd. | Wall structures for a semiconductor wafer |
-
1985
- 1985-05-02 JP JP60094907A patent/JPS61253829A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8507302B1 (en) * | 2005-10-11 | 2013-08-13 | SemiLEDs Optoelectronics Co., Ltd. | Wall structures for a semiconductor wafer |
| US8435869B2 (en) | 2010-01-22 | 2013-05-07 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
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