JPS645456B2 - - Google Patents
Info
- Publication number
- JPS645456B2 JPS645456B2 JP18500382A JP18500382A JPS645456B2 JP S645456 B2 JPS645456 B2 JP S645456B2 JP 18500382 A JP18500382 A JP 18500382A JP 18500382 A JP18500382 A JP 18500382A JP S645456 B2 JPS645456 B2 JP S645456B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon dioxide
- film
- semiconductor device
- groove
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000002585 base Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
この発明はメサ形構造が半導体基板の一主表面
もしくは両主表面に形成された環状溝などにより
形成されている半導体装置の製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which a mesa-shaped structure is formed by an annular groove or the like formed on one or both main surfaces of a semiconductor substrate.
半導体基板の一主表面もしくは両主表面に環状
溝が形成され、この環状溝の内側壁面にpn接合
部が露呈するようにしたメサ形構造は大面積の半
導体基板内に多数個の半導体ペレツトを形成する
場合に適する。また、この環状溝内にガラスなど
の無機物の安定化膜の形成が容易であり、信頼性
の高い高耐圧のものにも適用可能である。したが
つて、上述のメサ構造はサイリスタやトランジス
タなどの電力用半導体装置に広く適用されてい
る。一方、半導体装置の電流容量が増大するにつ
れて、半導体ペレツトを大形化することが必要で
あり、チツプサイズが増大する。このチツプサイ
ズの大形化により、１チツプの中の酸化膜のピン
ホールの発生率が高くなり、エツチングによるシ
リコン穴が増え、耐圧低下、洩れ電流の増大、ピ
ンホールの原因による信頼性上の問題が生ずる。
そこで、従来酸化膜をマスクとして環状溝を選択
的にエツチングする写真製版工程（レジスト塗布
→露光）を２回実施し、極力写真製版工程でのピ
ンホールを少なくすることが実施されている。 A mesa-shaped structure in which an annular groove is formed on one or both main surfaces of a semiconductor substrate and a pn junction is exposed on the inner wall surface of the annular groove allows a large number of semiconductor pellets to be deposited within a large area of the semiconductor substrate. Suitable for forming. Further, it is easy to form a stabilizing film of an inorganic material such as glass in this annular groove, and it is also applicable to a highly reliable and high-voltage structure. Therefore, the mesa structure described above is widely applied to power semiconductor devices such as thyristors and transistors. On the other hand, as the current capacity of a semiconductor device increases, it is necessary to increase the size of the semiconductor pellet, and the chip size increases. This increase in chip size increases the incidence of pinholes in the oxide film within one chip, increases the number of silicon holes caused by etching, lowers the withstand voltage, increases leakage current, and causes reliability problems due to pinholes. occurs.
Therefore, conventionally, the photolithography process (resist coating→exposure) for selectively etching the annular groove using an oxide film as a mask is carried out twice to reduce the number of pinholes in the photolithography process as much as possible.
しかしながら、従来の半導体装置の製造方法は
写真製版工程で発生する酸化膜のピンホール以外
に、熱酸化膜を形成する酸化膜生成工程において
も、酸化膜のピンホールが発生するうえ、チツプ
の中にピンホールの起因によるエツチング穴が生
ずるなどの欠点があつた。 However, in conventional semiconductor device manufacturing methods, pinholes in the oxide film are generated in the oxide film generation process in which a thermal oxide film is formed, in addition to pinholes in the oxide film that occur during the photolithography process. However, there were drawbacks such as etching holes caused by pinholes.
したがつて、この発明の目的は耐圧劣化や洩れ
電流のない信頼性の高い、しかも生産性のよい新
規なメサ形接合を有する半導体装置の製造方法を
提供するものである。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having a novel mesa-type junction, which is highly reliable without deterioration of breakdown voltage or leakage current, and has good productivity.
このような目的を達成するため、この発明は半
導体基板の一主表面あるいは両主表面からpn接
合部より深い環状溝あるいは格子溝を形成する際
に、二酸化シリコン膜の上にAl蒸着膜などの金
属膜を形成する工程と、前記二酸化シリコン膜お
よび金属膜をマスクとして半導体基板をエツチン
グして、前記溝を形成する工程とを備えるもので
あり、以下実施例を用いて詳細に説明する。 In order to achieve such an object, the present invention deposits an Al deposited film or the like on a silicon dioxide film when forming an annular groove or a lattice groove deeper than a pn junction from one or both main surfaces of a semiconductor substrate. The method includes a step of forming a metal film and a step of etching the semiconductor substrate using the silicon dioxide film and the metal film as a mask to form the groove, and will be described in detail below using examples.
第１図ａ〜第１図ｆはこの発明に係る半導体装
置の製造方法の一実施例の製造工程順に示す断面
図であり、第２図はこの半導体装置の製造方法に
より製造した高耐圧メサ形サイリスタを示す断面
図である。これらの図において、１はＮ形のシリ
コン基板、２はこのシリコン基板１の両主表面に
熱酸化法により形成した二酸化シリコン、３はＰ
形ベース層、４はＰ形エミツタ層、５は熱酸化法
により形成した二酸化シリコン、６はリンを拡散
して形成したｎ形エミツタ層、７はAl蒸着膜、
８はエツチング工程で発生したピンホール、９は
溝、１０はこの溝９に形成したガラス、１１は電
極である。 1a to 1f are cross-sectional views showing the manufacturing process order of an embodiment of the semiconductor device manufacturing method according to the present invention, and FIG. 2 is a high-voltage mesa shape manufactured by this semiconductor device manufacturing method. FIG. 3 is a cross-sectional view showing a thyristor. In these figures, 1 is an N-type silicon substrate, 2 is silicon dioxide formed on both main surfaces of this silicon substrate 1 by a thermal oxidation method, and 3 is a P silicon substrate.
4 is a P-type emitter layer, 5 is silicon dioxide formed by thermal oxidation, 6 is an N-type emitter layer formed by diffusing phosphorus, 7 is an Al vapor deposited film,
8 is a pinhole generated in the etching process, 9 is a groove, 10 is glass formed in this groove 9, and 11 is an electrode.
次に、上記半導体装置の製造方法について第１
図ａ〜第１図ｆに示す製造工程順に説明する。ま
ず、第１図ａに示すように、Ｎ形のシリコン基板
１の両主表面に熱酸化法により二酸化シリコン２
を形成したのち、ガリウムを両主表面から拡散
し、Ｐ形ベース層３およびＰ形エミツタ層４を形
成する。次に、第１図ｂに示すように、両主表面
に二酸化シリコン２を除去し、熱酸化法により二
酸化シリコン５を形成したのち、この二酸化シリ
コン５の前記Ｐ形ベース層３の一主表面に形成さ
れた一部分を写真製版により除去する。次いで、
リンを拡散してｎ形エミツタ層６を形成する。次
に、第１図ｃに示すように、前記二酸化シリコン
５を写真製版によりエツチングする。次に、第１
図ｄに示すように、シリコン基板１の両主表面に
例えば3μｍ以上のAl蒸着膜７を形成したのち、
写真製版でエツチングするが、このエツチング工
程で発生したピンホールを８で示す。次に、第１
図ｅに示すように、このAl蒸着膜７と２酸化シ
リコン５をマスクとして溝９を形成する。次に、
第１図ｆに示すように、この溝９にガラス１０を
形成したのち、電極形成部の酸化膜を除去し、第
２図に示すように電極１１を形成する。そして、
最後に環状溝と環状溝の間の中央部から切断し、
第２図に示すようにペレツトを得る。 Next, we will discuss the first method for manufacturing the semiconductor device.
The manufacturing steps will be explained in the order shown in Figures a to 1f. First, as shown in FIG. 1a, silicon dioxide 2 is applied to both main surfaces of an N-type silicon substrate 1 by thermal oxidation.
After forming gallium, gallium is diffused from both main surfaces to form a P-type base layer 3 and a P-type emitter layer 4. Next, as shown in FIG. 1b, silicon dioxide 2 is removed from both main surfaces and silicon dioxide 5 is formed by thermal oxidation, and then one main surface of the P-type base layer 3 of silicon dioxide 5 is formed. A portion formed on the surface is removed by photolithography. Then,
An n-type emitter layer 6 is formed by diffusing phosphorus. Next, as shown in FIG. 1c, the silicon dioxide 5 is etched by photolithography. Next, the first
As shown in Figure d, after forming an Al deposited film 7 of, for example, 3 μm or more on both main surfaces of the silicon substrate 1,
Etching is performed using photolithography, and the pinholes generated during this etching process are shown at 8. Next, the first
As shown in Figure e, a groove 9 is formed using the Al deposited film 7 and silicon dioxide 5 as a mask. next,
After forming glass 10 in this groove 9, as shown in FIG. 1f, the oxide film on the electrode forming portion is removed, and electrodes 11 are formed as shown in FIG. 2. and,
Finally, cut from the center between the annular grooves,
A pellet is obtained as shown in FIG.
上述の製造工程において、二酸化シリコン５の
部分にピンホールがあつたとしても、Al蒸着膜
７によつてカバーされ、ピンホールの位置が二酸
化シリコン５とAl蒸着膜７の同じ位置には同一
マスクを使用しない限り、ピンホールの発生する
確率は飛躍的に減少し、エツチングによるシリコ
ン穴はほとんどなくなる。また、耐圧劣化、洩れ
電流の増大およびピンホールに起因する品質の低
下は皆無に近くなる。 In the above manufacturing process, even if there is a pinhole in the silicon dioxide 5, it is covered by the Al vapor deposited film 7, and if the pinhole is located at the same position in the silicon dioxide 5 and the Al vapor deposited film 7, the same mask is used. Unless etching is used, the probability of pinholes occurring is dramatically reduced, and silicon holes due to etching are almost eliminated. Further, deterioration in breakdown voltage, increase in leakage current, and deterioration in quality due to pinholes are almost completely eliminated.
第３図は第１図ａ〜第１図ｆに示す半導体装置
の製造方法によつて製造したゲート・ターン・オ
フ・サイリスタを示す断面図であり、第２図と異
なるのは溝７が一主表面にあり、拡散構造がアノ
ード・シヨーテイド（anode shorted）されたも
のである。 FIG. 3 is a sectional view showing a gate turn-off thyristor manufactured by the semiconductor device manufacturing method shown in FIGS. 1a to 1f. Located on the main surface, the diffusion structure is anode shorted.
なお、上述の実施例では金属マスク材料として
Al蒸着膜を使用する場合について説明したが、
耐酸、耐アルカリの高い金属であれば任意の金属
を用いることができることはもちろんである。ま
た、環状溝の形成について説明したが、格子溝の
形成についても同様に形成することができること
はもちろんである。また、高耐圧メサ形サイリス
タを製造する場合について説明したが、トランジ
スタなどの他の半導体装置についても同様にでき
ることはもちろんである。 In addition, in the above-mentioned examples, as the metal mask material,
Although we explained the case of using Al vapor deposited film,
Of course, any metal can be used as long as it has high acid resistance and alkali resistance. Moreover, although the formation of annular grooves has been described, it goes without saying that lattice grooves can also be formed in the same manner. Further, although the case of manufacturing a high voltage mesa thyristor has been described, it goes without saying that the same can be applied to other semiconductor devices such as transistors.
以上詳細に説明したように、この発明に係る半
導体装置の製造方法によれば溝形成時のマスクと
して、Al蒸着膜のような金属膜を二酸化シリコ
ン膜の上に設けたので、装置が安価にできるう
え、歩留りおよび品質の高いものが得られるなど
の効果がある。 As explained in detail above, according to the method for manufacturing a semiconductor device according to the present invention, a metal film such as an Al vapor-deposited film is provided on a silicon dioxide film as a mask during trench formation, so that the device can be manufactured at low cost. Not only that, but it also has the effect of producing products with high yield and quality.
第１図ａ〜第１図ｆはこの発明に係る半導体装
置の製造方法の一実施例を製造工程順に示す断面
図、第２図および第３図はそれぞれ第１図ａ〜第
１図ｆに示す半導体装置の製造方法によつて製造
した高耐圧メサ形サイリスタおよびゲート・ター
ン・オフ・サイリスタを示す断面図である。
１……Ｎ形のシリコン基板、２……二酸化シリ
コン、３……Ｐ形ベース層、４……Ｐ形エミツタ
層、５……二酸化シリコン、６……ｎ形エミツタ
層、７……Al蒸着膜、８……ピンホール、９…
…溝、１０……ガラス、１１……電極。なお、図
中、同一符号は同一または相当部分を示す。
1a to 1f are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of manufacturing steps, and FIGS. 2 and 3 are sectional views shown in FIGS. 1a to 1f, respectively. FIG. 2 is a cross-sectional view showing a high voltage mesa thyristor and a gate turn-off thyristor manufactured by the semiconductor device manufacturing method shown in FIG. DESCRIPTION OF SYMBOLS 1...N-type silicon substrate, 2...Silicon dioxide, 3...P-type base layer, 4...P-type emitter layer, 5...Silicon dioxide, 6...n-type emitter layer, 7...Al vapor deposition Membrane, 8...Pinhole, 9...
...Groove, 10...Glass, 11...Electrode. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
成する溝の内側壁面にpn接合を有するメサ形構
造の半導体装置において、この一主表面もしくは
両主表面からpn接合部より深い環状溝あるいは
格子溝を形成する際に、二酸化シリコン膜の上
に、Al蒸着膜などの金属膜を形成する工程と、
前記二酸化シリコン膜および金属膜をマスクとし
て半導体基板をエツチングして前記溝を形成する
工程とを備えたことを特徴とする半導体装置の製
造方法。1. In a semiconductor device with a mesa-shaped structure having a pn junction on the inner wall surface of a groove formed on one or both main surfaces of a semiconductor substrate, an annular groove or a lattice groove deeper than the pn junction from one or both main surfaces a step of forming a metal film such as an Al vapor deposited film on the silicon dioxide film;
A method of manufacturing a semiconductor device, comprising the step of etching the semiconductor substrate using the silicon dioxide film and the metal film as a mask to form the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18500382A JPS5972769A (en) | 1982-10-19 | 1982-10-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18500382A JPS5972769A (en) | 1982-10-19 | 1982-10-19 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5972769A JPS5972769A (en) | 1984-04-24 |
| JPS645456B2 true JPS645456B2 (en) | 1989-01-30 |
Family
ID=16163072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18500382A Granted JPS5972769A (en) | 1982-10-19 | 1982-10-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5972769A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274362A (en) * | 1985-05-29 | 1986-12-04 | Fuji Electric Co Ltd | Manufacture of gate turn-off thyristor |
-
1982
- 1982-10-19 JP JP18500382A patent/JPS5972769A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5972769A (en) | 1984-04-24 |
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