JPS5972769A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5972769A JPS5972769A JP18500382A JP18500382A JPS5972769A JP S5972769 A JPS5972769 A JP S5972769A JP 18500382 A JP18500382 A JP 18500382A JP 18500382 A JP18500382 A JP 18500382A JP S5972769 A JPS5972769 A JP S5972769A
- Authority
- JP
- Japan
- Prior art keywords
- silicon dioxide
- films
- grooves
- main surfaces
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 23
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 5
- 239000008188 pellet Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 201000001880 Sexual dysfunction Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 150000001342 alkaline earth metals Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Weting (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はメサ形構造が半導体基板の一生表面もしくは
両生表面に形成された環状溝などによ多形成されている
半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which mesa-shaped structures are formed in a plurality of annular grooves or the like formed on a continuous surface or an amphibatic surface of a semiconductor substrate.
半導体基板の一生表面もしくは両生表面に環状溝が形成
され、この環状溝の内側壁面にｐｎ接合部が露呈するよ
うにしたメサ形構造は大面積の半導体基板内に多数個の
半導体ペレットを形成する場合に適する。また、この環
状溝内にガラスなどの無機物の安定化膜の形成が容易で
あシ、信頼性の高い高耐圧のものにも適用可能である。A mesa-shaped structure in which an annular groove is formed on the permanent or amphibatic surface of the semiconductor substrate and a pn junction is exposed on the inner wall surface of the annular groove forms a large number of semiconductor pellets within a large area of the semiconductor substrate. suitable for the case. Further, it is easy to form a stabilizing film of an inorganic material such as glass in this annular groove, and it is also applicable to a highly reliable and high-voltage structure.
したがって、上述のメサ構造はサイリスタやトランジス
タなどの電力用半導体装置に広く適用されている。Therefore, the mesa structure described above is widely applied to power semiconductor devices such as thyristors and transistors.
一方、半導体装置の電流容量が増大するにつれて、半導
体ペレットを大形化することが必要であシ、チップサイ
ズが増大する。このチップサイズの大形化によシ、１チ
ツプの中の酸化膜のピンホールの発生率が高くなシ、エ
ツチングによるシリコン穴が増え、耐圧低下、洩れ電流
の増大、ピンホールの原因による信頼性上の問題が生ず
る。そこで、従来酸化膜をマスクとして環状溝を選択的
にエツチングする写真製版工程（レジスト塗布→露光）
を２回実施し、極力写真製版工程でのピンホールを少な
くすることが実施されている。On the other hand, as the current capacity of a semiconductor device increases, it is necessary to increase the size of the semiconductor pellet, and the chip size increases. As the chip size increases, the incidence of pinholes in the oxide film within one chip increases, and silicon holes due to etching increase, resulting in lower breakdown voltage, increased leakage current, and reliability due to pinholes. Sexual problems arise. Therefore, in the conventional photolithography process (resist coating → exposure), the annular groove is selectively etched using an oxide film as a mask.
This process is carried out twice to reduce the number of pinholes in the photoengraving process as much as possible.
しかしながら、従来の半導体装置の製造方法は写真製版
工程で発生する酸化膜のピンホール以外に、熱酸化膜を
形成する酸化膜生成工程においても、酸化膜のピンホー
ルが発生するうえ、チップの中にピンホールの起因によ
るエツチング穴が生ずるなどの欠点があった。However, in conventional semiconductor device manufacturing methods, pinholes in the oxide film are generated not only in the photolithography process but also in the oxide film generation process in which a thermal oxide film is formed. However, there were drawbacks such as etching holes caused by pinholes.
したがって、この発明の目的は耐圧劣化や洩れ電流のな
い信頼性の高い、しかも生産性のよい新規なメサ形接合
を有する半導体装置の製造方法を提供するものである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having a novel mesa-type junction, which is highly reliable and free from breakdown voltage deterioration and leakage current, and which has good productivity.
このような目的を達成するため、この発明は半導体基板
の一主表面あるいは両生表面からｐｎ接合部より深い環
状溝あるいは格子溝を形成する際に、二酸化シリコン膜
の上にＡＪ蒸着膜などの金属膜を形成する工程と、前記
二酸化シリコン膜および金属膜をマスクとして半導体基
板をエツチングして、前記溝を形成する工程とを備える
ものであシ、以下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention provides a method for forming an annular groove or a lattice groove deeper than a pn junction from one main surface or both surfaces of a semiconductor substrate by depositing a metal film such as an AJ vapor deposited film on a silicon dioxide film. The method includes a step of forming a film, and a step of etching the semiconductor substrate using the silicon dioxide film and metal film as a mask to form the groove, and will be described in detail below using examples.
第１図（息）〜第１図（ｆ）はこの発明に係る半導体装
置の製造方法のｉ実施例の製造工程順に示す断面図であ
シ、第２図はこの半導体装置の製造方法によシ製造した
高耐圧メサ形ザイリスタを示す断面図である。とれらの
図において、（１）はＮ形のシリコン基板、（２）はこ
のシリコン基板（１）の両生表面に熱酸化法により形成
した二酸化シリコン、（３）はＰ形成−ス層、（４）は
Ｐ形エミッタ層、（５）は熱酸化法によ多形成した二酸
化シリコン、（６）はリンを拡散して形成したｎ形エミ
ッタ層、Ｃ′Ｉ）はＡｌ蒸着膜、（８）はエツチング工
程で発生したピンホール、（９）は溝、（１０）はこの
溝（９）に形成したガラス、（１１）は電極である。FIGS. 1(b) to 1(f) are cross-sectional views showing the manufacturing process of the i embodiment of the semiconductor device manufacturing method according to the present invention, and FIG. FIG. 2 is a cross-sectional view showing a manufactured high-voltage mesa-type Zyristor. In these figures, (1) is an N-type silicon substrate, (2) is silicon dioxide formed by thermal oxidation on the amphibatic surface of this silicon substrate (1), (3) is a P-formation layer, ( 4) is a P-type emitter layer, (5) is silicon dioxide formed by a thermal oxidation method, (6) is an n-type emitter layer formed by diffusing phosphorus, C'I) is an Al vapor deposited film, (8) ) is a pinhole generated in the etching process, (9) is a groove, (10) is glass formed in this groove (9), and (11) is an electrode.
次に、上記半導体装置の製造方法について第１図（、）
〜第１図（ｆ）に示す製造工程順に説明する。まず、第
１図（、）に示すように、Ｎ形のシリコン基板（１）の
両生表面に熱酸化法によシ二酸化シリコンＱ）を形成し
たのち、ガリウノ、を両生表面から拡散し、Ｐ形成−ス
層（３）およびＰ形エミッタ層（４）を形成する。次に
、第１図（ｂ）に示すように、両生表面に二酸化シリコ
ン＜２）を除去し、熱酸化法によシ二酸化シリコン（５
）を形成したのち、この二酸化シリコン（５）の前記Ｐ
形成−ス層（３）の−主表面に形成された一部分を写真
製版によシ除去する。次いで、リンを拡散してｎ形エミ
ッタ層（６）を形成する。次に、第１図（ｃ）に示すよ
うに、前記二酸化シリコン（５）を写真製版によシエッ
チングする。次に、第１図（ｄ）に示すように、シリコ
ン基板（１）の両生表面に例えば３μｍ以上のＡｌ蒸着
膜（７）を形成したのち、写真製版でエツチングするが
、このエツチング工程で発生したピンホールを（８）で
示す。次に、第１図（−）に示すように、とのＡＪ蒸着
膜ｆｆ）と２酸化シリコン（５）をマスクとして溝（９
）を形成する。次に、第１図（ｆ）に示すように、この
溝（９）にガラス（１０）を形成したのち、電極形成部
の酸化膜を除去し、第２図に示すように電極（１１）を
形成する。そして、最後に環状溝と環状溝の間の中央部
から切断し、第２図に示すようにペレットを得る。Next, the manufacturing method of the above semiconductor device is shown in FIG.
- The manufacturing steps shown in FIG. 1(f) will be explained in order. First, as shown in Figure 1(, ), silicon dioxide Q) is formed on the amphiboid surface of an N-type silicon substrate (1) by a thermal oxidation method, and then galiuno is diffused from the amphipathic surface. Formation - A source layer (3) and a P-type emitter layer (4) are formed. Next, as shown in Figure 1(b), silicon dioxide <2) is removed from the amphiboid surface, and silicon dioxide (5) is removed by thermal oxidation.
) of this silicon dioxide (5).
A portion formed on the main surface of the forming layer (3) is removed by photolithography. Next, phosphorus is diffused to form an n-type emitter layer (6). Next, as shown in FIG. 1(c), the silicon dioxide (5) is etched by photolithography. Next, as shown in FIG. 1(d), an Al deposited film (7) of, for example, 3 μm or more is formed on the amphibatic surface of the silicon substrate (1), and then etched by photolithography. The resulting pinhole is shown in (8). Next, as shown in FIG.
) to form. Next, as shown in FIG. 1(f), after forming a glass (10) in this groove (9), the oxide film on the electrode forming part is removed, and the electrode (11) is formed as shown in FIG. form. Finally, the pellet is cut from the center between the annular grooves to obtain a pellet as shown in FIG.
上述の製造工程において、二酸化シリコン（５）の部分
にピンホールがあったとしても、Ａｌ蒸着膜（７）によ
ってカバーされ、ピンホールの位置が二酸化シリコン（
５）とＡｌ蒸着膜（７）の同じ位置には同一マスクを使
用しない限シ、ピンホールの発生する確率は飛躍的に減
少し、エツチングによるシリコン穴はほとんどなくなる
。また、耐圧劣化、洩れ電流の増大およびピンホールに
起因する品質の低下は皆無に近くなる。In the above manufacturing process, even if there is a pinhole in the silicon dioxide (5), it is covered by the Al vapor deposition film (7) and the position of the pinhole is located in the silicon dioxide (5).
As long as the same mask is not used at the same position of 5) and the Al deposited film (7), the probability of pinholes occurring will be dramatically reduced, and silicon holes due to etching will almost disappear. Further, deterioration in breakdown voltage, increase in leakage current, and deterioration in quality due to pinholes are almost completely eliminated.
第３図は第１図（、）〜第１図（ｆ）に示す半導体装置
の製造方法によって製造したゲート・ターン・オフ・サ
イリスタを示す断面図であり、第２図と異なるのは溝（
７）が−主表面にあ）、拡散構造がアノード・ショーテ
ィド（ａｎｏｄｅ ５ｈｏｒｔａｄ ）されたものであ
る。FIG. 3 is a cross-sectional view showing a gate turn-off thyristor manufactured by the semiconductor device manufacturing method shown in FIGS. 1(a) to 1(f).
7) is on the main surface, and the diffusion structure is anode shorted.
なお、上述の実施例では金属マスク材料としてＡ７蒸着
膜を使用する場合について説明したが、耐酸、耐アルカ
リ土類金属であれば任意の金属を用いることができるこ
とは本ちろんである。また、環状溝の形成について説明
したが、格子溝の形成についても同様に形成することが
できることはもちろんである。また、高耐圧メサ形サイ
リスタを製造する場合について説明したが、トランジス
タなどの他の半導体装置についても同様にできることは
もちろんである。In the above-mentioned embodiment, the case where the A7 vapor deposited film is used as the metal mask material has been described, but it goes without saying that any metal can be used as long as it is acid-resistant and alkaline-earth metal resistant. Moreover, although the formation of annular grooves has been described, it goes without saying that lattice grooves can also be formed in the same manner. Further, although the case of manufacturing a high voltage mesa thyristor has been described, it goes without saying that the same can be applied to other semiconductor devices such as transistors.
以上詳細に説明したように、この発明に係る半導体装置
の製造方法によれば溝形成時のマスクとして、ＡＩ！蒸
着膜のような金属膜を二酸化シリコン膜の上に設けたの
で、装置が安価にできるうえ、歩留シおよび品質の高い
ものが得られるなどの効果がある。As described above in detail, according to the method of manufacturing a semiconductor device according to the present invention, AI! Since a metal film, such as a vapor-deposited film, is provided on the silicon dioxide film, the device can be made at low cost, and it is also effective in producing products with high yield and quality.
第１図（、）〜第１図（ｆ）はとの発明に係る半導体装
置の製造方法の一実施例を製造工程順に示す断面図、第
２図および第３図はそれぞれ第１図（、）〜第１図（ｆ
）に示す半導体装置の製造方法によって製造した高耐圧
メサ形サイリスタおよびゲート・ターン・オフ・サイリ
スタを示す断面図である。
（１）・・・・Ｎ形のシリコン基板、（２）・・・・−
酸化シリコン、（３）・・・・Ｐ形ベース層、（４）・
・・・Ｐ形エミッタ層、（５）・・・・二酸化シリコン
、（６）・・・・ｎ形エミッタ層、（７）・拳・・ＡＪ
蒸着膜、（８）・・・・ピンホール、（９）・・・・溝
、（１０）・・・拳ガラス、（１１）・・−・電極。
なお、図中、同一符号は同一または相当部分を示す。
代理人 葛 野 信 −1(a) to 1(f) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the invention in the order of manufacturing steps, and FIGS. 2 and 3 are sectional views shown in FIG. ) ~ Figure 1 (f
) is a cross-sectional view showing a high-voltage mesa-type thyristor and a gate turn-off thyristor manufactured by the semiconductor device manufacturing method shown in FIG. (1)...N-type silicon substrate, (2)...-
Silicon oxide, (3)...P-type base layer, (4)...
... P-type emitter layer, (5) ... silicon dioxide, (6) ... n-type emitter layer, (7) - fist ... AJ
Vapor deposited film, (8)... pinhole, (9)... groove, (10)... fist glass, (11)... electrode. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Shin Kuzuno −
Claims (1)
内側壁面にｐｎ接合を有するメサ形構造の半導体装置に
おいて、この−主表面もしくは両生表面からｐｎ接合部
よシ深い環状溝あるいは格子溝を形成する際に、二酸化
シリコン膜の上に、ｋｌ蒸着膜などの金属膜を形成する
工程と、前記二酸化シリコン膜および金属膜をマスクと
して半導体基板をエツチングして前記溝を形成する工程
とを備えたことを特徴とする半導体装置の製造方法。In a semiconductor device having a mesa-shaped structure having a pn junction on the inner wall surface of a groove formed on the main surface or the amphitheater surface of a semiconductor substrate, an annular groove or a lattice groove is formed deeper than the pn junction from the main surface or the amphitheater surface. In particular, the method includes a step of forming a metal film such as a KL vapor deposited film on the silicon dioxide film, and a step of etching the semiconductor substrate using the silicon dioxide film and the metal film as a mask to form the groove. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18500382A JPS5972769A (en) | 1982-10-19 | 1982-10-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18500382A JPS5972769A (en) | 1982-10-19 | 1982-10-19 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5972769A true JPS5972769A (en) | 1984-04-24 |
| JPS645456B2 JPS645456B2 (en) | 1989-01-30 |
Family
ID=16163072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18500382A Granted JPS5972769A (en) | 1982-10-19 | 1982-10-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5972769A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274362A (en) * | 1985-05-29 | 1986-12-04 | Fuji Electric Co Ltd | Manufacture of gate turn-off thyristor |
-
1982
- 1982-10-19 JP JP18500382A patent/JPS5972769A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274362A (en) * | 1985-05-29 | 1986-12-04 | Fuji Electric Co Ltd | Manufacture of gate turn-off thyristor |
| JPH0554704B2 (en) * | 1985-05-29 | 1993-08-13 | Fuji Electric Co Ltd |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS645456B2 (en) | 1989-01-30 |
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