JP3226528B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, constitutes an anode short type gate turn-off thyristor (hereinafter, simply referred to as GTO). The present invention relates to a semiconductor device and a method for manufacturing the same.

(Prior Art) Conventionally, in the manufacture of a semiconductor device having a GTO structure, a brazing technique is used to connect electrodes to a GTO main body. An example will be described below with reference to FIG. In this example, a P-type P ₁ layer 1, N
First, silicon having a stacked structure of the N-type N ₁ layer 2, the P-type P ₂ layer 3, and the N-type N ₂ layer 4 is formed. Next,
The P ₁ layer is brazed to the anode electrode plate 5 made of Mo or W by the Al layer 6 as a brazing material. Thereafter, a gate electrode 7 and a cathode electrode 8 are formed on the P ₂ layer and the N ₂ layer, respectively. Further, the periphery is beveled and the silicon resin 9 is coated. In such GTO of structure, P ₁ layers 20μm to 30μm in Al layer 6 is low material
As it melts in and partially melts as much as 60 μm,
Which may come into contact with the N ₁ layer 2 is for example the portion shown in A. Hereinafter, a conventional technique used to prevent this will be described with reference to FIGS. 12 and 13. FIG.

FIG. 12 shows an anode short type GTO in which the anode side is patterned, and shows a state before being brazed. In this configuration, first, the N ₁ ⁺ layer is partially diffused, and then the P ₁ layer is formed by diffusion. At this time, the N ₁ ⁺ layer and the P ₁ layer are formed deep to prevent the above-mentioned contact. However, at the same time, the N ₁ ⁺ layer diffuses in the lateral direction, so that the portion of X _N1 ⁺ expands, and therefore the X _P1 portion of the P ₁ layer decreases. For this reason, not only does the effective area through which the current flows decreases, but also fine control during patterning becomes difficult. Therefore, the GTO characteristics vary. Next, the GTO having the configuration shown in FIG. 13 will be described. In this configuration, first, the P ₁ layer is deeply diffused and then the N ₁
^{+ The} layer is diffused. In this case, there is an advantage that X _N1 ⁺ can be formed narrow, but as described above, the P ₁ layer cannot be controlled due to the lateral diffusion. Furthermore, the indicated resistance R near the N ₁ ⁺ layer increases, and the electrical characteristics deteriorate.

(Problems to be Solved by the Invention) As described above, the conventional semiconductor device, that is, the GTO
In the above, there is a problem that the brazing material comes into contact with another layer due to dissolution. Further, even if it is attempted to overcome this problem, fine control at the time of patterning becomes difficult, causing problems such as variations in GTO characteristics and deterioration of electrical characteristics.

The present invention has been made in view of the above circumstances, and has been developed by GTO.
By not brazing the body and the electrode,
The P1 equivalent layer can be formed shallowly, and fine control can be performed when patterning the P1 equivalent layer and the N1 ⁺ equivalent layer. Therefore, a semiconductor device having improved characteristics and a method of manufacturing the same are provided. The purpose is to do.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a semiconductor device of the present invention comprises:
A first conductive type substrate, a second conductive type first layer formed on one surface of the first conductive type substrate, and a first conductive type first layer formed on the second conductive type first layer. 2 layer, a first conductive type third layer selectively formed on the other surface of the first conductive type substrate, and a second conductive type third layer formed on the other surface of the first conductive type substrate. A fourth layer, and an electrode formed by a deposition method without using a brazing material for the third layer and the fourth layer, wherein the thickness of the first layer is about 60 μm. The thickness of the fourth layer is 5 μm to 20 μm.

Also, a method of manufacturing a semiconductor device according to the present invention provides a substrate of a first conductivity type, forming a first layer of a second conductivity type having a thickness of about 60 μm on one surface of the substrate, Forming a second layer of the first conductivity type on one surface of the layer; selectively forming a third layer of the first conductivity type on the other surface of the substrate;
5 so as to be thinner than the thicknesses of the first and third layers.
forming a fourth layer of a second conductivity type having a thickness of 20 μm to 20 μm, a higher concentration than the substrate and a lower impurity concentration than the third layer, and forming the one surface of the first layer; Forming a gate electrode on a selected portion of the second layer, forming a first main electrode on one surface of the second layer, and forming a second electrode on the third and fourth layers by a deposition method without using a brazing material. Is formed.

Also, a method of manufacturing a semiconductor device according to the present invention provides a substrate of a first conductivity type, forms a first layer of a second conductivity type with a thickness of about 60 μm on one surface of the substrate, A second layer of the second conductivity type is formed thinner than the thickness of the first layer, a third layer of the first conductivity type is formed on the first layer, and a second layer is formed on the second layer. Selectively forming a fourth layer of the first conductivity type having a higher concentration than the impurity concentration with a thickness of 5 μm to 20 μm, and forming a gate electrode on a part of the one surface of the first layer; A first main electrode is formed on one surface of the third layer, and a second main electrode is formed on the second and fourth layers by a deposition method without using a brazing material.

(Operation) In the present invention, the electrode formed by the deposition method is connected to the third layer and the fourth layer without using a brazing material, and the thickness of the fourth layer is Since the first layer is formed to be thinner than the thickness of the first layer and between 5 μm and 20 μm, fine control at the time of patterning becomes possible, and variations in characteristics are eliminated.

(Embodiment) Hereinafter, with reference to the drawings, a first embodiment of a semiconductor device according to the present invention
An example will be described.

FIG. 1 is a cross-sectional configuration diagram of a GTO main body of a semiconductor device of the present invention. Reference numeral 21 denotes an N-type silicon substrate (N ₁ ) layer,
On the surface of the reference number 22 is N ₁ layer, formed by the diffusion P
The mold base layer (P ₂ ) layer, reference number 23 is an N ⁺ type emitter layer (N ₂ ⁺ layer) diffused and formed on the surface side of the P ₂ layer, and reference number 24
Is, N ⁺ -type base layer on the back surface side is selectively formed by diffusion of N ₁ layer (N ₁ ⁺ layer), reference numeral 25, P-type emitter layer which is formed by diffusion on the back side of the N ₁ layer (P ₁ layer). In addition,
N ₁ ⁺ The layer and P ₁ layer surface, the anode electrode film, a cathode electrode film on the N ₂ ⁺ layer surface, further, P ₂ exposed from the cutout portion 26
A gate electrode film is formed on each layer surface. Each of the above electrode films is formed by a deposition method such as evaporation or sputtering.

2 (a) to 2 (e) are views showing an example of a method of manufacturing the GTO main body of FIG. First, FIG. 2 (a)
, An N-type silicon substrate 21 is prepared. This board
Specific resistance ρ of 21, the wafer thickness W _T is determined by the specifications of the device. For example, in the case of 2500V specification, ρ = 100Ωcm,
W _T = 500 μm. The substrate 21 to be formed by diffusion of P ₂ layer 22 from one side (FIG. 2 (b)). Ga or B is used as the dopant at that time. Further, the surface concentration of the P ₂ layer 22 is about 1 × 10 ¹⁸ cm ⁻³ , and the diffusion depth is about 60 μm. Instead of the structure of FIG. 2 (a), after forming a P ₂ layer on both sides of the substrate as shown in FIG. 3 (a), as shown in FIG. _Two layers may be removed. Next, as shown in FIG. 3 (c), an N ₁ ⁺ layer 24 is selectively formed on the anode side surface, and N ₂ ⁺ layer is formed on the cathode side surface.
_The ²⁺ layer 23 is formed by diffusion over the entire surface. Thereafter, the P ₁ layer 25, N ₁ ⁺
The diffusion is formed so as to have a lower concentration than the layer and a higher concentration than the substrate 21 (FIG. 2 (d)). Thus, the P ₁ layer and the N ₁ ⁺ layer are selectively formed on the anode side. Then the second
As shown in FIG. 5E, the surfaces of the N ₂ layer and the P ₂ layer are partially removed, and the surface of the P ₂ layer is partially exposed. Incidentally, as shown in FIG. 4 (a), if the N ₂ layer is selectively diffused and formed,
It is also possible to obtain the configuration as shown in FIG. 4 (b) by omitting the step of removing the N ₂ and P ₂ surfaces in FIG. 2 (e).

The thickness of the P ₁ layer 5 to 20μm is preferable. When the thickness is 5 μm or less, the injection efficiency from the P ₁ layer to the N ₁ layer is reduced, so that α _PNP is reduced and the ON characteristics are impaired. On the other hand, when the thickness is 20 μm or more, a seepage in the horizontal direction occurs, so that fine control becomes difficult as described above.

Thereafter, through an electrode forming step, a passivation step, and the like, a completed structure close to the actual example is obtained as shown in FIG. That is, after forming the GTO main body shown in FIG. 2 (e), an SiO ₂ film 31 is formed over the P ₂ layer and the N ₂ layer to passivate the P ₂ and N ₂ junctions. Then, P ₁ , N ₁ ⁺
The anode electrode 32 on the layer, the cathode electrode 33 on the N ₂ layer,
The gate electrode 34 to the P ₂ layer on, for example, formed respectively in Al deposition. Furthermore, a polyimide film 35 is coated on the gate electrode 34 except for a part, and the periphery is beveled.
The silicone resin 36 is coated.

Further, the structure of the GTO will be further described with reference to a schematic cross-sectional view of the semiconductor device according to the present invention in FIG.

In the figure, a semiconductor pellet 121 includes a P emitter layer 25, an N base layer 21, a P base layer 22, and an N emitter from a second main surface (lower in the drawing) to a first main surface (upper in the drawing). The layer 23 has a four-layer structure. The P emitter layer 25 is partially formed, and the N base layer 24 is partially exposed on the second main surface (on the anode side). N emitter layer
23 is divided into many. First of semiconductor pellet 121
Main electrode (cathode electrode) on N emitter layer 23 on main surface
23, and a control electrode (gate electrode) on the P base layer 22
34 are respectively formed. The main electrode 33 is surrounded by a control electrode 34, and both electrodes are formed on one main surface so as to be intricate with each other. On the other main surface (second main surface) of the semiconductor pellet 121, a main electrode (anode electrode) 32 is formed, and a P emitter layer 25 and a partially exposed N base layer 24 are formed.
Are short-circuited to form a so-called anode short-circuit structure.
The cathode electrode 33 on the first main surface of the semiconductor pellet 121 is pressed by the cathode electrode post 23k via the cathode-side electrode member 24k composed of the electrode plate 24m and the soft metal thin plate 24n,
The anode electrode 32 on the second main surface is an anode-side electrode member.
Pressurized by the anode electrode post 23a via 24a. The semiconductor pellet 121 is subjected to beveling on its side wall to maintain the breakdown voltage between the anode and the cathode, and after etching the crushed surface, a silicon resin 36 is applied for passivation (insulation protection). The gate lead 9 is disposed in a hollow portion and a notch of the electrode post 23k and the electrode member 24k via a positioning guide 31k made of an insulating material and an insulating member (not shown). One end of the gate lead 9 is provided by a gate pressure contact spring. The other end is inserted through a metal sleeve 12 brazed to the side wall of the insulating cylinder 6, is led out to the outside, and is sealed by a seal portion 13.

The electrode posts 23k and 23a and the insulating cylinder (ceramic) 6 are silver-braded and arc-welded to each other via ring-shaped metal plates (kovar) 6k, 6a, 7k and 7a called weld rings. An envelope to be hermetically sealed is formed. Further, the anode-side electrode member 24a and the anode electrode post 23a are aligned via a positioning guide 31a. The positioning guide 31a is an annular cylindrical body made of a metal such as Al or an insulating material such as Teflon or epoxy, and has a step 133 provided on its inner peripheral surface. The step 133 prevents vertical vibration of the guide 31a itself.

As described above, in the method of forming a semiconductor device of the present invention, P ₁ layer, it is possible to shallow the N ₁ ⁺ layer, lateral diffusion is small, therefore, made larger lateral dimensions of the P ₁ layer.
From this, P ₁ layer, allows fine control of the N ₁ ⁺ layer pattern, variation in characteristics is eliminated. Also N ₁
⁺ An increase in resistance on the layer can be prevented.

Further, as shown in FIG. 6, in the semiconductor device of the present invention, the trade-off between the switching loss at the time of turn-on and turn-off and the steady-state on-loss is improved by about 25% as compared with the conventional configuration ( Here, a GTO with a gate turn-off current I _TGQM = 700 A is used). Further, the manufacturing method itself is almost the same as the conventional method, and the semiconductor device of the present invention can be manufactured relatively easily and inexpensively.

Next, a second embodiment of the semiconductor device according to the present invention will be described. In this embodiment, first, as shown in FIG. 7 (a), relatively, to prepare a first conductivity type substrate N ₁ of high resistivity. Then to form the first layer P ₂ of the second conductivity type on the surface side (FIG. 7 (b)). Thereafter, the forming the second layer P ₁ of the second conductivity type on the back side of the substrate N ₁ thinner than the first layer (FIG. 7 (c)). Furthermore, as shown in FIG. 7 (d), a third layer N ₂ of a first conductivity type in the first layer P _2, and the second layer P _1, a high than impurity concentration A fourth layer N ₁ ⁺ of the first conductivity type having a high concentration is selectively formed. afterwards,
As shown in FIG. 7E, the N ₂ layer and the P ₂ layer are partially removed, and the surface of the P ₂ layer is partially exposed. Further, the first
Of the gate electrode on the surface side exposed surface of the layer P _2, the first main electrode to the third layer N ₂ surface, the layer P ₁ of the second and 4, N ₁ ⁺ the second
Are formed by a deposition method.

Note that, instead of the configuration of FIG. 7 (b), FIG. 8 (a)
After forming the P ₂ layer on both sides of the substrate as shown in FIG. 8, the P ₂ layer on one side may be removed as shown in FIG. 8 (b). Further, if the N ₂ layer is selectively diffused as shown in FIG. 9, the step of removing the N ₂ and P ₂ surfaces in FIG. 7E can be omitted.

The second embodiment has the following advantages in addition to the advantages of the first embodiment. That is, the depth of the second layer is
(FIG. 7 (c)), it is possible to control freely so that emphasis between characteristics can be taken. Further, since the fourth layer has a higher concentration than the second layer and the diffusion coefficient of the impurity of the fourth layer is larger than that of the impurity of the second layer, the fourth layer
Can be formed deeper than the second layer.

[Effects of the Invention] As described above, according to the present invention, fine control at the time of patterning becomes possible, so that it is possible to provide a semiconductor device having improved characteristics and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a main part configuration diagram showing a first embodiment of a semiconductor device according to the present invention, and FIGS. 2 (a) to 2 (e) show the first embodiment.
FIGS. 3 (a) and 3 (b) are views showing a modification of the configuration of FIG. 1, and FIGS.
4 (a) and 4 (b) are diagrams showing still another modification of the configuration of FIG. 1, FIG. 5 is a diagram showing an example of a completed GTO, and FIG. 6 is a switching loss. 7 (a) to 7 (e) are manufacturing process diagrams showing a second embodiment of the semiconductor device according to the present invention, and FIGS. 8 (a) and 8 (a) to 8 (e). 7 (b) is a diagram showing a modification of the configuration of FIG. 7, FIG. 9 is a diagram showing another modification of the configuration of FIG. 7, and FIG. 10 is a semiconductor device shown in FIG. FIG. 11 to FIG. 13 are diagrams for explaining problems of the conventional semiconductor device. 21 ...... N-type silicon substrate (N ₁₎ layer, 22 ...... P-type base layer (P ₂₎ layer, 23 ...... N ⁺ -type emitter layer (N ₂ ⁺ layer), 24 ...... N ⁺
Base layer (N ₁ ⁺ layer), 25 P-type emitter layer (P
₁ layer), 26 ...... notch, 31 ...... SiO ₂ film, 32 ...... anode electrode, 33 ...... cathode electrode, 34 ...... gate electrode, 35 ......
Polyimide film, 36 ... silicon resin.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takeomi Yoshida 1 Kogamu Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (56) References JP-A-63-87767 (JP, A) JP-A-63-87767 JP-A-63-37660 (JP, A) JP-A-62-290174 (JP, A) JP-A-51-52282 (JP, A) JP-A-59-171161 (JP, A) JP-A-62-32646 (JP, A) , A)

Claims (9)

(57) [Claims] A first conductive type substrate; and a second conductive type first substrate formed on one surface of the first conductive type substrate.
A second conductive type second layer formed on the second conductive type first layer.
A first conductive type third layer selectively formed on the other surface of the first conductive type substrate; and a second conductive type third layer formed on the other surface of the first conductive type substrate. And a third layer and an electrode formed by a deposition method without using a brazing material for the third layer and the fourth layer, wherein the first layer has a thickness of about 60 μm. Wherein the thickness of the fourth layer is 5 μm to 20 μm. 2. The method according to claim 1, wherein the surface concentration of the first layer is about 1 × 10 ¹⁸ cm.
^3. The semiconductor device according to claim 1, wherein the value is ^-3 . 3. The semiconductor device according to claim 1, wherein the concentration of the fourth layer is higher than that of the substrate and lower than that of the third layer. 4. A substrate of a first conductivity type, wherein a first layer of a second conductivity type having a thickness of about 60 μm is formed on one surface of the substrate, and a first conductive layer is formed on one surface of the first layer. Forming a second layer of a mold, selectively forming a third layer of a first conductivity type on the other surface of the substrate, and forming a second layer of the first conductivity type on the other surface of the substrate according to the thickness of the first and third layers. Forming a fourth layer of the second conductivity type having a thickness of 5 μm to 20 μm, a higher concentration than the substrate, and a lower impurity concentration than the third layer so as to be thinner. Forming a gate electrode on a selected portion of the one surface of the first layer, forming a first main current on one surface of the second layer, and using no brazing material for the third and fourth layers; Forming a second main electrode by a deposition method. 5. The method according to claim 1, further comprising a step of partially removing said second layer by a post-process and partially exposing said first layer. 4) The production method according to the above. 6. The manufacturing method further comprises forming a second conductivity type layer on the one surface and the other surface of the substrate when forming the first layer, and forming the second conductivity type layer on the other surface after the formation. The method according to claim 4, further comprising the step of removing the second conductivity type layer. 7. The method according to claim 4, wherein said second layer is selectively formed on said one surface of said first layer by diffusion. 8. The method according to claim 1, wherein the gate electrode and the first main electrode are:
The production method according to claim 4, wherein the production method is formed by a deposition method. 9. A substrate of a first conductivity type, wherein a first layer of a second conductivity type having a thickness of about 60 μm is formed on one surface of the substrate, and a second layer of a second conductivity type is formed on the other surface of the substrate. A second layer is formed thinner than the thickness of the first layer; a third layer of the first conductivity type is formed on the first layer; and an impurity concentration of the second layer is higher than an impurity concentration of the third layer. A fourth layer of a first conductivity type having a concentration of 5 μm to 20 μm is selectively formed; a gate electrode is formed on a part of the one surface of the first layer; and one surface of the third layer is formed. A method of manufacturing a semiconductor device, comprising: forming a first main electrode on a substrate; and forming a second main electrode on the second and fourth layers by a deposition method without using a brazing material.