JPS6223177A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6223177A JPS6223177A JP16458185A JP16458185A JPS6223177A JP S6223177 A JPS6223177 A JP S6223177A JP 16458185 A JP16458185 A JP 16458185A JP 16458185 A JP16458185 A JP 16458185A JP S6223177 A JPS6223177 A JP S6223177A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- insulating film
- epitaxial layer
- regions
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 238000001816 cooling Methods 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 206010011878 Deafness Diseases 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、１ノードあるいはカソードを共通とする複
数のダイオードが半導体基板上に形成された半導体装置
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device in which a plurality of diodes having one node or common cathode are formed on a semiconductor substrate.
第２図は７ノードあるいはカソードを共通とする複数の
ダイオードが半導体基板上に形成された従来の半導体装
置の一例を示す構成断面図で、１はＳｔ かうなる抵
抗率０．００１〜０．００３Ωｃｍのｎ”Ｗの半導体基
板、２はｎ−型のシリコンエピタキシャル層、３はＳｉ
Ｏ２からなる絶縁膜、４は高濃度領域であるｎ十型領域
、５はｐ属領域、６は金属電極である。この場合、ｐ型
頭域５が７７−ド、ｎ−Ｗシリコンエピタキシャル層２
が共通のカソードとなる。FIG. 2 is a cross-sectional view showing an example of a conventional semiconductor device in which seven nodes or a plurality of diodes having a common cathode are formed on a semiconductor substrate, and 1 is St. The resistivity is 0.001 to 0.003 Ωcm. 2 is an n-type silicon epitaxial layer, 3 is a Si
An insulating film made of O2, 4 is a high concentration n-type region, 5 is a p-type region, and 6 is a metal electrode. In this case, the p-type head region 5 is 77-doped and the n-W silicon epitaxial layer 2 is
becomes a common cathode.
このような半導体装置では、ラデラルＰＮＰもしくはＮ
ＰＮ）ランジスタのエミノターコンクク間のに流に相当
するｔ流が、各ダイオード間のリーク′ａＬ流となって
流れる。従来はこのリークを流を巷減らすために、各ダ
イオード間ＫｎｆＪｌまたはｐ凰の高濃度の不純物領域
（第２図ではれ十型領域４）を設けてバルクの少数キャ
リアのライフタイムを減らしたり、各ダイオードの間隔
を広げたりするほか、製造段階でキャリアのライフタイ
ムキラーとなる金を拡散させていた。In such a semiconductor device, lateral PNP or N
PN) The t current corresponding to the current between the eminoter contacts of the transistor flows as a leakage 'aL current between each diode. Conventionally, in order to reduce this leakage current, a high-concentration impurity region of KnfJl or p-oxide was provided between each diode (the cross-shaped region 4 in FIG. 2) to reduce the lifetime of bulk minority carriers. In addition to widening the spacing between each diode, they also diffused gold, which is a carrier lifetime killer, during the manufacturing process.
上記のような従来の半導体装置では、各ダイオード間に
高濃度の不純物領域を設けるだけではリーク電流を充分
忙減らすことができず、これを補うため忙各ダイオード
間の間隔を広げれば、チップの面積が大きくなってしま
う。また金拡散による方法では、金のドープ量が多けれ
ばリーク電流が増え少なければ効果を失うので、ドープ
量の調整が峻しく、やはり充分にリークを流を減らすこ
とができないという問題点があった。In conventional semiconductor devices such as those described above, it is not possible to sufficiently reduce leakage current by simply providing a high concentration impurity region between each diode, and to compensate for this, widening the spacing between each diode will improve the chip performance. The area becomes large. In addition, in the method using gold diffusion, if the amount of gold doped is large, the leakage current increases, and if the amount of gold is small, the effect is lost, so the doping amount must be adjusted tightly, and there is still a problem that the leakage current cannot be sufficiently reduced. .
この発明は、かかる問題点を解決するためＫなされたも
ので、半導体基板上に形成された各ダイオード間のリー
クを光の少ない半導体装置の製造方法を得ることを目的
とする。The present invention has been made to solve these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that reduces light leakage between diodes formed on a semiconductor substrate.
この発明に係る半導体装置の製造方法は、半導体基板の
エピタキシャル層表面に絶縁膜を形成した後忙不純物ド
ープ層形成のため妃行う熱拡散処理のｖＡに、半導体基
板の昇温速度および冷却速度の少なくとも一方を１６０
℃／分以上としたものである。The method for manufacturing a semiconductor device according to the present invention includes adjusting the heating rate and cooling rate of the semiconductor substrate to the vA of the thermal diffusion treatment performed for forming the impurity doped layer after forming the insulating film on the surface of the epitaxial layer of the semiconductor substrate. at least one 160
℃/min or more.
この発明においては、半導体基板の急激な温度変化によ
り工学導体基板のエピタキシャル層と絶縁膜間に再結合
中心が増え、ライフタイムキラー領域が形成される。In this invention, the rapid temperature change of the semiconductor substrate increases the number of recombination centers between the epitaxial layer and the insulating film of the engineering conductor substrate, forming a lifetime killer region.
第１図（ａ）〜（ｅ）はこの発明の半導体装置の製造方
法の一実施例の工程を示す図で、第２図と同一符号は同
一部分を示し、Ｔは再結合中心によるライフタイムキラ
ー領域である。1(a) to 1(e) are diagrams showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention, in which the same reference numerals as in FIG. 2 indicate the same parts, and T is the lifetime due to recombination centers. This is killer territory.
以下、工程について説明する。The steps will be explained below.
まず、第１図（ａ）に示すよ５＆ｔ、半導体基板１上に
シリコンエピタキシャル層２を形成する。次に第１図（
ｂ） Ｋ示すよ５に、通常の酸化法で絶縁膜３を形成し
たのち、各ダイオードを形成する部分のまわりにｎ十匿
領域４を写真製版方法を用〜・て形成する。次いで第１
図（ｃ）に示すように、ダイオードを形成するためのｐ
型領域５を、写真製版方法を用いて形成した領域中ＫＢ
＋イオンな注入すること忙よって形成する。次にこの半
導体基板ＩＹ１１００℃の窒素雰囲気中に１５分間置く
。First, as shown in FIG. 1(a), a silicon epitaxial layer 2 is formed on a semiconductor substrate 1. Next, Figure 1 (
b) After forming an insulating film 3 using a normal oxidation method, an n-density region 4 is formed around a portion where each diode is to be formed using a photolithography method. Then the first
As shown in figure (c), p
The mold region 5 is formed using a photolithography method.
It is formed by implanting + ions. Next, this semiconductor substrate IY is placed in a nitrogen atmosphere at 1100° C. for 15 minutes.
このとき、半導体基板１を室温から高温の窒素雰囲気中
に入れる速度および取出し速度は１１００℃／分とし、
半導体基板１の昇温速度および冷却速度が１６０℃／分
以上となるよう忙することにより、シリコンエピタキシ
ャル層２と絶縁膜３との間にライフタイムキラーとなる
再結合中心が増え、第１図（ｄ）に示すようｋ、ライフ
タイムキラー領域１が形成される。最後に、第１図（ｅ
）Ｉ／ｃ示すよ５１’（、不要な絶縁膜３を除去して電
極６を形成することＫより半導体装置が得られる。この
結果、各ダイオード間のリーク電流は１００ｎＡ以下と
なった。At this time, the speed at which the semiconductor substrate 1 is put into and taken out from the room temperature to the high temperature nitrogen atmosphere is 1100° C./min.
By increasing the heating rate and cooling rate of the semiconductor substrate 1 to 160° C./min or higher, the number of recombination centers between the silicon epitaxial layer 2 and the insulating film 3, which can be a lifetime killer, increases, resulting in As shown in (d), a lifetime killer region 1 is formed. Finally, in Figure 1 (e
) As shown in I/c, a semiconductor device is obtained by removing the unnecessary insulating film 3 and forming the electrode 6. As a result, the leakage current between each diode became 100 nA or less.
なお、上記実施例忙おける半導体基板１の昇温速度およ
び冷却速度を１１０℃／分以下としたときの各ダイオー
ド間のリークを流は、３０μＡ以上であった。In addition, when the heating rate and cooling rate of the semiconductor substrate 1 in the above embodiment were set to 110° C./min or less, the leakage current between each diode was 30 μA or more.
またこの発明の半導体装置の製造方法に金拡散を併用す
ることも可能であり、その場合には各ダイオード間のリ
ーク電流を完全に抑えることができる。Further, it is also possible to use gold diffusion in combination with the method of manufacturing a semiconductor device of the present invention, and in that case, leakage current between each diode can be completely suppressed.
さらに、上記実施例ではｎ聾の半導体基板上にダイオー
ドを形成する場合につい工説明したが、ｐ型の半導体基
板上べ形成する場合につ〜・ても同様である。またこの
発明は８５０℃以上の高温処理を含む場合に有効である
。Further, in the above embodiments, the case where the diode is formed on an n-deaf semiconductor substrate has been described, but the same applies to the case where the diode is formed on a p-type semiconductor substrate. Further, the present invention is effective when high temperature treatment of 850° C. or higher is involved.
この発明は以上説明したとおり、半導体基板のエピタキ
シャル層表面に絶縁膜を形成した後に不純物ドープ層形
成のため忙行う熱拡散処理の際に、半導体基板の昇温速
度および冷却速度の少なくとも一方を１６０℃／分以上
としたので、半導体基板のエピタキシャル層と絶縁膜間
に再結合中心が増えてライフタイムキラー領域が形成さ
れ、各ダイオード間のリークｘｉの少ない半導体装置を
得ることができるという効果がある。As explained above, the present invention reduces at least one of the heating rate and cooling rate of the semiconductor substrate to 160% during the thermal diffusion treatment performed for forming the impurity doped layer after forming the insulating film on the surface of the epitaxial layer of the semiconductor substrate. ℃/min or more, the number of recombination centers increases between the epitaxial layer of the semiconductor substrate and the insulating film, forming a lifetime killer region, which has the effect of making it possible to obtain a semiconductor device with less leakage xi between each diode. be.
第１図（ａ）〜（ｅ）はこの発明の一実施例を示す半導
体装置の製造方法の工程を示す図、第２図は７ノードあ
るいはカソードを共通とする複数のダイオードが半導体
基板上に形成された従来の半導体装置の一例を示す構成
断面図である。
図におい℃、１は半導体基板、２はシリコンエピタキシ
ャル層、３は絶縁膜、４はｎ◆型領領域５はｐ属領域、
７はライフタイムキラー領域である。
なお、各図中の同一符号は同一または相当部分を示す＠
代理人 大 岩 増 雄 （外２名）第コ図FIGS. 1(a) to (e) are diagrams showing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows a plurality of diodes having seven nodes or a common cathode formed on a semiconductor substrate. 1 is a configuration cross-sectional view showing an example of a conventional semiconductor device formed; FIG. In the figure, 1 is a semiconductor substrate, 2 is a silicon epitaxial layer, 3 is an insulating film, 4 is an n◆ type region 5 is a p type region,
7 is the lifetime killer area. The same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
ドが半導体基板上に８５０℃以上の高温処理により形成
された半導体装置の製造方法において、前記半導体基板
のエピタキシャル層表面に絶縁膜を形成した後に不純物
ドープ層形成のために行う熱拡散処理の際に、前記半導
体基板の昇温速度および冷却速度の少なくとも一方を１
６０℃／分以上としたことを特徴とする半導体装置の製
造方法。In a method for manufacturing a semiconductor device in which a plurality of diodes having a common anode or cathode are formed on a semiconductor substrate by high-temperature treatment at 850° C. or higher, an impurity doped layer is formed after forming an insulating film on the surface of an epitaxial layer of the semiconductor substrate. At the time of the thermal diffusion treatment performed for the purpose of
A method for manufacturing a semiconductor device, characterized in that the temperature is 60° C./min or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16458185A JPS6223177A (en) | 1985-07-23 | 1985-07-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16458185A JPS6223177A (en) | 1985-07-23 | 1985-07-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6223177A true JPS6223177A (en) | 1987-01-31 |
Family
ID=15795888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16458185A Pending JPS6223177A (en) | 1985-07-23 | 1985-07-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6223177A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05508904A (en) * | 1990-08-23 | 1993-12-09 | アライド シグナル インコーポレイテッド | Mechanically actuated brakes with automatic adjustment |
| JP2008034606A (en) * | 2006-07-28 | 2008-02-14 | Nec Electronics Corp | Semiconductor device, and its fabrication process |
-
1985
- 1985-07-23 JP JP16458185A patent/JPS6223177A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05508904A (en) * | 1990-08-23 | 1993-12-09 | アライド シグナル インコーポレイテッド | Mechanically actuated brakes with automatic adjustment |
| JP2008034606A (en) * | 2006-07-28 | 2008-02-14 | Nec Electronics Corp | Semiconductor device, and its fabrication process |
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