JPS6110275A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain different current amplification factors with the same element shape by setting the concentration of an impurity layer suitably by a method wherein the impurity layer of lower concentration than that of an epitaxial layer and the same polarity is formed between the emitter layer and the collector layer. CONSTITUTION:The epitaxial layer 12 is provided with the P<+> type emitter layer 14, P<+> type collector layer 15, N<+> type base contact layer 16, and N<--> type impurity layer 17 formed between the emitter layer 14 and the collector layer 15. This impurity layer 17 has a lower concentration than that of the epitaxial layer 12 and the same polarity. Then, different current amplification factors can be obtained with the same element shape by suitably setting the concentration of the impurity layer 17.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a semiconductor device including a lateral PNP transistor.

(b) Prior Art In general, it is common practice to form lateral PNP transistors, NPN transistors, etc. on the same chip due to requirements for circuit characteristics in integrated circuits.

At this time, in order to improve the gain of the NPN type transistor, it is necessary to lower the specific resistance of the epitaxial layer to lower the saturation resistance. It is necessary to increase the resistivity of the layer. However, recently, in order to reduce power consumption, the driving voltage of integrated circuit devices themselves has been lowered, and there is a tendency to improve the gain f44 of NPN transistors by lowering the resistivity of the epitaxial layer. . In this case, as the specific resistance of the epitaxial layer is lowered, the current amplification degree hfe of the lateral PNP transistor becomes lower. Therefore, in order to form a lateral PNP transistor with a high current amplification degree hfe, a problem arises in that the element shape must be large +J.

Therefore, in forming a lateral I) NP type transistor with a high current amplification degree hfe, a semiconductor device is desired that can obtain different current amplification degrees hfe with the same element shape.

(c) Purpose This invention aims to provide a semiconductor device that can obtain different current amplification degrees hfe with the same element shape.

(D) Structure The semiconductor device according to the present invention is a semiconductor device including a lateral PNP transistor, and has an impurity layer formed between an emitter layer and a collector layer at a concentration lower than that of the epitaxial layer, but with the same polarity. It is characterized by the fact that it was formed.

(e) Embodiment FIG. 1 is an explanatory cross-sectional view showing an embodiment of a semiconductor device according to the present invention.

In Figure 1, ■ is a lateral PNP transistor;
Reference numeral 10 denotes a semiconductor substrate made of P-type silicon, which includes an N medium-sized buried diffusion layer 11, an epitaxial layer 12 forming a base in particular, and an isolation diffusion layer 1'i for separating each element.
13 are formed.

The epitaxial layer 12 includes a P medium emitter layer 1.
4, a P medium-sized collector layer 15, an N medium-sized base contact layer 16, the emitter layer 14 and the collector layer 1.
5 and an N-1 type impurity layer 17 formed between the N-type impurity layer 17 and This impurity layer 17 is formed on the epitaxial I
The concentration is lower than that of 'g12, and it has the same polarity.

Reference numeral 20 denotes a silicon oxide film serving as an insulator, and the film thickness thereof is relatively thick.

30a is an emitter electrode connected to the emitter Jif14. 30b is a collector area connected to the collector column 5. 30c is a base electrode connected to the contact layer 16 of the base.

Next, a method for manufacturing the above-mentioned semiconductor device will be explained with reference to FIG. Note that a case will be described in which a lateral PNP transistor and an NPN transistor are formed at the same time.

FIG. 2 is an explanatory cross-sectional view showing an embodiment of the method for manufacturing the semiconductor device shown in FIG. 1. However, the same parts as in FIG. 1 are indicated by the same reference numerals. '(δ) A buried diffusion layer 11 is formed on the surface of the semiconductor substrate 10, and an epitaxial layer 12 is grown. The isolation diffusion layer 13 separates each element. A relatively thick solicon oxide film 20 is formed on the surface of this substrate 10. Next, the emitter region and collector region of the lateral PNP transistor 1 and the N
The surface of the substrate other than the portion forming the base region of the PN type transistor 40 is covered with a photoresist 50.

(b) Using the photoresist 50 as a mask, the silicon oxide fli 20 is selectively etched. Then, using the silicon oxide film 20 on the substrate surface from which the photoresist 50 has been removed as a mask, P medium-sized impurities (for example, boron) are added.
ion implantation.

(C1) The ion-implanted substrate is heat-treated and diffused to form the emitter Fii 14 and collector column 5 of the lateral PNP transistor 1, as well as the base layer 41 of the NPN transistor 40.

(d) A new photoresist 51 is applied to the surface of the substrate except for the area between the emitter layer 14 and the collector layer 15 of the lateral PNP transistor 1 and where the emitter layer 14 and the collector layer 15 overlap. cover. Using this photoresist 51 as a mask, the silicon oxide film 20 is selectively etched.

(e) The selectively etched silicon oxide film 2
Using 0 as a mask, for example, a low concentration P-type impurity (eg, boron) is ion-implanted. Thereafter, an impurity layer 17 is formed by each heat treatment (indicated by a chain line).

(fl Cover the substrate surface with a photoresist 52 except for the portion where the base contact region of the lateral PNP transistor 1 and the emitter region and collector contact region of the NPN transistor 40 are to be formed.

(g) Using this photoresist 52 as a mask, the silicon oxide film 20 is selectively etched. Thereafter, using this silicon oxide M*20 as a mask, N medium size impurity (eg, arsenic) is ion-implanted.

(h) By heat-treating and diffusing the ion-implanted substrate, the contact layer 16 of the base of the lateral PNP transistor 1 and the NPN transistor 4 are formed.
0 emitter layer 42 and collector contact layer 43
form.

(1) Each electrode is formed in the same manner as in the conventional semiconductor device manufacturing method.

In addition, the steps (al to (e)) of the above-mentioned manufacturing method are as follows:
The following method may be used, and will be explained with reference to FIG.

FIG. 3 is an explanatory cross-sectional view showing another embodiment of the method for manufacturing the semiconductor device shown in FIG. Note that the same parts as in FIG. 2 are indicated by the same reference numerals.

(Al Thermal oxide film 2 as an insulating film on the surface of the substrate 10
1 (film thickness is, for example, about 1000 layers).

Next, the surface of the substrate other than the portion where the emitter region and collector region of the lateral PNP transistor 1 and the base region of the NPN transistor 40 are to be formed is covered with a photoresist 53. Using this photoresist 53 as a mask, P
Ion implant a medium-sized impurity (eg, boron).

Then, the photoresist 53 is removed.

(bl Cover the surface of the substrate other than the region where the impurity 117 is to be formed with a new photoresist 54. Using this photoresist 54 as a mask, ions of a P-type impurity (for example, boron) are implanted. Then, the photoresist 54 is removed.

(C) By heat-treating and diffusing the substrate into which ions have been implanted twice, the emitter layer 14, collector layer 15, and impurity layer 17 of the lateral PNP transistor 1 are formed, as well as the impurity layer 17 of the NPN transistor 40. A base 141 is formed. At this time, the thermal oxide film 2
1 is grown thickly (silicon oxide film 20 shown in FIG.
(same as the film thickness).

It should be noted that, according to the above-described other embodiment, the number of steps can be reduced compared to the manufacturing method shown in FIG. 2.

(f) Effects In this invention, an impurity layer is formed between the emitter layer and the collector layer, with a concentration lower than that of the epitaxial IiJ, but with the same polarity. Therefore, according to the present invention, by appropriately setting the concentration of the impurity layer,
Different current amplification degrees hre can be obtained with the same element shape. That is, even if the specific resistance of the epitaxial layer is lowered, the current amplification degree hfe can be increased without making the element shape thicker.

[Brief explanation of drawings]

1 is an explanatory cross-sectional view showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is an explanatory cross-sectional view showing an example of the method for manufacturing the semiconductor device shown in FIG. 1, and FIG. FIG. 2 is a cross-sectional explanatory diagram showing another example of the method for manufacturing the semiconductor device shown in FIG. 1; 10... Semiconductor substrate, 12... Epitaxial layer,
14... Emitter layer, 15... Collector layer, 17
...Impurity layer. Patent Applicant: ROHM Co., Ltd. Agent, Patent Attorney: Takaharu Ohnishi Figure 1

Claims (1)

[Claims] (1) A semiconductor device including a lateral PNP transistor, characterized in that an impurity layer is formed between an emitter layer and a collector layer at a concentration lower than that of the epitaxial layer and of the same polarity.