JPS60154656A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the integration and to enhance the performance of a semiconductor device by forming only the base portion directly under the emitter region of the second transistor so that the impurity density is lower than the base portion around the periphery and the depth of the junction is shallower. CONSTITUTION:An oxide film 2 which is obtained by oxidizing the surface of an n type Si substrate 1 is patterned to form a mask 7 by B ion implanting. B ions are implanted, elongated and diffused to form a p type base layer 9. A window is opened at a portion to become a collector (emitter), and P ions are implanted deeply in the layer 9. Thereafter, phosphorus is elongated and diffused to obtain a p type layer (graft base) 10 which is compensated by P and has low p type density. Then, it is oxidized, As ions are shallowly implanted to the surface of the layer 10 from the window. Thereafter, it is annealed, oxidized to obtain an n<+> type collector (emitter) 8. Since the collector (emitter) and the graft base are formed through one mask in the self-aligning manner as described above, the intergration can be improved without providing an excess base size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor devices, and particularly to analog/digital mixed semiconductor integrated circuit technology.

[Background technology]

A TC (or r-ST > When forming, I
f1. , if the invert tie row is inverse n
In order to improve the performance of the IC (or LSI), it is necessary to individually increase the amplification factor of the p r ] I transistor and the amplification factor of the bipolar n p n l transistor in the linear section. However, since conditions such as impurity diffusion concentration and base width for increasing the amplification factor of each element are contradictory, there is a problem in performing base diffusion and emitter diffusion for these pixel elements in the same process.

In other words, in order to increase the amplification factor (βi) of the inverse transistor at TTL, it is necessary to reduce the impurity concentration of the base directly below the collector and reduce the base width. bipolar in the linear section.
Forming a transistor amplifies it! (hFE) becomes smaller, and the withstand voltage decreases.

The present inventor has proposed a TC with such analog/digital mixing.
In order to improve the performance of a part of the ITT without impairing the characteristics of the linear section, we have developed the following technology.

That is, as shown in FIG. 1, high-concentration boron ions are scooped and diffused onto the surface of a semiconductor substrate (n-type epitaxial silicon layer) 1 through a mask 2 treated with an ordinary photoresist to form an r)-type base in the linear part. At the same time as 3 is formed, a P-type base extraction layer 4 which is applied to the inverter n p r+ 1- transistor in the flL section is formed.

Next, as shown in FIG. 2, a window is opened on the semiconductor surface in the part sandwiched between the base extraction layers 4 in the IIL part, and a shallow base 5 in graph 1 with a low concentration (hovel type) is formed by implanting and diffusing low concentration boron ions. After the formation, a new mask 6 is formed on the surface by a new resist process, as shown in FIG. High concentration arsenic ions are implanted and diffused using this mask 6 to form an n1 type emitter 7 in the linear portion and at the same time form an n+ type collector 8 in the I I L portion.

According to such a technique, the base 5 of graph 1 directly below the collector part has a low concentration and can be formed with a small base width, and β in the inverse transistor of
Although it is possible to improve i, the inventors have found that the miniaturized TTL has the following problems.

In other words, when performing emitter (collector) diffusion on the Graphmy base, it is necessary to take into account the mask alignment margin (d), and the dimensions of the base must be made sufficiently large. However, there was a drawback that the base side wall resistance increased. Furthermore, since the emitter diffusion and base diffusion do not form a self-alignment line, I
The problem of increasing device area and hindering miniaturization has become clear.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned problems.

One object of the present invention is to provide an analog/digital hybrid IC with I1. The purpose of this invention is to increase the degree of integration of the IC and improve its performance by forming the L portion into a graph 1-based structure using a self-alignment method.

Another object of the present invention is to provide a semiconductor device manufacturing technique that enables microfabrication to be performed by iTJ without complicating the process when manufacturing transistors with different amplification factors on one substrate.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, regions of the second conductivity type are formed on the surface of the first conductivity type layer of the semiconductor substrate as the bases of the bipolar transistors constituting the linear circuit and the bases of the ITL inverse transistors constituting the logic circuit, and then Highly concentrated impurities of the first conductivity type are shallowly introduced into a part of the surface of these second conductivity type regions by ion implantation, and a low 4 or 5 degree impurity is added directly below the collector of the second conductivity type region to become an emitter or collector. By deeply introducing and diffusing the impurity of the first conductivity type by ion implantation, a base of the second conductivity type (graft base) with a low concentration compensated for by the impurity of the first conductivity type and a junction depth shallower than the surrounding area is obtained. be.

[Example 1] FIGS. 4 to 6 show an example of the present invention, and show the main part of the process of forming an inverse n p n l-transistor having a base in graph 1 on the surface of a semiconductor substrate. It is a process sectional view.

(1) Prepare an n-type silicon substrate 1 with an impurity concentration of 5 x 10''cm-3 grown on the surface of an n-type silicon layer, for example, a substrate having a V-type buried layer on the surface by an epitaxial method. Then surface oxidation (8
75°C for 160 minutes). The oxide film 2 thus obtained is patterned to form a mask 7 for boron ion implantation. Next, boron (“B”) is ion implanted (2.7X
10"cm-", 40KeV), and is stretched and diffused to form a P-type base layer 9 as shown in FIG.

(2) Photoetch the oxide film 2 on the surface, open a window in the part that will become the collector (emitter) as shown in FIG.
31P+) is introduced deep into the P-type base layer by ion implantation. The Rinne obtuse concentration at this time was 7.5
Q 13cm-2, implant energy 125 KeV
shall be. After this, phosphorus enlargement was carried out 11 times (1000℃40
minutes, N2), a part of the bottom of the P-type layer becomes r
Compensation (compensation l-
) with low P-type concentration (based on graph 1)
It becomes 10.

(3) After this, oxidation (800℃, 30 minutes, dry 02)
Then, arsenic (Δs+) is ion-implanted shallowly into the surface of the I] type base layer through the window opening. At this time, the concentration of arsenic is 5 X L O1gcm-2, and the implantation energy is 50Ke.
Let it be V. After this, annealing oxidation (1000°C130
(N2), an n+ type collector (emitter) 8 is obtained as shown in FIG.

FIG. 7 shows an impurity concentration profile curve obtained by the above process. As shown in the figure, the impurity concentration profile of the bar A' cross section is shown by a solid line, and that of the bar B-B'' cross section is shown by a dotted line.The base depths of the A-A' and B-B' cross sections are compared. Case 1. Base depth N of A-A' cross section
2 is smaller than the base X1 of the BB' cross section. That is, N
It turns out that 2<X goose. In the figure, X3 indicates the diffusion depth of the collector or emitter.

In the above process, since the collector (emitter) and the graft base are formed in a self-aligned manner through one mask, the degree of integration can be increased without using an extra -J method for the base. Furthermore, the base impurity concentration directly under the collector (emitter) can be lowered, and βi of the inverse transistor can be reduced by one white.

[Embodiment 2] FIGS. 8 to 11 show another embodiment of the present invention, in which a bipolar n p n l-transistor serving as a linear part and a logic part are provided on one semiconductor substrate. I
FIG. 3 is a cross-sectional view of a process for forming an IL. Each step will be explained in detail below.

(1) As shown in FIG. 8, an epitaxial T1-type silicon layer 13 having an n+ type buried layer 12 is formed on a P-type silicon substrate (substray h) 11, and this D-type silicon layer is isolated. Several semiconductor island regions in the P+ type layer 14] 3a.

A separated substrate 13b is prepared.

(2) The oxide film 15 is etched to form a window in the base region, and boron (B) ions are implanted and diffused to form a p-type base 16 on the linear part side, as shown in FIG. However, a P-type injector 17 and a p-type base 18 of an inverse transistor are formed in the I I 'LL section.

(3) Next, surface oxidation and 1-etching are performed to open the collector part of the linear part and the collector of ITL (multi-collector part) as shown in FIG.
Place photoresist master 1 on the injector of the IL section.
9, and deeply ion-implant phosphorus (P) through the -4 second window opening.

(4) After this, the collector of the linear part and the multi-collector part of IIL are opened by surface oxidation and photoetching, and arsenic (A
, s) and annealed at the same time as the phosphorus ion-implanted in step (3) above, an n'''' type collector extraction portion 20. is formed in the linear portion as shown in FIG. An r+'' type emitter layer 21 is formed, a multi-collector n+ type layer 22 is formed in the flI portion, and a low concentration P- type graft base is obtained directly below the collector.
FIG. 2 is a plan view of a diffusion pattern in an inverse transistor fabricated by up to the second manufacturing method, and its AA' cross section is shown in FIG. 12Δ. In contrast, FIG. 13 is a plan view of a diffusion pattern in an inverse transistor manufactured by the J& method of the present invention, and its A-A cross section is shown at 1.3A.
Diagram; not shown.

As is clear from comparing the two, according to the present invention, since the graph and the base can be formed directly under the collector n1 type layer, the base area can be reduced by the master margin d, and the element area can be made finer. In addition, since there is no p-type base layer around the I-noctor as shown in FIG. This completes the process as shown in FIG. 14.

[Example 3] In the case of forming npn I-transistors with two or more different types of hFE on the surface of one semiconductor substrate,
The P-type bases of the two 1-transistors are formed by common boron diffusion, and after opening the oxide film window for emitter formation,
Cover one emitter with a mask and implant phosphorus ions.
Thereafter, arsenic ions are implanted into the window openings of both emitters.

For example, in the case of a plurality of transistors that usually have a bFE of 100 to 200, some of them are hFE of about 1000,
In particular, the -1- notation method is effective when it is desired to increase βi as an inverse 1 transistor.

〔effect〕

According to the present invention described in the embodiments above, the following effects can be obtained.

(1) Since the base of the emitter (collector) direct F is implanted with phosphorus in advance, only the base concentration is low (as shown in graph 1), which increases the injection efficiency and increases the βi of the inverse transistor and the cutoff frequency of the ITL. can do.

(2) The P-type layer portion which becomes the region for the base contact 1 can be kept at a high concentration, and an ohmic contact electrode can be obtained.

(3) The emitter (collector) and graft base 1- can be formed in a self-lined manner through a common mask, and there is no need to consider mask margins, which reduces the base area (dimensions) and increases the degree of integration. , the base sidewall resistance is also reduced, and performance can be improved.

(4) Since the base of the linear part and the base of the IIL part can be formed at the same time, the IC can be manufactured without increasing the number of man-hours.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

In the following description of -1-, the invention made by the present inventor is mainly applied to a method of manufacturing a semiconductor device, which is its field of application, but the invention is not limited thereto.

The present invention is particularly effective when applied to a 1C1 IC having a bipolar 1-transistor, and especially to an analog/digital mixed IC that requires miniaturization.

[Brief explanation of the drawing]

FIGS. 1 to 3 show an example of a process for forming an inverse transistor, such as a 1-transistor, which will become a linear part, on a semiconductor substrate, and an inverse transistor, which will become an IIL part. FIG. Embodiment 1 of the present invention is shown in FIGS. 4 to 6, which are cross-sectional views of a process for forming an inverse transistor. FIG. 7 is a curve diagram showing the impurity concentration distribution in the 1-transistor obtained by the method of Example (1). FIG. 8 to FIG. 1I show another embodiment (2) of the present invention, in which linear parts 1 to 1 are formed on one semiconductor substrate.
FIG. 3 is a cross-sectional view of a process for forming a transistor and a T I L; FIG. 12 shows the ITL formed by the conventional method.
FIG. FIG. 12A is a sectional view taken along the line AA in FIG. 12. FIG. 13 is a partial plan view of an IIL formed by the method of the present invention. 13.DELTA. is a sectional view taken along the line AA in FIG. . FIG. 14 is a diagram of the completed device. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Mask, 3... P-type base, 4... P-type base extraction layer, 5... Graft base, 6... Oxide film, 7... 11+ type Emitsuta,
8...n+ type collector, 9...P type base layer, 10
...P-type craft base, 11...p-type silicon substrate, 12...n3 type buried layer, 13...n-type silicon layer, 14...isolation P-type layer, 15・
...Oxide film, 16...P type base, 17...P type injector, 18...P type base, 19...mask,
20...n1 type collector extraction part, 21...n+ type emitter, 22...n1 type Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 6 Fig. ρeptl (μm) Fig. 8 Fig. 9 Figure 10 Figure 11, ?4 Figure 12 Figure 12A Figure A''' Figure 13 Figure 134 r- Figure 14 Procedural amendment (method) 11 indications Patent Application No. 10011 of 1982 Invention Name of semiconductor device and its manufacturing method to be corrected for each item 1 '1 no (7 Jun f patent application Oshima 1j1: '511) + 11 formula ≦, ll: H stand manufacturing agent agent person specification subject to amendment Contents of amendment to the column of the title of the invention

Claims (1)

[Scope of Claims] 1. The base region of the first 1-transistor and the base region of the second 1-transistor having different amplification factors have the same impurity concentration and the same diffusion on one main surface of the semiconductor substrate. Emitters formed at the surface of these base regions (
or the collector) regions are formed with the same impurity concentration and the same diffusion depth, and only the base portion directly below the emitter (or collector) region of the second 1-transistor has a lower impurity concentration than the surrounding base portion, A semiconductor device characterized in that a junction depth is formed to be shallow. 2. The first transistor is a bipolar transistor forming a linear circuit, and the second transistor is an inverter transistor of an injection integrated logic element (IL) forming a logic circuit. The semiconductor device described in . 3. Form a second conductivity type region on the surface of the first conductivity type layer of the semiconductor substrate as a base of the inverse transistor of the implanted integrated logic element, and then form a low concentration first conductivity type region on a part of the surface of the second conductivity type region. The conductivity type impurity is deeply introduced, and then, using the mask used when introducing the low concentration first conductivity type impurity, a high concentration first conductivity type impurity is introduced into the surface of the second conductivity type region (inversely). By forming the collector of the transistor, a second conductivity type base (graph 1. A method for laterally advancing a semiconductor device, comprising forming a base.