JP2000183073A - Semiconductor device with bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bipolar transistor in which power loss in reduced during switching operation. SOLUTION: A P-type base region 3 is formed on the surface of a substrate within an N--type epitaxial region. An N+-type emitter region 5 is formed on the surface of the substrate within the P-type base region 3. As shown in Fig. B, concentration distribution of the base region on the side nearer base-to- collector junction face is made deeper than that of a base-to-emitter junction face. Thereby, the difference between a base-to-emitter voltage Vbe and a base-to-collector voltage Vbc, ΔV is reduced, and thus a collector-to-emitter saturation voltage Vce in a low current region can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a bipolar transistor, and more particularly to an improvement in switching characteristics.

[0002]

2. Description of the Related Art Generally, in a bipolar transistor, it is desirable that the collector-emitter saturation voltage Vce be low. In the low current region, the collector-emitter saturation voltage Vce becomes substantially equal to the difference ΔV between the base-emitter voltage Vbe and the base-collector voltage Vbc.

In order to reduce the difference ΔV, it is conceivable to increase the impurity concentration in the collector region. However, in this case, the punch-through withstand voltage between the collector and the emitter and the current amplification factor decrease. Also, when the impurity concentration in the emitter region is reduced, the carrier injection efficiency is reduced.

An object of the present invention is to solve the above-mentioned problem and to provide a semiconductor device including a bipolar transistor having a small power loss during a switching operation.

[0005]

In a semiconductor device including a bipolar transistor according to the present invention, a PN junction is formed between an emitter region formed of a high-concentration impurity of a first conductivity type and the emitter region. A base region formed of a second conductivity type impurity region provided to form a surface, and a first conductivity type high concentration impurity provided in a non-contact state with the emitter region via the base region; A collector region, wherein the collector region has an impurity concentration lower in the vicinity of the base region than in other portions, and an impurity concentration distribution in the base region. Is characterized in that the collector side is darker than the emitter side.

As described above, the impurity concentration in the vicinity of the base region in the collector region is lower than that in other portions, and the impurity concentration distribution in the base region is higher on the collector side than on the emitter side. Thus, the saturation voltage determined by the difference between the base-emitter voltage and the base-collector voltage can be reduced. Therefore, it is possible to provide a bipolar transistor which can operate at a low power supply voltage and can widen an output power width.

Note that the semiconductor device including a bipolar transistor includes not only an IC including a bipolar transistor, for example, an LSI having both a bipolar transistor and a MOS transistor, but also a single bipolar transistor.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A bipolar transistor 1 according to the present invention will be described with reference to the drawings.

The bipolar transistor 1 is a planar type bipolar transistor, and an N type transistor
^A- type epitaxial region 7 is formed. The N ⁻ type epitaxial region 7 is separated from the element by the P ⁺ region 11. The N ⁻ type epitaxial region 7 has an N ⁺ type region 9 on the side opposite to the substrate surface.

On the surface of the N ⁻ type epitaxial region 7,
A P-type base region 3 is formed so as to form a PN junction surface. P type base region 3 is surrounded by N ⁻ type epitaxial region 7. An N ⁺ -type emitter region 5 is formed on the substrate surface in the P-type base region 3 so as to form a PN junction surface. The N ⁺ type emitter region 5 is surrounded by the base region 3. On the substrate surface in the N ⁻ -type epitaxial region 7, N
^{A +} type region 8 is formed. The N ⁻ type epitaxial region 7 and the N ⁺ type regions 8 and 9 correspond to the collector region.

FIG. 1B shows the relationship between the depth from the substrate surface and the impurity concentration in the AA ′ section of FIG. Solid line β
Is the impurity concentration distribution of the bipolar transistor 1,
The dashed line α is the impurity concentration distribution of the conventional bipolar transistor.

As described above, the concentration distribution of the emitter region and the collector region is the same as the conventional one, but the concentration distribution of the base region becomes deeper as it approaches the base-collector junction surface side than the base-emitter junction surface side. in this way,
By making the impurity concentration distribution of the base region higher on the collector side than on the emitter side, the difference ΔV between the base-emitter voltage Vbe and the base-collector voltage Vbc is reduced, and the collector-emitter saturation voltage Vce in the low current region is reduced. Can be reduced. As a result, power loss at the time of switching operation is reduced, and operation at a low power supply voltage becomes possible. Further, the output power width can be widened.

FIG. 2 illustrates a method of manufacturing the bipolar transistor 1. As in the conventional case, the P-type substrate 2
Then, an N ^- type epitaxial region 7, a P ⁺ region 11, and an N ⁺ type region 9 are formed, and a silicon oxide film 13 and a resist 27 for forming a base region are formed on the N ^- type epitaxial region 7. In this state, boron as a P-type impurity is ion-implanted at high energy (FIG. 2).
A). In this embodiment, the implantation energy is 200 Ke.
Ion implantation was performed at v to 1 Mev and an impurity concentration of 5E13 to 1E15 cm ⁻² . Thus, an impurity region having a base diffusion concentration peak is formed in a deep portion of N ⁻ type epitaxial region 7. 900-1200 ° N ₂ or O ₂ or 6 hours annealed 10 minutes in their mixed atmosphere conditions. Thereby, the base region 3 is formed as shown in FIG. 2B.

Thereafter, as in the conventional case, a portion of the silicon oxide film 13 is selectively etched to form a thin film portion 13a. As shown in FIG. 2C, phosphorus or arsenic is implanted with an implantation energy of 50 K using silicon oxide film 13 as a mask.
ev ~ 150Kev, impurity concentration 1E15 ~ 5E16c
Ion implantation is performed at m- ² . 900-1100 ° N ₂ or O ₂ or 3 hours annealed 10 minutes in their mixed atmosphere conditions. Thereby, as shown in FIG. 2D, an emitter region 5 and an N ⁻ type region 8 are formed.

As described above, in the present embodiment, impurity ion implantation is performed with a higher implantation energy than in the past in order to change the impurity concentration distribution.

After the base region is formed as shown in FIG. 2B, an opening is provided in the silicon oxide film 13, an N ⁺ type polysilicon electrode is formed (FIG. 3A), and annealing is performed to obtain an N ⁺ -type polysilicon electrode. As shown in (1), a shallow N ⁺ type region can be formed and used as an emitter region.

Further, as shown in FIG. 4A, the base region may have a graft base structure. A- of FIG. 4A
FIG. 5 shows the distribution of the impurity concentration in the A ′ and BB ′ cross sections.
As described above, the base region 3 includes the region 3a near the center where the emitter is formed and the region 3b which is deeper than the region 3a.
It is composed of The region 3a is P-type, and the region 3b is P-type.
⁺ Region. As shown in FIG.
An emitter 5 is formed at a.

By employing such a graft base structure, the radius of curvature at the base surface can be increased,
A decrease in breakdown voltage due to electric field concentration can be prevented.

In the above embodiment, the high-energy ion implantation is performed so that the concentration peak is located on the side closer to the collector junction surface. However, it can be realized by another manufacturing method. For example, as shown in FIG. 6A, a silicon oxide film 13 is formed as an insulating film on the N epitaxial region 7, an opening is provided in a part of the silicon oxide film 13, and a P-type Area 3
Form one. As shown in FIG. 6B, the impurity concentration of the P-type region 31 is formed so as to increase as the depth increases.
As shown in FIG. 6C, an N ⁺ type region 32 is formed above the P type region 31. The N ⁺ type region 32 can be formed by, for example, ion implantation or doping from N ⁺ polysilicon. As shown in FIG. 6D, the impurity distribution of the base region 31 is such that the concentration gradient is gentler on the base-emitter junction surface side than on the base-collector junction surface side, and the region with the highest concentration is the base collector region. It is on the joint side. In addition,
In this case, the P-type region 31 becomes a base region, and the N ⁺ -type region 32 becomes an emitter region.

In this embodiment, the case where the bipolar transistor for an integrated circuit is formed on a semiconductor substrate has been described. However, the present invention can be similarly applied to a single bipolar transistor.

Further, other than the planar type transistor,
The present invention can be applied to other bipolar transistors, for example, junction type transistors.

In this embodiment, the concentration distribution in the base region is smoothly changed. However, any impurity concentration distribution that can reduce the difference between the base-emitter voltage and the base-collector voltage can be used. It may be.

[Brief description of the drawings]

FIG. 1 is a sectional view and a distribution of impurity concentration of a main part of a bipolar transistor 1 according to the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing the bipolar transistor 1.

FIG. 3 is a view showing another method of manufacturing the bipolar transistor 1;

FIG. 4 is a cross-sectional view of a main part of another bipolar transistor.

5 is a diagram showing an impurity concentration distribution of the bipolar transistor 1 of FIG.

FIG. 6 is a cross-sectional view of a main part of a bipolar transistor according to another embodiment.

[Explanation of symbols]

1 Bipolar transistor 2 Substrate 3 Base region 5 Emitter region layer 7 N ^- type epitaxial region 11 P ⁺ Region 13 ··· silicon oxide film 31 ··· base region 32 ··· emitter region

Claims (1)

[Claims] An emitter region formed of a high concentration impurity of a first conductivity type; and a base formed of an impurity region of a second conductivity type provided to form a PN junction surface with the emitter region. A collector region comprising a first conductive type high-concentration impurity provided in a non-contact state with the emitter region via the base region; The impurity concentration of the region is lower in the vicinity of the base region than in other portions, and the impurity concentration distribution of the base region is higher on the collector side than on the emitter side. Including semiconductor devices.