JPS61207064A - Bi-polar transistor - Google Patents
Bi-polar transistorInfo
- Publication number
- JPS61207064A JPS61207064A JP60047829A JP4782985A JPS61207064A JP S61207064 A JPS61207064 A JP S61207064A JP 60047829 A JP60047829 A JP 60047829A JP 4782985 A JP4782985 A JP 4782985A JP S61207064 A JPS61207064 A JP S61207064A
- Authority
- JP
- Japan
- Prior art keywords
- region
- base region
- base
- emitter
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 14
- 239000012535 impurity Substances 0.000 abstract description 11
- 230000006798 recombination Effects 0.000 abstract description 6
- 238000005215 recombination Methods 0.000 abstract description 6
- 239000000969 carrier Substances 0.000 abstract description 3
- 230000008033 biological extinction Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体集積回路（ＩＣ）に組込まれるバイポー
ラトランジスタのｈａｌｌ値コントロールに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to hall value control of a bipolar transistor incorporated in a semiconductor integrated circuit (IC).
（ロ）従来の技術
従来のバイポーラトランジスタとしては、例えば特開昭
５９−２３４３号公報に開示されている。(B) Prior Art A conventional bipolar transistor is disclosed in, for example, Japanese Patent Laid-Open No. 59-2343.
第４図はこのようなバイポーラトランジスタを示し、（
１）はＰＭ半導体基板、（２）はＮ 型埋込層。Figure 4 shows such a bipolar transistor, (
1) is a PM semiconductor substrate, and (2) is an N-type buried layer.
（３）はＮ−型エピタキシャル層、（４）はＰ 型分離
領域、（５）は分離領域（４）により島状に分離された
複数の島領域である。そして島領域（５）表面にＰ型不
純物を拡散して第１のベース領域（６）を形成し、後に
Ｎ型不純物を拡散してエミッタ領域（７）及びコレクタ
コンタクト領域（８）を形成し、ＮＰＮ型トランジスタ
を構成する。この時他の島領域（５）においても前述し
た拡散工程で同時にＮＰＮ型トランジスタが形成されて
いる。(3) is an N-type epitaxial layer, (4) is a P-type isolation region, and (5) is a plurality of island regions separated into island shapes by the isolation region (4). P-type impurities are then diffused into the surface of the island region (5) to form a first base region (6), and later N-type impurities are diffused to form an emitter region (7) and a collector contact region (8). , constitutes an NPN type transistor. At this time, an NPN transistor is also formed in the other island region (5) at the same time by the above-described diffusion process.
斯上した如く構成したトランジスタのｈ□値は。The h□ value of the transistor constructed as above is.
ベース領域（６）及びエミッタ領域（７）の不純物濃度
。Impurity concentration in the base region (6) and emitter region (7).
ベース幅（第４図図中に′Ｂ”で示す）により決定する
。従って各々の島領域（５）に同時に形成する限り、従
来のトランジスタは何れもほぼ均一なｈ□値になる。It is determined by the base width (indicated by 'B'' in FIG. 4). Therefore, as long as they are formed in each island region (5) at the same time, all conventional transistors have a substantially uniform h□ value.
（ハ）発明が解決しようとする問題点
しかしながら、ユーザーの要求や回路構成上の必要性か
ら同一チップ上に複数の異るｈ□値をもつトランジスタ
を形成したい場合、従来のトランジスタではそれぞれの
ｈ１値ごとに拡散工程を追加しなければならず、同時に
は形成できないという欠点があった。(c) Problems to be Solved by the Invention However, when it is desired to form transistors with a plurality of different h□ values on the same chip due to user requests or circuit configuration needs, conventional transistors There was a drawback that a diffusion process had to be added for each value, and that they could not be formed at the same time.
に）問題点を解決するための手段
本発明は斯上した欠点に鑑みてなされ、同一チップ上に
様々なｈ□値をもつトランジスタを形成することを目的
とし、エミッタ領域−に一部重畳し且つ第１のベース領
域（ト）より深い第２のベース領域（２）を設け、第２
のベース領域（ハ）とエミッタ領域−との重畳面積の変
化でｈ□値をコントロールすることを特徴とする。B) Means for Solving the Problems The present invention was made in view of the above-mentioned drawbacks, and aims to form transistors with various h□ values on the same chip. In addition, a second base region (2) deeper than the first base region (G) is provided, and a second base region (2) is provided.
It is characterized by controlling the h□ value by changing the overlapping area of the base region (c) and the emitter region.
（ホ）作用
本発明によれば、第２のベース領域（ホ）のベース幅［
Ｆ］）がより広いのでベースでの注入担体の消滅による
再結合電流が増加し、ｈ□値は小さくなる。(e) Effect According to the present invention, the base width of the second base region (e) [
Since F]) is wider, the recombination current due to the annihilation of implanted carriers at the base increases, and the h□ value becomes smaller.
その値は重畳面積により増減し１重畳面積が大であれば
第２のベース領域−による再結合電流の増加が大きいの
でり、Ｎ値は小となる。The value increases or decreases depending on the overlapping area, and if the overlapping area is large, the increase in recombination current due to the second base region is large, so the N value becomes small.
（へ）実施例
以下本発明の実施例を図面を参照しながら説明の第１の
実施例を示し、αωはＰＷ半導体基板 Ｕ （’１１．
’・１“
はＮｕ埋込層、（２）はＮ型エピタキシャル層、α→゛
はＰ 型分離領域、（至）（２）は分離領域０局により
島状に分離された複数の島領域、ση叫はＰ型第１のベ
ース領域、ＱＩ翰はＮ 型エミッタ領域、ＱＢ（ハ）は
Ｎ“型コレクタコンタクト領域、＠はＰ 型梁２のベー
ス領域、（ハ）は酸化膜、＠（ホ）・・・・・・銅は夫
々の領域上に設けられた電極である。(F) Example Hereinafter, a first example of the present invention will be described with reference to the drawings, and αω is a PW semiconductor substrate U ('11.
'・1'' is a Nu buried layer, (2) is an N-type epitaxial layer, α→゛ is a P-type isolation region, (to) (2) is a plurality of island regions separated into islands by isolation region 0 stations. , ση is the P-type first base region, QI wire is the N-type emitter region, QB (c) is the N"-type collector contact region, @ is the base region of the P-type beam 2, (c) is the oxide film, @ (e) Copper is an electrode provided on each region.
而して、島領域α■には同一チップ上で最も大きいｈ□
値をもつＮＰＮ型トランジスタが形成され。Therefore, the island area α■ has the largest h□ on the same chip.
An NPN transistor with a value of .
島領域（２）には第２のベース領域−により小さいｈＦ
ｍ値をもつＮＰＮ型トランジスタが形成されている。The island region (2) has a second base region - a smaller hF
An NPN transistor having a value of m is formed.
本発明の最も特徴゛とする点は、エミッタ領域（ホ）と
一部重量し且つ第１のベース領域（ト）より深い第２の
ベース領域−を形成した点にある。この構造によれば、
第２のベース領域−のベース＠（１重１図図中に”Ｂ′
”で示す）がより広いのでトランジスタのベースでの注
入担体の消滅による再結合電流が増し、ｈＦｌ値は小さ
くなる。その値は３つのパタメータ、すなわち第２のベ
ース領域−の不純物濃度、拡散深さ及び第２のベース領
域−とエミッタ領域−との重畳面積により決定するが、
これを夫々の島領域（至）に同時に形成すれば不純物濃
度と拡散深さは全て均一なのでｈ□値をコントロールす
るには第２のベース領域−とエミッタ領域−との重畳面
積による。前記重畳面積が大きくなれば第２のベース領
域−による再結合電流の増加が大きいのでｈ□値は小と
なる。The most distinctive feature of the present invention is that a second base region is formed which partially overlaps the emitter region (e) and is deeper than the first base region (g). According to this structure,
The base of the second base region
”) is wider, the recombination current due to the annihilation of the implanted carriers at the base of the transistor increases, and the hFl value becomes smaller. Its value depends on three parameters: the impurity concentration in the second base region, the diffusion depth. It is determined by the overlap area of the second base region and emitter region,
If this is formed simultaneously in each island region, the impurity concentration and diffusion depth will all be uniform, so the h□ value can be controlled by the overlapping area of the second base region and the emitter region. As the overlapping area increases, the increase in recombination current due to the second base region increases, so the h□ value decreases.
従って本発明によれば、ｈ□値の最も高いトランジスタ
を第１のベース領域αηのみの構造とし。Therefore, according to the present invention, the transistor with the highest h□ value has a structure including only the first base region αη.
ｈ□値が小さくなるに従って前記重畳面積を大とすれば
同一チップ上に様々なｈｒｍ値をもつトランジスタを同
時に形成することができる。By increasing the overlapping area as the h□ value decreases, transistors having various hrm values can be simultaneously formed on the same chip.
実験によれば、ベース拡散深さ２．３μ、セミツタ拡散
深さ１．８μ、ｈ□＝３００のトランジスタに、前記重
畳面積をエミッタ面積の約３０％として拡散深さ４．７
ｐ、不純物濃度５． ＯＸ １０”ａｔｏｍｓ・ｃＩｒ
Ｌ−’の第２のベース領域−を形成したところ。According to experiments, a transistor with a base diffusion depth of 2.3μ, a semi-vine diffusion depth of 1.8μ, and h□=300 has a diffusion depth of 4.7μ with the overlapping area being about 30% of the emitter area.
p, impurity concentration5. OX 10”atoms・cIr
The second base region of L-' is formed.
ｈ□＝１００前後にコントロールできた。It was possible to control h□=around 100.
第２図（イ）（ロ）は本発明の第２の実施例を示してい
る。本実施例では第２のベース領域−をエミッタ領域−
と一部重畳すると共に、第１のベース領域（至）の周辺
部にリング状に設けている。この構造によれば、第２の
ベース領域（２）の拡散深さがより深いことから領域底
部でのＰＮ接合の曲率半径（２）が大きくなり、電界集
中を緩和できるので静電破壊に強くなる。また第１の実
施例と同様にｈ□値をコントロールできる。FIGS. 2A and 2B show a second embodiment of the present invention. In this embodiment, the second base region is the emitter region.
It partially overlaps with the first base region, and is provided in a ring shape around the first base region. According to this structure, since the diffusion depth of the second base region (2) is deeper, the radius of curvature (2) of the PN junction at the bottom of the region becomes larger, and electric field concentration can be alleviated, making it resistant to electrostatic damage. Become. Further, the h□ value can be controlled similarly to the first embodiment.
以下本発明による第１の実施例の製造方法を第３図（イ
）〜に）を参照しながら説明する。The manufacturing method of the first embodiment according to the present invention will be explained below with reference to FIGS.
先ず第３図（イ）に示す如く、Ｐ型半導体基板（ロ）に
Ｎ 型埋込層（２）をドープした後エピタキシャル成長
法を用いてエピタキシャル層（至）を形成し ｐ＋型分
離領域α４を形成することにより複数の島領域（至）（
至）を形成する。First, as shown in FIG. 3(A), a P type semiconductor substrate (B) is doped with an N type buried layer (2), and then an epitaxial layer (2) is formed using an epitaxial growth method to form a p+ type isolation region α4. By forming multiple island areas (to) (
to form).
次に第３図（ロ）に示す如く１選択拡散法を用いてＰ型
不純物１例えばボロンを拡散し、所望の島領域（至）に
第２のベース領域−を形成する。拡散窓の大きさは後に
形成するエミッタ領域翰との重畳面積で所望のｈ□値が
得られるようＫする。Next, as shown in FIG. 3(B), a P-type impurity 1, for example, boron, is diffused using a selective diffusion method to form a second base region in a desired island region. The size of the diffusion window is determined so that a desired h□ value can be obtained by the area of overlap with the emitter region that will be formed later.
次に第３図（ハ）に示す如く、選択拡散法を用いてＰ型
不純物を拡散し、トランジスタを形成する島領域（至）
（至）に第１のベース領域α力（ト）を形成し、続いて
Ｎ型不純物１例えばすｙ（Ｐ）を拡散してエミッタ領域
α■東コレクタコンタクト領域＠η翰を形成する。Next, as shown in FIG. 3(c), P-type impurities are diffused using a selective diffusion method to form an island region (to) where a transistor will be formed.
First, a first base region α is formed, and then an N-type impurity 1, for example, sy(P) is diffused to form an emitter region α■east collector contact region @η翰.
そして、第３図に）に示す如く酸化膜（ハ）にコンタク
トホールなあけた後に周知の蒸着技術にて電極部材、例
えばアルミ（１りを蒸着し、所望形状にエツチングして
各領域上に電極ｅｊ４ｍ・・・・・・（１）（ロ）（至
）を設けて完成する。After forming contact holes in the oxide film (c) as shown in Figure 3), an electrode member, such as aluminum (1), is deposited using a well-known vapor deposition technique and etched into a desired shape on each region. Electrodes ej4m... (1) (B) (To) are provided and completed.
同図では島領域（至）には最も高いｈ□値をもつトラン
ジスタが、島領域（２）にはそれより小さいｈ□値をも
つトランジスタが形成されている。In the figure, a transistor with the highest h□ value is formed in the island region (to), and a transistor with a smaller h□ value is formed in the island region (2).
（ト）発明の詳細
な説明した如く１本発明によれば１回の拡散工程を追加
するだけで同一チップ上に様々なｈ□値をもつトランジ
スタを同時に形成することができるので、ユーザーの要
求に即対応でき、回路設計がより容易になる。(G) As described in detail, according to the present invention, transistors with various h□ values can be simultaneously formed on the same chip by adding one diffusion process, so that it is possible to meet the user's requirements. This makes circuit design easier.
さらに第２の実施例によれば静電破壊に強くなるので信
頼性向上に寄与する。Furthermore, the second embodiment is resistant to electrostatic damage, contributing to improved reliability.
第１図（イ）（ロ）はそれぞれ本発明の第１の実施例を
説明するだめの断面図、平面図、第２図８）（ロ）はそ
れぞれ本発明の第２の実施例を説明するための断面図、
平面図、＠３図（イ）〜に）は本発明の第１の実施例の
製造方法を説明する断面図、第４図（イ）（ロ）はそれ
ぞれ従来のバイポーラトランジスタを示す断面図、平面
図である。
主な図番の説明
αＢは半導体基板、ＱＱ（至）は島領域、 αη（９）
は第１のベース領域、 （イ）は第２のベース領域。
ｃＩ窃翰はエミッタ領域、 ［３１Ｂ）はベース暢で
ある。
次
ζＱ：、：、 ２ １ｊ（す
Ｃ）
紀Ｓ い
ン５
Ｃ）
ビ −はFigures 1 (a) and (b) are cross-sectional views and plan views for explaining the first embodiment of the present invention, and Figures 2 and 8) (b) are for explaining the second embodiment of the present invention, respectively. A cross-sectional view for
A plan view, Figures 3 (a) to 3) are cross-sectional views explaining the manufacturing method of the first embodiment of the present invention, and Figures 4 (a) and (b) are cross-sectional views showing conventional bipolar transistors, respectively. FIG. Explanation of main figure numbers αB is the semiconductor substrate, QQ (to) is the island region, αη (9)
is the first base area, and (a) is the second base area. cI control is the emitter area, [31B) is the base control. Next
ζQ:, :, 2 1j (S C) Ki S in 5 C) B - is
Claims (1)
タキシャル層と該エピタキシャル層を島状に分離した島
領域と該島領域表面に二重に形成した一導電型の第１の
ベース領域及び逆導電型のエミッタ領域とを備えたバイ
ポーラトランジスタにおいて、前記エミッタ領域と一部
重畳し且つ前記ベース領域より深い第２のベース領域を
備え、該第２のベース領域と前記エミッタ領域との重畳
面積を変化させることによりｈ＿■＿■値をコントロー
ルした事を特徴とするバイポーラトランジスタ。(1) An epitaxial layer of the opposite conductivity type formed on a semiconductor substrate of one conductivity type, an island region in which the epitaxial layer is separated into islands, and a first base region of one conductivity type formed double on the surface of the island region. and a second base region that partially overlaps with the emitter region and is deeper than the base region, wherein the second base region and the emitter region overlap. A bipolar transistor characterized by controlling the h_■_■ value by changing the area.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60047829A JPS61207064A (en) | 1985-03-11 | 1985-03-11 | Bi-polar transistor |
| KR1019860000499A KR900001244B1 (en) | 1985-03-11 | 1986-01-27 | Bipolar transistor |
| CN86100522.8A CN1003149B (en) | 1985-03-11 | 1986-03-07 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60047829A JPS61207064A (en) | 1985-03-11 | 1985-03-11 | Bi-polar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61207064A true JPS61207064A (en) | 1986-09-13 |
Family
ID=12786241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60047829A Pending JPS61207064A (en) | 1985-03-11 | 1985-03-11 | Bi-polar transistor |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS61207064A (en) |
| KR (1) | KR900001244B1 (en) |
| CN (1) | CN1003149B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1315186C (en) * | 2004-05-01 | 2007-05-09 | 江苏长电科技股份有限公司 | Mini flipchip transistor and method for manufacturing same |
-
1985
- 1985-03-11 JP JP60047829A patent/JPS61207064A/en active Pending
-
1986
- 1986-01-27 KR KR1019860000499A patent/KR900001244B1/en not_active IP Right Cessation
- 1986-03-07 CN CN86100522.8A patent/CN1003149B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CN1003149B (en) | 1989-01-25 |
| KR900001244B1 (en) | 1990-03-05 |
| KR860007726A (en) | 1986-10-15 |
| CN86100522A (en) | 1986-09-10 |
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