JPH0439789B2 - - Google Patents
Info
- Publication number
- JPH0439789B2 JPH0439789B2 JP59162551A JP16255184A JPH0439789B2 JP H0439789 B2 JPH0439789 B2 JP H0439789B2 JP 59162551 A JP59162551 A JP 59162551A JP 16255184 A JP16255184 A JP 16255184A JP H0439789 B2 JPH0439789 B2 JP H0439789B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- type
- buried
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000009792 diffusion process Methods 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 description 11
- 239000007924 injection Substances 0.000 description 11
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は半導体注入集積論理回路装置（以下、
IILという。）の製造方法に関する。[Detailed Description of the Invention] (a) Industrial Application Field The present invention relates to a semiconductor injection integrated logic circuit device (hereinafter referred to as
It is called IIL. ).
(ロ) 従来の技術
一つの半導体基板上に二つのトランジスタQI，
QRを第２図に示すように構成されたIILは、一般
に第３図に示すように、注入側をラテラルPNP
トランジスタQIとし、出力側を逆方向縦形NPN
トランジスタQRとして、ラテラルPNPトランジ
スタQIのコレクタを逆方向縦形NPNトランジス
タQRのベースと共用する構造を有する。すなわ
ち、Ｐ型シリコン基板１上にN+型の埋め込み層
２を設け、基板１上にエピタキシヤル成長で形成
されたN-型のエピタキシヤル層３をP+型の分離
領域４で島状に分離して島領域５が形成される。
この島領域５にＰ型拡散領域６，７およびＮ型拡
散領域８，９を順次不純物拡散によつて形成し、
酸化膜３ａに設けた電極孔を介して電極１０〜１
４が設けられている。そして、ラテラルPNPト
ランジスタQIはＰ型拡散領域６がエミツタ（イ
ンジエクタ）、エピタキシヤル層（島領域５）が
ベース、Ｐ型拡散層７がコレクタでベース接地で
働く。一方逆方向縦形NPNトランジスタQRはエ
ピタキシヤル層（島領域５）がエミツタ、Ｐ型拡
散領域７がベース、Ｎ型拡散領域８，９がコレク
タとなつている。(b) Conventional technology Two transistors Q I on one semiconductor substrate,
An IIL configured with Q R as shown in Figure 2 generally has a lateral PNP on the injection side as shown in Figure 3.
Transistor Q I , reverse vertical NPN on output side
The transistor Q R has a structure in which the collector of the lateral PNP transistor Q I is shared with the base of the reverse vertical NPN transistor Q R. That is, an N + type buried layer 2 is provided on a P type silicon substrate 1, and an N - type epitaxial layer 3 formed by epitaxial growth on the substrate 1 is formed into an island shape with a P + type isolation region 4. Island regions 5 are formed by separation.
P-type diffusion regions 6, 7 and N-type diffusion regions 8, 9 are sequentially formed in this island region 5 by impurity diffusion,
Electrodes 10 to 1 are inserted through the electrode holes provided in the oxide film 3a.
4 is provided. The lateral PNP transistor Q I operates with the P-type diffusion region 6 as the emitter (injector), the epitaxial layer (island region 5) as the base, and the P-type diffusion layer 7 as the collector, with the base being grounded. On the other hand, in the reverse vertical NPN transistor Q R , the epitaxial layer (island region 5) serves as an emitter, the P type diffusion region 7 serves as a base, and the N type diffusion regions 8 and 9 serve as a collector.
このようなIILにおいては、高速動作を行うべ
く、逆方向縦形NPNトランジスタの高い逆方向
電流増幅率βiを得るために、N+型のカラー領域
１５でベース領域、Ｐ型拡散領域６，７を取り囲
んでいた（例えば、特公昭49−35030号公報に詳
しい。）。 In such an IIL, in order to achieve high-speed operation and a high reverse current amplification factor βi of the reverse vertical NPN transistor, the base region and the P-type diffusion regions 6 and 7 are formed in the N + type collar region 15. (See, for example, Japanese Patent Publication No. 49-35030 for details.)
(ハ) 発明が解決しようとする問題点
しかしながら第２図に示すように、従来のIIL
は、N+型のカラー領域１５を島領域５表面に形
成しているため、島領域５表面でのホールの逆注
入は抑えることができるが、カラー領域１５直下
からのホールの逆注入は大きくホールの逆注入を
一定以上に小さくできず、逆方向電流増幅率βiを
あまり大きくすることはできなかつた。(c) Problems to be solved by the invention However, as shown in Figure 2, the conventional IIL
Since the N + type collar region 15 is formed on the surface of the island region 5, the back injection of holes at the surface of the island region 5 can be suppressed, but the back injection of holes from directly below the collar region 15 is greatly suppressed. It was not possible to reduce the reverse injection of holes beyond a certain level, and it was not possible to increase the reverse current amplification factor βi very much.
また、ホールの逆注入を小さくするために、カ
ラー領域１５を深く拡散しようとすれば、カラー
領域１５の横方向拡散が大きくなり、集積度を上
げることができないなどの問題点があつた。 Further, if an attempt is made to diffuse the collar region 15 deeply in order to reduce the back injection of holes, the lateral diffusion of the collar region 15 becomes large, resulting in problems such as an inability to increase the degree of integration.
更に、IILはラテラルPNPトランジスタQIのコ
レクタを逆方向縦形NPNトランジスタQRのベー
スとして共用する構造としているため、ラテラル
PNPトランジスタQIの動作の関係上逆方向縦形
NPNトランジスタQRのベース領域の全周をエピ
タキシヤル層表面に形成するカラー領域１５で取
り囲むことはできない。従つて、第１図に示すよ
うにＰ型拡散領域６とＰ型拡散領域７との間には
N+型のカラー領域１５は設けていないので、そ
の領域からのホールの逆注入は抑制できず、逆方
向電流増幅率βiをあまり大きくすることはできな
かつた。 Furthermore, since the IIL has a structure in which the collector of the lateral PNP transistor Q I is shared as the base of the reverse vertical NPN transistor Q R , the lateral
Due to the operation of PNP transistor Q I , reverse vertical type
The entire circumference of the base region of the NPN transistor Q R cannot be surrounded by the collar region 15 formed on the surface of the epitaxial layer. Therefore, as shown in FIG. 1, there is a gap between P type diffusion region 6 and P type diffusion region 7.
Since the N + type collar region 15 is not provided, the reverse injection of holes from that region cannot be suppressed, and the reverse current amplification factor βi cannot be made very large.
(ニ) 問題点を解決するための手段
本発明は上述した従来の問題点を解決するため
になされたもので、一導電型の半導体基板上に逆
導電型の埋め込み層となる不純物堆積層を形成す
る工程と、前記堆積層の不純物の拡散速度より拡
散速度の速い逆導電型の不純物を前記堆積層の所
望位置に注入してベース領域を取り囲む埋め込み
カラー領域となる第２堆積層を形成する工程と、
前記基板上に逆導電型のエピタキシヤル層を形成
する工程と、前記埋め込み層上のエピタキシヤル
層表面の所望箇所に一導電型の不純物を拡散し
て、インジエクタ領域と埋め込みカラー領域に取
り囲まれたベース領域とを形成する工程と、逆導
電型の不純物を前記ベース領域表面およびエピタ
キシヤル層表面に拡散することにより、前記ベー
ス領域にコレクタ領域を形成すると共に、前記エ
ピタキシヤル層表面に前記インジエクタ領域およ
びベース領域を取り囲むカラー領域を形成する工
程と、からなる。(d) Means for Solving the Problems The present invention has been made to solve the above-mentioned conventional problems, and consists of forming an impurity deposited layer to serve as a buried layer of the opposite conductivity type on a semiconductor substrate of one conductivity type. forming a second deposited layer that becomes a buried collar region surrounding the base region by implanting an impurity of an opposite conductivity type whose diffusion rate is faster than that of the impurity in the deposited layer into a desired position of the deposited layer; process and
forming an epitaxial layer of opposite conductivity type on the substrate, and diffusing impurities of one conductivity type to a desired location on the surface of the epitaxial layer on the buried layer to form an epitaxial layer surrounded by an injector region and a buried collar region; By forming a base region and diffusing impurities of opposite conductivity type to the surface of the base region and the surface of the epitaxial layer, a collector region is formed in the base region, and a collector region is formed in the surface of the epitaxial layer. and forming a color region surrounding the base region.
(ホ) 作用
本発明によれば、横方向拡散を大きくせずにベ
ース領域の側面を高濃度の埋め込みカラー領域で
取り囲むことができる。(e) Effects According to the present invention, the side surfaces of the base region can be surrounded by a high-density embedded color region without increasing lateral diffusion.
(ヘ) 実施例
第１図イ〜トは本発明による製造方法の各工程
の断面図を示すものである。(f) Example FIGS. 1A to 1I show cross-sectional views of each step of the manufacturing method according to the present invention.
(i) Ｐ型シリコン半導体基板１の表面に酸化膜３
０等をマスクとしてN+型埋め込み層２を形成
するためにアンチモン（sb）をデボ拡散して不
純物堆積層２１を形成する（第１図イ）。(i) Oxide film 3 on the surface of P-type silicon semiconductor substrate 1
In order to form an N + type buried layer 2, antimony (SB) is deposited and diffused using a mask such as 0 as a mask to form an impurity deposited layer 21 (FIG. 1A).
(ii) 不純物堆積層２１の所望の位置、すなわち、
ベース領域７を取り囲む位置に、N+型の埋め
込みカラー領域２０を形成するために酸化膜３
１等をマスクとして不純物堆積層２１の不純物
拡散速度より拡散速度の早いＮ型の不純物、本
実施例ではリンＰをイオン注入して第２堆積層
２２を形成する（第１図ロ）。(ii) the desired position of the impurity deposition layer 21, i.e.
At a position surrounding the base region 7, an oxide film 3 is formed to form an N + type buried collar region 20.
The second deposited layer 22 is formed by ion-implanting an N-type impurity whose diffusion rate is faster than that of the impurity deposited layer 21, in this example, phosphorus P, using the second deposited layer 22 as a mask (FIG. 1B).
(iii) 基板１上に気相によりN-型のエピタキシヤ
ル層３を成長させる。このN-型エピタキシヤ
ル層３の成長により、前記工程でデボジツトお
よびイオン注入して形成された不純物堆積層２
１および第２堆積層２２が拡散して埋め込み層
２と埋め込みカラー領域２０が形成される（第
１図ハ）。(iii) An N - type epitaxial layer 3 is grown on the substrate 1 in a vapor phase. By the growth of this N - type epitaxial layer 3, the impurity deposited layer 2 formed by depositing and ion implantation in the previous step is removed.
The first and second deposited layers 22 are diffused to form a buried layer 2 and a buried collar region 20 (FIG. 1c).
(iv) エピタキシヤル層３表面の酸化膜３２をマス
クにして、ボロンＢを拡散して基板１に達する
P+型の分離領域４を形成する。この分離領域
４によりエピタキシヤル層３を島状にPN接合
分離して島領域５が形成される。また、この熱
処理によつて埋め込み層２および埋め込みカラ
ー領域１６は上下方向に拡散された所定の巾を
有する埋め込み層２と所定のはい上り量を有す
る埋め込みカラー領域１６が形成される（第１
図ニ）。(iv) Using the oxide film 32 on the surface of the epitaxial layer 3 as a mask, boron B is diffused to reach the substrate 1.
A P + type isolation region 4 is formed. This isolation region 4 separates the epitaxial layer 3 into island-like PN junctions to form island regions 5. Further, by this heat treatment, the buried layer 2 and the buried collar region 16 are vertically diffused to form a buried layer 2 having a predetermined width and a buried collar region 16 having a predetermined creeping amount (the first
Figure 2).
(v) 島領域５表面にＰ型の不純物拡散によりＰ型
のインジエクタ領域６およびＰ型のベース領域
７を形成する。すなわち、エピタキシヤル層３
表面の酸化膜３３をマスクにしてボロン(B)を拡
散して、インジエクタ領域６と埋め込みカラー
領域２０に隣接してベース領域７を形成する。
そして、ベース領域７の全周は埋め込みカラー
領域２０で取り囲まれることになる（第１図
ホ）。(v) A P-type injector region 6 and a P-type base region 7 are formed on the surface of the island region 5 by diffusing P-type impurities. That is, epitaxial layer 3
Using the surface oxide film 33 as a mask, boron (B) is diffused to form a base region 7 adjacent to the injector region 6 and the buried collar region 20.
Then, the entire circumference of the base region 7 is surrounded by the embedded color region 20 (FIG. 1(e)).
(vi) さいごにＮ型の不純物拡散を行なう。すなわ
ち、エピタキシヤル層３の酸化膜３４をマスク
にしてベース領域７表面とベース領域７および
インジエクタ領域６を取り囲む島領域５表面に
リン(P)を拡散する。この拡散工程によりベース
領域７にコレクタ領域８，９が形成されると共
に、ベース領域７およびインジエクタ領域６を
取り囲むN+型カラー領域１５が島領域５表面
に形成される。そしてこのカラー領域１５は、
埋め込みカラー領域２０に接するように形成さ
れており、カラー領域１５で取り囲まれている
ベース領域７の周囲は埋め込みカラー領域２０
とカラー領域１５という高濃度領域で取り囲ま
れている。また、インジエクタ領域６とベース
領域７との間の島領域５表面にはカラー領域１
５は拡散形成されていない（第１図ヘ）。(vi) Finally, N-type impurity diffusion is performed. That is, using the oxide film 34 of the epitaxial layer 3 as a mask, phosphorus (P) is diffused into the surface of the base region 7 and the surface of the island region 5 surrounding the base region 7 and the injector region 6. Through this diffusion process, collector regions 8 and 9 are formed in the base region 7, and an N + type collar region 15 surrounding the base region 7 and the injector region 6 is formed on the surface of the island region 5. And this color area 15 is
The base area 7 is formed so as to be in contact with the embedded color area 20 and is surrounded by the color area 15. The area around the base area 7 is surrounded by the embedded color area 20.
and is surrounded by a high density area called a color area 15. Further, a color area 1 is provided on the surface of the island area 5 between the injector area 6 and the base area 7.
5 is not formed by diffusion (FIG. 1).
次いて、周知のアルミニウム蒸着技術等によ
り、電極１０…１４を設けて第１図トに示すIIL
が製造される。 Next, electrodes 10...14 are provided by well-known aluminum vapor deposition technology, etc., and the IIL shown in FIG.
is manufactured.
このようにして製造されたIILは第１図トに示
すように、半導体基板１と基板１上にエピタキシ
ヤル成長されたN-型のエピタキシヤル層３との
間にN+型の埋め込み層２が設けられると共に、
この埋め込み層２とエピタキシヤル層３との間に
ベース領域７を取り囲むN+型の埋め込みカラー
領域２０が埋め込み層２からはい上らせて設けら
れている。エピタキシヤル層３はP+型の分離領
域４で島状に分離され島領域５が形成されてい
る。島領域５表面に、Ｐ型のインジエクタ領域６
とベース領域７が形成され、ベース領域７表面に
N+型のコレクタ領域８，９が形成される。また
島領域５表面にインジエクタ領域６およびベース
領域７を取り囲むN+型のカラー領域１５が形成
されている。３ａはエピタキシヤル層３表面に設
けられた酸化膜である。インジエクタ領域６には
インジエクタ電極１０、ベース領域７にはベース
電極１１、コレクタ領域８，９にはコレクタ電極
１２，１３が設けられていると共に、逆方向縦形
NPNトランジスタのエミツタ電極１４はカラー
領域１５にオーミツクコンタクトすることにより
電極の取り出しが行なわれる。 As shown in FIG . is established, and
An N + type buried collar region 20 surrounding the base region 7 is provided between the buried layer 2 and the epitaxial layer 3 and extends from the buried layer 2 . The epitaxial layer 3 is separated into islands by P + type isolation regions 4 to form island regions 5 . A P-type injector region 6 is provided on the surface of the island region 5.
and base region 7 is formed, and on the surface of base region 7
N + type collector regions 8 and 9 are formed. Further, an N + type collar region 15 surrounding the injector region 6 and base region 7 is formed on the surface of the island region 5 . 3a is an oxide film provided on the surface of the epitaxial layer 3. An injector electrode 10 is provided in the injector region 6, a base electrode 11 is provided in the base region 7, and collector electrodes 12 and 13 are provided in the collector regions 8 and 9.
The emitter electrode 14 of the NPN transistor is brought into ohmic contact with the collar region 15 to take out the electrode.
このように本発明による製造方法によれば、イ
ンジエクタ領域６とベース領域７との間を除いて
ベース領域７の側面は埋め込みカラー領域２０と
カラー領域１５とで取り囲み、そしてベース領域
７とインジエクタ領域６との間は埋め込みカラー
領域２０がベース領域７に隣接して設けてベース
領域７を取り囲むことができる。従つて、ラテラ
ルPNPトランジスタQIの注入効率を低下させず
に、サイドウオールでのホールの逆注入を埋め込
みカラー領域２０とカラー領域１５とで抑制で
き、逆方向電流増幅率βiを高くでき、IILの高速
動作が可能となる。 As described above, according to the manufacturing method according to the present invention, the side surface of the base region 7 except for the area between the injector region 6 and the base region 7 is surrounded by the embedded collar region 20 and the collar region 15, and the base region 7 and the injector region 6, a buried collar region 20 may be provided adjacent to the base region 7 to surround the base region 7. Therefore, the reverse injection of holes in the sidewall can be suppressed by the buried collar region 20 and the collar region 15 without reducing the injection efficiency of the lateral PNP transistor QI , and the reverse current amplification factor βi can be increased, and IIL enables high-speed operation.
また、カラー領域１５はコレクタ領域８，９の
形成と同時に形成するため、カラー領域１５の横
方向拡散量も小さくすむため集精度を上げること
ができる。 Further, since the color region 15 is formed at the same time as the collector regions 8 and 9, the amount of lateral diffusion of the color region 15 can also be reduced, and collection accuracy can be improved.
更に、インジエクタ領域６を取り囲むカラー領
域１５による濃度差により立上り電圧が良くな
り、インジエクタ領域６からベース領域７への注
入効率が上る。 Furthermore, the rise voltage is improved due to the concentration difference due to the collar region 15 surrounding the injector region 6, and the injection efficiency from the injector region 6 to the base region 7 is increased.
(ト) 発明の効果
以上説明したように本発明によれば、ラテラル
PNPトランジスタの動作に影響を与えずにサイ
ドウオールからのホールの逆注入を大幅に抑制し
て、逆方向電流増幅率βiを高くした高速動作の可
能なIILを製造することができる。(g) Effects of the invention As explained above, according to the present invention, the lateral
It is possible to significantly suppress the reverse injection of holes from the sidewall without affecting the operation of the PNP transistor, and to manufacture an IIL capable of high-speed operation with a high reverse current amplification factor βi.
第１図イ乃至第１図トは本発明による製造方法
の各プロセスにおける工程断面図である。第２図
はIILの回路図、第３図は従来のIIL構造を示す断
面図である。
１……半導体基板、２……埋め込み層、３……
エピタキシヤル層、５……島領域、６……インジ
エクタ領域、７……ベース領域、８，９……コレ
クタ領域、１５……カラー領域、２０……埋め込
みカラー領域、２１……不純物堆積層、２２……
第２堆積層。
FIGS. 1A to 1G are cross-sectional views of each process of the manufacturing method according to the present invention. FIG. 2 is a circuit diagram of an IIL, and FIG. 3 is a sectional view showing a conventional IIL structure. 1... Semiconductor substrate, 2... Buried layer, 3...
epitaxial layer, 5... island region, 6... injector region, 7... base region, 8, 9... collector region, 15... collar region, 20... buried collar region, 21... impurity deposition layer, 22...
Second sedimentary layer.
Claims (1)
み層となる不純物堆積層を形成する工程と、前記
堆積層の不純物の拡散速度より拡散速度の速い逆
導電型の不純物を前記堆積層の所望位置に注入し
てベース領域を取り囲む埋め込みカラー領域とな
る第２堆積層を形成する工程と、前記基板上に逆
導電型のエピタキシヤル層を形成する工程と、前
記埋め込み層上のエピタキシヤル層表面の所望箇
所に一導電型の不純物を拡散して、インジエクタ
領域と埋め込みカラー領域に取り囲まれたベース
領域とを形成する工程と、逆導電型の不純物を前
記ベース領域表面およびエピタキシヤル層表面に
拡散することにより、前記ベース領域にコレクタ
領域を形成すると共に、前記エピタキシヤル層表
面に前記インジエクタ領域およびベース領域を取
り囲むカラー領域を形成する工程と、からなる半
導体注入集積論理回路装置の製造方法。1. A step of forming an impurity deposited layer to be a buried layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and adding an impurity of the opposite conductivity type, which has a diffusion rate faster than the diffusion rate of the impurity of the deposited layer, to a desired amount of the deposited layer. forming a second deposited layer to form a buried collar region surrounding the base region; forming an epitaxial layer of opposite conductivity type on the substrate; and forming a surface of the epitaxial layer on the buried layer. a step of diffusing impurities of one conductivity type to a desired location of the base region to form an injector region and a base region surrounded by a buried collar region; and diffusing impurities of the opposite conductivity type to the surface of the base region and the surface of the epitaxial layer. A method for manufacturing a semiconductor implanted integrated logic circuit device, comprising the steps of: forming a collector region in the base region, and forming a collar region surrounding the injector region and the base region on the surface of the epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16255184A JPS6142166A (en) | 1984-08-01 | 1984-08-01 | Manufacture of semiconductor injection integrated logic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16255184A JPS6142166A (en) | 1984-08-01 | 1984-08-01 | Manufacture of semiconductor injection integrated logic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6142166A JPS6142166A (en) | 1986-02-28 |
| JPH0439789B2 true JPH0439789B2 (en) | 1992-06-30 |
Family
ID=15756738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16255184A Granted JPS6142166A (en) | 1984-08-01 | 1984-08-01 | Manufacture of semiconductor injection integrated logic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142166A (en) |
-
1984
- 1984-08-01 JP JP16255184A patent/JPS6142166A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6142166A (en) | 1986-02-28 |
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