JPS63119536A - Manufacture of mesa type semiconductor device - Google Patents
Manufacture of mesa type semiconductor deviceInfo
- Publication number
- JPS63119536A JPS63119536A JP26585286A JP26585286A JPS63119536A JP S63119536 A JPS63119536 A JP S63119536A JP 26585286 A JP26585286 A JP 26585286A JP 26585286 A JP26585286 A JP 26585286A JP S63119536 A JPS63119536 A JP S63119536A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- mesa
- semiconductor device
- forming
- scribing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000011521 glass Substances 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 230000001681 protective effect Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 241000270281 Coluber constrictor Species 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- OQZCSNDVOWYALR-UHFFFAOYSA-N flurochloridone Chemical compound FC(F)(F)C1=CC=CC(N2C(C(Cl)C(CCl)C2)=O)=C1 OQZCSNDVOWYALR-UHFFFAOYSA-N 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、メサ溝部にガラス保護膜を有する半導体装置
の製造に関し、特にガラス保護膜の形成力法の改良によ
りレーザースクライプ工程を省略あるいは容易に行なう
ことに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the production of semiconductor devices having a glass protective film in a mesa groove, and in particular to omitting or eliminating the laser scribing process by improving the method for forming the glass protective film. It is about things that are easy to do.
従来この種の半導体装置は一般に一枚の半導体クエハー
に拡散等によって多数の半導体素子を形成し、各半導体
素子間にメサ溝を形成し、メサ溝部Kjll出するPN
接合部を、ガラス絶縁体で被覆保護したのち前記絶縁体
の中央部からレーザー光線によってスクライプし、さら
にブレーキングして半導体装置が製造されていた。Conventionally, in this type of semiconductor device, a large number of semiconductor elements are generally formed on a single semiconductor wafer by diffusion or the like, and a mesa groove is formed between each semiconductor element, and a PN is formed in the mesa groove part Kjll.
Semiconductor devices have been manufactured by covering and protecting the bonded portion with a glass insulator, scribing the insulator from the center with a laser beam, and further braking.
上述した従来の半導体装置はガラス保護膜によってメサ
溝に露出するPN接合を保護する役割を備なえる。その
ためKはガラス保護膜の厚さを十分厚くする心安がある
。しかしながら、ガラス保護膜が厚いと、レーザー光線
によるスクライプが困難になるため、その対策として、
レーザーパワーを最大限上げてスクライプするか、又は
、レーザースピードを遅くしてスクライプする方法がと
られている。しかしながらレーザーパワーを上げてスク
ライプすると半導体装置の初期耐圧特性が、大幅に劣化
する危険性があり、又、レーザースピードを遅くしてス
クライプすると作業能率が極端に低下するという欠点が
ある。The conventional semiconductor device described above has a glass protective film that protects the PN junction exposed in the mesa groove. Therefore, it is safe for K to make the glass protective film sufficiently thick. However, if the glass protective film is thick, it becomes difficult to scribe with a laser beam, so as a countermeasure,
The methods used are to increase the laser power to the maximum and scribe, or to slow down the laser speed and scribe. However, when scribing with a high laser power, there is a risk that the initial breakdown voltage characteristics of the semiconductor device will be significantly deteriorated, and when scribing with a low laser speed, the working efficiency is extremely reduced.
〔問題点を解決するための手段j
本発明によれば、メサ溝形成後に、メサ溝中央部に細溝
を有し、ホトレジスト膜忙て前記細溝を保護したのち従
来通りガラス保護膜を形成すること罠より、レーザー光
線によるスクライプ工程を省略あるいは容易にした半導
体装置を得る。[Means for Solving the Problems J] According to the present invention, after forming a mesa groove, a narrow groove is formed at the center of the mesa groove, and after the narrow groove is protected by a photoresist film, a glass protective film is formed as before. To obtain a semiconductor device in which a scribing process using a laser beam is omitted or simplified.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(N〜(口は、本発明の一実施例の縦断面図であ
る。図においては、半導体ウェハーで1は、N型基板で
2は、ゲート、3はカソードで4はアノード、5はPN
接合、6はメサ溝、7は細溝、8は、ホトレジスト膜、
9は、ガラス保護膜である。まず従来と同様にしてN型
基板1に、ゲート2、カソード3、アノード4を有する
多数の半導体素子を有する半導体ウェハーを用意する(
第1図四)。次に常法処したがって、メサエッチングを
行なってメサ溝6.6′を形成する(第1図(B))。FIG. 1 (N~) is a vertical cross-sectional view of one embodiment of the present invention. In the figure, 1 is a semiconductor wafer, 2 is an N-type substrate, 2 is a gate, 3 is a cathode, 4 is an anode, 5 is PN
junction, 6 is a mesa groove, 7 is a narrow groove, 8 is a photoresist film,
9 is a glass protective film. First, a semiconductor wafer having a large number of semiconductor elements having a gate 2, a cathode 3, and an anode 4 is prepared on an N-type substrate 1 in the same manner as in the conventional method (
Figure 1 4). Next, mesa etching is performed using a conventional method to form mesa grooves 6 and 6' (FIG. 1(B)).
こののちメサ溝6の底部中央に、レーザー又は、ダイ7
ングにより細ts7.7’を形成する。次いで細溝部7
.7′にホトレジストあるいは、絶縁ワックス等をスク
リーン印刷により被着せしめ保護したのち常法にしたが
って電気泳動法によりガラス保護膜9,9′を形成する
(第1図IQ)。その後、ガラス保役膜を加熱溶融する
。その際ホトレジスト又は絶縁ワックス等は、焼き飛ば
されガラス保護膜のないMB@7.7’が露出された半
導体素子Bを形成する(第1図(ロ)。After this, a laser or die 7 is placed at the center of the bottom of the mesa groove 6.
A narrow ts7.7' is formed by Next, the narrow groove part 7
.. After coating 7' with photoresist or insulating wax by screen printing to protect it, glass protective films 9 and 9' are formed by electrophoresis according to a conventional method (FIG. 1IQ). Thereafter, the glass retention film is heated and melted. At this time, the photoresist or insulating wax is burned off to form a semiconductor element B in which the MB@7.7' without the glass protective film is exposed (FIG. 1(b)).
〔発明の幼果)
以上説明したように本発明は、メサエッチ後にメサ溝中
央部にすでにプレー平ング用のlK11#を形成しホト
レジストあるいはワックス等によシ細溝を保護したのち
メサ溝部にガラス保護膜を形成するため通常のレーザー
光線照射によるスクライプ工程を省略あるいは容易にし
たのち、ブレーキングを行なプことができる。したがっ
て本発明を適用することKよシ従来より問題となってい
るレーサースクライプによる耐圧劣化、スクライブ位置
ズレによる外観不良及び特性不良又は、作業能率低下と
いう問題が、解決され、物性変動のない良好で高歩留な
半導体装置が得られるという効果がある。[Young fruit of the invention] As explained above, in the present invention, after mesa etching, lK11# for play flattening is already formed in the center of the mesa groove, the thin groove is protected by photoresist or wax, and then glass is applied to the mesa groove. In order to form a protective film, the usual scribing process using laser beam irradiation can be omitted or facilitated, and then breaking can be performed. Therefore, by applying the present invention, the conventional problems of pressure deterioration due to racer scribe, poor appearance and characteristics due to misalignment of the scribe, and decreased work efficiency can be solved, and the problem is good with no change in physical properties. This has the effect that high-yield semiconductor devices can be obtained.
第1図(A)〜(鴎は本発明方法を説明する各工程にお
ける縦断面図である。
A・・・・・・半導体ウェハー、B・・・・・・半導体
素子、1・・・・・・N型基板、2・・・・・ゲート、
3・・・・・・カソード、4・・・・・・アノード、5
・・・・・・PN接合、6・・・・・・メサ溝、7・・
・・・・細溝、8・・・・・・ホトレジスト膜、9・・
・・・ガラス保護膜、10・・・・・酸化膜。
(C)FIG. 1 (A) - (The seagulls are longitudinal cross-sectional views at each step to explain the method of the present invention. A... Semiconductor wafer, B... Semiconductor element, 1... ...N-type substrate, 2...gate,
3...Cathode, 4...Anode, 5
...PN junction, 6...Mesa groove, 7...
... Thin groove, 8... Photoresist film, 9...
...Glass protective film, 10...Oxide film. (C)
Claims (1)
素子間にメサ溝を形成してガラス保護膜を形成するもの
において、前記メサ溝形成後にメサ溝中央に細溝を形成
し、前記細溝内にホトレジスト膜を付着せしめしかるの
ちにガラス保護膜を形成することを特徴とする半導体装
置の製造方法。In a device in which a glass protective film is formed by forming a mesa groove between each semiconductor element after forming a large number of semiconductor elements on a semiconductor wafer, a narrow groove is formed in the center of the mesa groove after the mesa groove is formed, and a thin groove is formed in the narrow groove. 1. A method of manufacturing a semiconductor device, which comprises: attaching a photoresist film to the substrate, and then forming a glass protective film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26585286A JPS63119536A (en) | 1986-11-07 | 1986-11-07 | Manufacture of mesa type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26585286A JPS63119536A (en) | 1986-11-07 | 1986-11-07 | Manufacture of mesa type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63119536A true JPS63119536A (en) | 1988-05-24 |
Family
ID=17422969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26585286A Pending JPS63119536A (en) | 1986-11-07 | 1986-11-07 | Manufacture of mesa type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63119536A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5691248A (en) * | 1995-07-26 | 1997-11-25 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
-
1986
- 1986-11-07 JP JP26585286A patent/JPS63119536A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5691248A (en) * | 1995-07-26 | 1997-11-25 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
US5925924A (en) * | 1995-07-26 | 1999-07-20 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
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