Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W95/00—Packaging processes not covered by the other groups of this subclass
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
  • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/019—Manufacture or treatment of bond pads
  • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
  • H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
  • H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
  • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/321—Structures or relative sizes of die-attach connectors
  • H10W72/325—Die-attach connectors having a filler embedded in a matrix
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
  • H10W72/347—Dispositions of multiple die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/351—Materials of die-attach connectors
  • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/59—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/921—Structures or relative sizes of bond pads
  • H10W72/926—Multiple bond pads having different sizes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/941—Dispositions of bond pads
  • H10W72/9413—Dispositions of bond pads on encapsulations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/941—Dispositions of bond pads
  • H10W72/944—Dispositions of multiple bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
  • H10W76/10—Containers or parts thereof
  • H10W76/12—Containers or parts thereof characterised by their shape
  • H10W76/13—Containers comprising a conductive base serving as an interconnection
  • H10W76/138—Containers comprising a conductive base serving as an interconnection having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• Embodiments of the invention relate to a system in package (SIP) comprising a laminate body having a substrate and a semiconductor die arranged in the laminate body. Further, other embodiments relate to a method for manufacturing the system in package.
• SIP system in package
• system in package One approach to fulfill the increasing customer demands is a so called "system in package” which was developed to address the growing challenges faced in many applications such as computing and telecommunication.
• a system in package for example the MicroSIP (pSIP) package from Texas Instruments
• Incorporated (Dallas, Texas, USA) incorporates a semiconductor die, a controller, as examples in a laminate substrate. Furthermore, active and/or passive electronic components, such as inductor(s), are incorporated in the system in package by placing them on top of an upper surface of a laminate substrate or body.
• a system in package comprising a laminate body comprising a substrate which is arranged inside the laminate body.
• the substrate is pre-pressed.
• a semiconductor die is embedded in the laminate body and at least one contact area of the semiconductor die is bonded to a contact pad of the substrate by help of a sintered bonding layer which is made from a sinter paste.
• the system in package according to aspects of the invention may be manufactured in a combined pressing and sintering process.
• a pressing step is typically known from the manufacture of printed circuit boards and is typically carried out at process temperatures in a range around 200°C.
• the process parameters of such a pressing step are suitable for performing a sintering process, too.
• a combined pressing and sintering step is provided. Sintering of the sinter paste takes place and the sintered bonding layer is provided within the same process step which is applied for lamination of the stack.
• a method for manufacturing a system in package is provided.
• a sinter paste is applied to contact pads of a substrate and/or to contact areas of a semiconductor die.
• the application of the sinter paste is performed by paste printing and sinter paste is applied to either the contact areas of a semiconductor die or the contact pads of a substrate.
• the contact areas of the semiconductor die are placed on the contact pads of the substrate. In other words, the contact areas of the semiconductor die and the contact pads of the substrate are brought in register with each other.
• the substrate together with the placed semiconductor die and further layers forming a laminate body of the system in package are stacked. Finally, a combined pressing and sintering step is performed on the stack.
• the substrate and the further layers of the stack are laminated so as to provide the laminate body. Further, during the combined pressing and sintering step, sintering of the sinter paste is performed so as to provide an electrical connection between the contact pads of the substrate and the contact areas of the semiconductor die. In other words, lamination of the stack and electrical contacting is performed in a common and single process step.
• said stack may be exposed to heat and pressure as it is typically known for the manufacture of printed circuit boards.
• the method may comprise a step of pre-pressing the substrate and the semiconductor die will be arranged on this pre-pressed substrate before pressing and sintering the stack. Further, a partial pre-sintering of the sinter paste may be performed before the final pressing and sintering step.
• FIG.1 is illustrative of a simplified stack for manufacturing a system in package, the stack is shown after placement of semiconductor dies and before sintering and pressing the stack-up,
• FIG. 2 is illustrative of the stack of FIG. 1 , wherein a filling material is inserted between subsequent substrates,
• FIG. 3 is illustrative of a simplified system in package which is
• FIG. 4 is illustrative of the simplified system in package of FIG. 3, wherein vias are inserted so as to provide a connection between an upper, middle and lower interconnection surface of the system in package,
• FIG. 5 is illustrative of a further simplified system in package having no lower substrate
• FIG. 6 is illustrative of another simplified system in package having no substrate adjacent to an upper and lower surface
• FIG. 7 is illustrative of a further simplified system in package comprising two power FETs placed side by side and a controller stacked on top of the FETs,
• FIG. 8 is illustrative of another simplified system in package comprising two power FETs arranged side by side and a passive component placed upon an upper surface
• FIG. 9 is illustrative of a simplified system in package comprising two power FETs arranged side by side and a passive component, wherein the dies are directly stacked in a die-on-die configuration
• FIGS. 10 and 1 1 are illustrative of further simplified systems in package comprising a semiconductor die and a metal block providing a high current connection.
• FIG. 1 is illustrative of a simplified stack for manufacturing a system in package.
• the stack is shown after placement of semiconductor dies 2 onto respective substrates 4 and before sintering and pressing the stack.
• the substrates 4 are pre-pressed and further preferably, they are made from a printed circuit board material such as a fiber reinforced resin.
• Contact pads 6 of the substrates 4 are preferably made from copper and have a plating 7 which is made from a noble metal.
• the material of the plating 7 is preferably more noble than copper when considered in a galvanic series.
• NiAu or NiAg is applied for the plating 7.
• a NiAu plating 7 prevents the Cu contact pads 6 from oxidation during the sinter process.
• each contact area or contact pad 6 which is designated to be coupled or contacted by help of a sintered connection is provided with a noble metal plating 7 to prevent oxidation of the sintered electrical contact.
• Electrically conductive vias 8 project through the substrate 4.
• the vias 8 are for electrically coupling a respective contact pad 6 which is arranged on a first surface of the substrate 4 with a further contact pad 6 which is arranged on an opposite surface of the substrate 4.
• the electrically conductive vias 8 are copper filled drilling holes.
• the vias 8 electrically couple a contact pad 6 which is arranged at an inner surface of the substrate 4 with an upper contact pad 10 which is arranged at an upper surface 28.
• the vias 8 are for coupling the contact pad 6 which is arranged at an inner surface with a lower contact pad 12 which is arranged at a lower surface 26 of the stack. Further active and/or passive components may be arranged at the upper surface 28 and may be coupled to the upper contact pads 12.
• the lower surface 26 of the stack typically faces a printed circuit board if the system in package is mounted thereto. An electric coupling of the system in package to the printed circuit board may be provided via the lower contact pads 12.
• the contact pads 6 of the substrates 4, more precisely the plating 7 of the lower contact pads 6 of the upper and middle substrate 4 are provided with sinter paste 14 which is preferably applied by sinter paste printing.
• the sinter paste 14 is made from a metal or a metal alloy which is more noble than Cu. Again, this is considered in a galvanic series and a preferable material is a Ag-based sinter paste 14.
• the sinter paste 14 is applied to either one or both of the contact areas of the semiconductor dies 2 and the contact pads 6 of the substrates 4.
• sinter paste 14 is printed to the contact pads 6 of the substrates 4.
• the semiconductor dies 2 are placed on top of the sinter paste 14 on the respective contact pads 6 of the substrates 4 which means that the contact areas of the semiconductor dies 2 are brought in register with the contact pads 6 of the substrates 4.
• a backside of the semiconductor dies 2 has been provided with sinter paste and a pre-sintering step has been performed so as to attach the backside of the semiconductor dies 2 to the substrates 4.
• the sinter paste becomes a sintered bonding layer 16 which is arranged between the backside of the dies 2 and the upper contact pads 6 of the substrates 4.
• the semiconductor dies 2 are power MOSFETs and the depicted stack-up is for providing a stacked power-FET configuration.
• FIG. 2 is illustrative of the stack-up known from FIG. 1 , wherein a filling material 18 is inserted between adjacent substrate layers 4.
• the filling material 18 is added to the stack during the stack-up step and preferably, the filling material 18 is pre-cut to accommodate the semiconductor dies 2.
• the filling material 18 may further accommodate additional active and/or passive components (not shown) which may be integrated in the system in package.
• the filling material 18 is for filling voids in the stack-up during the subsequent pressing and sintering step.
• the stack-up of FIG. 2 is exposed to heat and pressure, wherein parameters for performing this step may be in a range for temperature and pressure which is typically known from the
• the system in package may be manufactured in a combined process step which means lamination and sintering is performed in a single and common process step. This simplifies the manufacturing process of the system in package. It is further advantageous that the semiconductor dies 2 are bonded directly to a respective conductive path or contact pad 6 of the substrate 4. There is no need for a lead frame. The abandonment of the lead frame and the required bond wire bonding process between the semiconductor die 2 and the lead frame is advantageous with respect to manufacturing cost and will further speed up the manufacturing process.
• FIG. 3 is illustrative of a simplified system in package 20 comprising a laminate body which is substantially manufactured from the substrates 4, cured filling material 22 and the embedded semiconductor dies 2.
• the sinter paste pads 16 which have been previously applied or printed on the lower contact pads 6 of the upper and center substrate 4 become a sintered bonding layer 16.
• the contact areas of the semiconductor dies 2 are coupled to the contact pads 6 of the substrate 4 by help of the sintered bonding layer 16.
• the semiconductor dies 2 are coupled to the upper contact pads 10 and to the lower contact pads 12 via electrically conductive vias 8.
• Further active and/or passive electronic components may be embedded on and coupled to the upper contact pads 10.
• these further active and/or passive electronic components may be an inductor or a capacitor so as to provide a highly integrated power converter having a small form factor and a small footprint.
• the lower contact pads 12 of the system in package 2 may be coupled to a printed circuit board of an electronic device by application of an arbitrary
• FIG. 4 is illustrative of the system in package 20 of FIG. 3, however, vertical connections 24 which may be copper filled vias, are inserted in the system in package 20 according to the embodiment of FIG. 4.
• the vertical connections 24 are for coupling the upper contact pads 10 of the system in package 20 with the lower contact pads 12 and contacts pads 12 of the middle substrate 4 if required.
• the system in package 20 may comprise further electronic components (not shown) which are embedded in the laminate body.
• a controller may be integrated in the system in package 20 and may be applied for controlling the power MOSFETs (i. e. the semiconductor dies 2) so as to provide a highly integrated power stage.
• these further active and/or passive electronic components may be coupled to the respective upper and/or lower contact pads 10, 12 of the system in package 20 by help of the vertical connections 24.
• the further electronic components for example a controller chip or a small capacitor are embedded in the second layer of the system in package 20. Consequently, on-space on the upper side 28 may be leveraged for larger electronic parts or components which are required for the module.
• contact areas of a same semiconductor die 2 may be coupled via the substrates 4.
• a first contact area of a semiconductor die 2 may be coupled to a contact pad 6 of a substrate 4 and a further contact pad 6 of said substrate 4 is coupled to a further contact area of said semiconductor die 2.
• the further contact area may a contact area of a further semiconductor die 2.
• the latter embodiment allows coupling two or more semiconductor dies 2 via the substrate 4.
• the electrical connection between the respective contact areas and the contact pads 6 may be provided by a sintered bonding layer 16 which is made from sinter paste 14.
• this aspect removes the need for complex inter die wire bonding. Complex routing on a PCB to which the respective system in package is assembled may be simplified.
• FIG. 5 is illustrative of another simplified system in package 20 according to an embodiment of the invention, wherein there is no substrate 4 adjacent to the lower surface 26. Accordingly, especially for the lower semiconductor die 2, there is very efficient heat transfer to a printed circuit board which may be arranged adjacent to the lower surface 26 of the system in package 20.
• the configuration of the system in package 20 in FIG. 5 is known from FIG. 4 despite of the fact there is no substrate 4 adjacent to the lower surface 26. Therefore, the configuration of the system in package 20 of FIG. 5 will not be explained repeatedly.
• FIG. 6 is illustrative of a further simplified system in package 20 according to another embodiment of the invention.
• the system in package 20 according to the embodiment in FIG. 6 comprises a single substrate 4 in the center of the system in package 20 only. There is very efficient heat dissipation for the upper and lower semiconductor die 2.
• the configuration of the system in package 20 according to the embodiment in FIG. 6 is in principle known from FIG.
• FIG. 7 is illustrative of a simplified system in package 20 according to another embodiment of the invention.
• the system in package 20 comprises a substrate layer 4 which is arranged in the center of the system in package 20 and which is adjacent to cured filling material 22 embedding a first and a second semiconductor die 2 which are arranged side by side in a lower layer. Further, a controller 30 is arranged in an upper layer of the system in package 20.
• the semiconductor dies 2 are bonded to the lower contact pads 12 which are embedded in a lower surface 26 of the system in package 20 and to contact pads 6 of the substrate 4 by help of sintered bonding layers 16. Something similar applies to the controller 30 which is bonded to the substrate layer 4 by help of a sintered bonding layer 16. However, standard die attaching methods may be applied for bonding the controller 30, too. As already mentioned with respect to the embodiments in FIG. 1 to 6, the system in package 20 according to the embodiment in FIG.
• the controller 30 may be stacked up and lamination of the laminate body (mainly comprising the substrate 4 and the filling material, shown as cured filling material 22) and sintering of sinter paste pads so as to provide a bonding of the semiconductor dies 2 and the controller 30 is performed in a single and combined process step.
• Further contacts 32 for coupling the controller 30 may be inserted in the upper surface 28 of the system in package 20 using conventional technology.
• Coupling of the controller 30 to lower contact pads 12 may be provided by vertical connections 24 which may be copper filled vias and which are for coupling an upper side of the controller 30 with lower contact pads 12.
• An additional layer on top of the upper surface 28 can provide space and interconnections for topside arranged external components.
• FIG. 8 is illustrative of a simplified system in package 20 which is configured similar to the system in package 20 according to FIG. 7. However, there is no substrate 4 arranged in the center of the stack. The substrate 4 is arranged adjacent to an upper surface 28 of the system in package 20. The controller 30 is coupled to contact pads 6 of the substrate 4 using conventional technology.
• Coupling of the contact pads 6 of the substrate 4 to lower contact pads 12 may be provided by vertical connections 24 which may be copper filled vias.
• the semiconductor dies 2 are coupled to lower contact pads 12 by help of sintered bonding layers 16 as it is known from FIG. 7.
• the semiconductor dies 2 and the controller 30 are arranged in a die-on-die configuration which means that the dies 2 and the controller die 30 are directly stacked upon each other without a substrate in-between. Bonding of the dies 2, 30 is performed by help of a sintered bonding layer 16.
• a backside of the controller die 30, which is plated with a noble metal plating 7, is adjacent to the sintered bonding layer 16 which is further adjacent to the noble metal plating 7 of the semiconductor dies 2.
• FIG. 9 is illustrative of another simplified system in package 20
• the system in package 20 comprises a substrate 4 which is adjacent to an upper surface 28 of the system in package 20.
• the substrate 4 comprises contact pads 6 which are coupled to contact areas of the semiconductor dies 2 by help of sintered bonding layers 16.
• the backside of the semiconductor dies 2 is coupled to lower contact pads 12 by help of sintered bonding layers 16.
• very efficient heat dissipation from the semiconductor dies 2 to a printed circuit board which may be adjacent to the lower surface 26 of the system in package 20 may be provided.
• Contact areas of the semiconductor dies 2 which are arranged at an upper an active side of the semiconductor dies 2 may be further coupled to lower contact pads 12 by help of vertical connections 24 which extend though the laminate body down to the contact pads 6 of the substrate layer 4.
• An external heat sink (not shown) or a further active and/or passive element 34 may be attached to the upper surface 28.
• the further element 34 is coupled to the lower contacts 12 by help of the vertical connections 24, by way of an example only.
• FIG. 10 is illustrative of a simplified system in package 20 comprising two semiconductor dies 2 which may be power MOSFETs of a semiconductor half bridge configuration. Further, the system in package 20 according to the embodiment in FIG. 10 comprises a metal block 36 which serves as a high current conductive path. Further active and/or passive electronic components (not shown) may be integrated in the system in package 20.
• the semiconductor dies 2 are coupled to contact pads 6 of the substrate 4 and to a lower contact 12 by help of sintered bonding layers 16 which are adjacent to the respective plating 7 of the contacts 6, 12.
• the metal block 36 is provided with a plating 7 at an upper and lower surface, too.
• a Cu- block is used as a metal block 36.
• the metal block 36 serves as a high current connection, providing a conductive path from the upper side of the semiconductor die 2 via the contact pad 6 and the metal block 36 to a circuit board which may be arranged adjacent to a lower surface of the system in package 20.
• Integration of the metal block 36 is in general comparable to integration of a semiconductor die 2.
• each semiconductor die 2 in the above referenced embodiments may be replaced by a suitably plated metal block 26 if necessary or desired. Integration and placement of a metal block 36 in the system in package 2 may be driven by a need for a high current connection.
• FIG. 1 1 is illustrative of another simplified system in package 20 which is comparable to the system in package 20 according to FIG. 10.
• FIG. 1 1 the system in package in FIG. 1 1 may be configured similar to the embodiment in FIG. 10, which means that the system in package may comprise two semiconductor dies 2 arranged in a half-bridge configuration.
• a vertical connection 24 at the left side in FIG. 1 1 is provided by a filled via.
• a vertical connection may be provided by a metal ball 36, which is depicted on the right side of the system in package 20.
• the metal ball 36 comprises a noble metal plating 7 and is sintered via sintered bonding layers 16 to a contact pad 6 on the one hand and to a lower contact pad 12 on the other hand.
• Embedding the metal ball 36 may be similar to integration of the metal block 36 which is shown in the center of the system in package 20.

Landscapes

• Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Die Bonding (AREA)
• Combinations Of Printed Boards (AREA)

Priority Applications (2)

Applications Claiming Priority (4)

Publications (1)

Family

ID=49001956

Family Applications (1)

Country Status (4)

Cited By (3)

Families Citing this family (33)

Citations (5)

Family Cites Families (12)

• 2013
  • 2013-02-19 US US13/770,237 patent/US8884343B2/en active Active
  • 2013-02-25 WO PCT/US2013/027656 patent/WO2013126893A1/en not_active Ceased
  • 2013-02-25 JP JP2014558928A patent/JP6384868B2/ja active Active
  • 2013-02-25 CN CN201380010431.XA patent/CN104170082B/zh active Active
• 2018
  • 2018-07-20 JP JP2018136615A patent/JP6615284B2/ja active Active
• 2019
  • 2019-10-10 JP JP2019186475A patent/JP7132467B2/ja active Active

Patent Citations (5)

Also Published As

Similar Documents

Legal Events