CN111668196A - 半导体封装件以及相关方法 - Google Patents

半导体封装件以及相关方法 Download PDF

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Publication number
CN111668196A
CN111668196A CN202010106173.7A CN202010106173A CN111668196A CN 111668196 A CN111668196 A CN 111668196A CN 202010106173 A CN202010106173 A CN 202010106173A CN 111668196 A CN111668196 A CN 111668196A
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dies
substrate
spacers
coupled
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CN202010106173.7A
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Inventor
周志雄
E·N·托伦蒂诺
V·J·H·吴
S·克里南
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Publication of CN111668196A publication Critical patent/CN111668196A/zh
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Abstract

本发明题为“半导体封装件以及相关方法”。半导体封装件的具体实施可包括耦接在衬底之上的一个或多个管芯，耦接在衬底之上的导电间隔件，以及耦接在一个或多个管芯和导电间隔件之上并且耦接到该一个或多个管芯和导电间隔件的夹具。夹具可将一个或多个管芯与导电间隔件电耦接。

Description

半导体封装件以及相关方法
相关专利申请的交叉引用
本文件要求授予Chee Hiong Chew的名称为“Semiconductor Package andRelated Methods”(半导体封装件以及相关方法)的美国临时专利申请62/814,366的提交日期的权益，该申请提交于2019/3/6，该申请的公开内容据此全文以引用方式并入本文。
技术领域
本文件的各方面整体涉及包括功率半导体器件的半导体器件。特定的具体实施还包括功率半导体器件，该功率半导体器件包括不是引线键合的电连接件。
背景技术
半导体封装件可包括耦接到芯片的半导体衬底。互连半导体封装件的部件的方法可包括形成引线键合。引线键合可通过楔形键合或球形键合来形成。
发明内容
半导体封装件的具体实施可包括耦接在衬底之上的一个或多个管芯，耦接在衬底之上的导电间隔件，以及耦接在一个或多个管芯和导电间隔件之上并且耦接到其的夹具。夹具可将一个或多个管芯与导电间隔件电耦接。
半导体封装件的实施方式可包括以下各项中的一项、全部或任一项：
夹具可包括具有第一厚度的第一部分和具有第二厚度的第二部分。
导电间隔件可以是竖直连接系统。
夹具可通过焊料或粘合剂中的一者耦接到一个或多个管芯和间隔件。
一个或多个管芯可包括绝缘栅双极型晶体管(IGBT)和二极管。
导电间隔件可包含铜箔。
封装件可仅包括单个夹具。
导电间隔件可通过焊料或粘合剂中的一者直接耦接到衬底和夹具两者。
半导体封装件的具体实施可包括耦接在衬底之上的一个或多个管芯，耦接在衬底之上的导电间隔件，以及重新分布层(RDL)，该RDL包含耦接在一个或多个管芯和导电间隔件之上的氮化硼。RDL可将一个或多个管芯与导电间隔件电连接。
半导体封装件的实施方式可包括以下各项中的一项、全部或任一项：
导电间隔件可通过焊料或粘合剂中的一者直接耦接到衬底和RDL两者。
焊料或粘合剂中的一者可包含银烧结材料。
RDL可包括在一侧上的多个电迹线。
导电间隔件可包含铜箔。
衬底可包括直接接合铜(DBC)衬底。
形成半导体封装件的方法的具体实施可包括：将烧结材料施加在多个管芯的第一侧或夹具的第一侧中的一者之上；将烧结材料施加到导电间隔件的第一侧或夹具中的一者；通过烧结材料将导电间隔件和多个管芯压力烧结到夹具；以及将烧结材料施加到多个管芯的第二侧或衬底中的一者，第二侧与多个管芯的第一侧相对。该方法还可包括：将烧结材料施加到导电间隔件的第二侧或衬底中的一者，第二侧与导电间隔件的第一侧相对；以及通过烧结材料将衬底压力烧结到导电间隔件和多个管芯。
形成半导体封装件的方法的具体实施可包括以下各项中的一项、全部或任一项：
在将多个管芯和导电间隔件被压力烧结到夹具之后，将多个管芯和导电间隔件翻转，然后多个管芯和导电间隔件可随后被压力烧结到衬底。
该方法可包括蚀刻夹具。
衬底可包括直接接合铜(DBC)衬底。
在多个管芯和导电间隔件被压力烧结到衬底之后，多个管芯和导电间隔件可被压力烧结到夹具。
烧结材料可包含银烧结材料。
对于本领域的普通技术人员而言，通过说明书和附图并且通过权利要求书，上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述实施方式，在附图中类似标号表示类似元件，并且：
图1是半导体模块的透视图；
图2是半导体封装件的透视图；
图3是衬底的顶视图；
图4是耦接在图3的衬底之上的多个管芯和间隔件的顶视图；
图5是烧结工具中的多个管芯、间隔件和衬底的横截面侧视图；
图6是多个夹具的顶视图；
图7是图6的多个夹具的底视图；
图8是图6的多个夹具的顶部透视图；
图9是图6的多个夹具的底部透视图；
图10是耦接在多个管芯和多个间隔件之上的多个夹具的顶视图；
图11是烧结工具中的图10的半导体模块的横截面侧视图；
图12是半导体模块的透视图；
图13是半导体封装件的顶视图；
图14是半导体封装件的顶部透视图；
图15是半导体模块的另一个具体实施的顶视图；
图16是晶圆的顶视图；
图17是从晶圆分离的多个管芯的顶视图；
图18是由烧结材料覆盖的图17的多个管芯的顶视图；
图19是在固化过程期间的图18的多个管芯的顶视图；
图20是多个夹具的顶视图；
图21是图20的多个夹具的底视图；
图22是图20的多个夹具的底部透视图；
图23是夹具的侧视图；
图24是蚀刻夹具的侧视图；
图25是由烧结材料覆盖的多个管芯和间隔件的顶视图；
图26是耦接到蚀刻夹具的多个管芯和间隔件的侧视图；
图27是烧结工具中的图26的多个管芯和间隔件的侧视图；
图28是耦接到夹具的多个管芯和间隔件的侧视图；
图29是烧结工具中的图28的多个管芯和间隔件的侧视图；
图30是在压力烧结之后耦接到夹具的图29的多个管芯和间隔件的侧视图；
图31是在压力烧结之后耦接到夹具的图27的多个管芯和间隔件的侧视图；
图32是耦接到夹具的多个管芯和间隔件的底视图；
图33是耦接到夹具的多个管芯和间隔件的顶视图；
图34是耦接在多个管芯和间隔件之上的烧结材料的侧视图，该多个管芯和间隔件耦接到夹具；
图35是耦接在多个管芯和间隔件之上的烧结材料的侧视图，该多个管芯和间隔件耦接到蚀刻夹具；
图36是耦接在衬底之上的烧结材料的侧视图；
图37是耦接到烧结工具中的图31的多个管芯、间隔件和夹具的衬底的侧视图；
图38是耦接到烧结工具中的图30的多个管芯、间隔件和夹具的衬底的侧视图；
图39是在烧结过程之后耦接在衬底之上的夹具的顶视图；
图40是半导体模块的顶视图；
图41是半导体模块的顶部透视图；
图42是半导体封装件的顶部透视图；
图43是衬底的顶视图；
图44是耦接在图43的衬底之上的多个管芯和间隔件的顶视图；
图45是烧结工具中的多个管芯、间隔件和衬底的侧视图；
图46是重新分布层的底视图；
图47是图46的重新分布层的底部透视图；
图48是具有耦接到其的烧结材料的图46的重新分布层的底视图；
图49是耦接在多个管芯和间隔件之上的重新分布层的顶视图；
图50是烧结工具中的重新分布层、多个管芯和间隔件的侧视图；
图51是图41的半导体模块的顶部透视图；
图52是图42的半导体封装件的顶视图；以及
图53是图42的半导体封装件的顶部透视图。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的与预期半导体封装件符合的许多附加部件、组装工序和/或方法元素将显而易见地能与本公开的特定实施方式一起使用。因此，例如，尽管本发明公开了特定实施方式，但是此类实施方式和实施部件可包括符合预期操作和方法的本领域已知用于此类半导体封装件以及实施部件和方法的任何形状、尺寸、样式、类型、模型、版本、量度、浓度、材料、数量、方法元素、步骤，和/或类似的。
参见图1，示出了半导体模块的透视图。在各种具体实施中，半导体模块2可以是SSDC(单侧直接冷却)半导体模块或其他类型的半导体模块。半导体模块2可包括可用于高功率和/或高切换应用中的一个或多个变薄的管芯。半导体模块2包括衬底4。如图1所示，衬底4可为直接键合铜(DBC)衬底。虽然本文所公开的具体实施例示为包括DBC衬底，但在其他具体实施中，可使用其他衬底，包括(非限制性示例)绝缘金属衬底技术(IMST)衬底、有源金属键合(AMB)衬底、在两个金属或金属合金层之间具有绝缘层的衬底、或其它含硅和非硅衬底。
仍参见图1，半导体模块2包括耦接在衬底4之上的一个或多个管芯6。管芯6可包括各种功率器件，诸如(非限制性示例)，金属氧化物半导体场效应晶体管(MOSFET)、绝缘栅双极型晶体管(IGBT)、二极管或任何其他类型的功率半导体器件。此类器件可具有高载流能力。在其他具体实施中，半导体模块可包括不是功率器件的管芯。在特定的具体实施中，管芯6可从初始制造厚度变薄并被配置为在高功率输出条件下工作。
如图1所示，半导体模块2包括耦接在一个或多个管芯6之上的多个夹具8。在各种具体实施中，尽管未示出，但可焊接的顶部金属层可耦接在一个或多个管芯6之上。多个夹具8中的至少一个夹具也可耦接在间隔件之上，并且在各种具体实施中，多个夹具8中的每个夹具可耦接在间隔件之上。在本文所公开的具体实施中，夹具可将一个或多个管芯与间隔件电耦接。间隔件也耦接在衬底4之上。间隔件可通过焊料或其他粘合剂直接耦接到衬底和夹具两者。在特定的具体实施中，粘合剂包含烧结材料，包含银烧结材料。在各种具体实施中，并且如本文所用，间隔件为导电间隔件。在其他具体实施中，间隔件可为非导电的。间隔件中的每一个也是与管芯提供电连接或热连接或电连接和热连接两者的竖直连接系统。
图1中未示出间隔件，因为它们被夹具8覆盖。在各种具体实施中，间隔件可为金属材料或金属合金，并且可包含(非限制性示例)铜、黄铜、铝包铜或任何其它类型的金属材料或层状金属材料。在特定的具体实施中，间隔件可包含铜箔。在各种具体实施中，多个夹具8可为铜、银、钯、镍、金或任何其它金属、它们的合金或金属的组合。在特定的具体实施中，夹具的底侧面可以是裸铜、镀有银、钯、镍、金或它们的任何其它金属或其合金。在其他具体实施中，夹具8可包括非金属导电材料和/或导热材料。在包括一个或多个夹具8的具体实施中，与管芯6互连的夹具可提供半导体模块2的低导通状态电阻(RDS)。在各种具体实施中，夹具还可充分利用管芯的顶部金属化。另外，当通过使用夹具8来消除用于形成引线键合的力时，夹具8可降低对管芯6的损坏风险。夹具8可最终导致改善的功率管理、更好的热性能和更高的可靠性。虽然图1-2示出了多个夹具，在其他具体实施中，模块和/或封装件可仅包括单个夹具。
在各种具体实施中，每个夹具8可覆盖单个间隔件和两个或更多个管芯。在特定的具体实施中，单个夹具可覆盖IGBT、二极管和间隔件。在各种具体实施中，间隔件可在衬底和管芯之间提供延伸/延长的连接。间隔件可补偿管芯之间的不均匀性，因为间隔件可补偿衬底和/或管芯和/或管芯附接或夹具附接材料的各种厚度之间的差异。另外，间隔件可填充夹具8和衬底4之间的间隙并且向夹具8提供附加的结构支撑。在各种具体实施中，夹具8可包括横跨夹具的单个厚度。在其他具体实施中，夹具8可包括具有第一厚度的第一部分和具有第二厚度的第二部分。可通过蚀刻或压印夹具8来形成此类夹具8。
每个夹具8可通过导电粘合剂键合到管芯6和间隔件。在各种具体实施中，粘合剂可包括烧结材料，并且在具体实施中，可包含银烧结材料。在此类具体实施中，银烧结材料可用来使半导体模块2的热效率和电效率尽可能地最大化。虽然本文所述的具体实施主要涉及银烧结材料，但应当理解，可使用其他烧结、焊料、键合或粘合剂材料来代替银烧结材料。如图1所示，半导体模块2可包括多个引脚10。虽然本文所公开的具体实施包含银烧结材料，但应当理解，在其他具体实施中，可使用任何其它导电粘合剂/管芯附接材料。
参见图2，示出了半导体封装件的具体实施的透视图。在各种具体实施中，半导体封装件12可包括耦接到壳体16和背板18的半导体模块14中的一个或多个。半导体模块14中的每一个可与图1的半导体模块相同或相似。在图2所示的具体实施中，半导体封装件中包括三个模块。在各种具体实施中，壳体16可包括分隔半导体模块14的一个或多个支柱20。尽管未示出，但在各种具体实施中，壳体的内部可填充有覆盖半导体模块14的密封剂。密封剂可包含灌封化合物，并且在特定的具体实施中，可包含凝胶灌封化合物。半导体封装件可包括可通过封装剂暴露的引脚22。
参见图3至图14，示出了在形成图2的半导体封装件的方法的具体实施中的各个点处的半导体封装件的具体实施。具体地参见图3，示出了衬底的顶视图。该方法可包括提供本文所公开的任何类型的衬底，包括DBC衬底24。衬底24可在其上包括多种图案/迹线。参见图4，示出了耦接在图3的衬底之上的多个管芯和间隔件的顶视图。管芯26可包括本文所公开的任何类型的管芯。间隔件28可包含本文所公开的任何类型的材料，并且在具体实施中可包含金属箔，诸如铜箔，但也可使用本文所公开的任何金属材料。在各种具体实施中，该方法可包括将烧结材料施加在多个管芯的第一侧之上，以及将烧结材料施加到间隔件的第一侧。在其他具体实施中，可将烧结材料施加到衬底24。管芯26和间隔件28可通过粘合剂耦接到衬底，并且在特定的具体实施中，可通过焊料材料或银烧结材料将其耦接到衬底。在具有银烧结材料的具体实施中，银烧结材料可通过(非限制性示例)丝网印刷、膜层压、孔版印刷和施加液体或半透明材料的其他方法施加到衬底24或多个管芯26和间隔件28。在各种具体实施中，管芯26和间隔件28可利用热管芯放置通过烧结材料耦接到衬底24。在其他具体实施中，间隔件28可通过方法诸如(非限制性示例)超声键合、熔焊、焊接或任何其它附接方法来键合到衬底24。本文所公开的间隔件28可包括其上可焊接的表面层，该可焊接表面层可通过(非限制性示例)电镀、化学镀、溅射或沉积可焊接材料的任何其它方法来形成。
参见图5，其示出了压力烧结到衬底的多个管芯和间隔件的侧视图。在各种具体实施中，形成半导体封装件的方法可包括固化银烧结材料30。在各种具体实施中，银烧结材料可在约80C至约150C之间固化。在各种具体实施中，可通过将衬底24、管芯26和间隔件28放置在烧结工具32中并向管芯、间隔件和衬底施加压力来将管芯26和间隔件28键合到衬底24。在各种具体实施中，可结合压力，向烧结材料施加热、低热或不施加热。在其他具体实施中，固化可包括施加热而不施加任何压力到管芯26、间隔件28或衬底24。
参考图6，示出了多个夹具的顶视图，并且参考图8，示出了多个夹具的顶部透视图。夹具的数量、夹具的尺寸以及夹具的形状可全部与耦接到衬底的管芯和间隔件相对应，以使得夹具34可被配置为将选择的管芯和至少一个间隔件彼此耦接的方式。因此，尽管图6示出为包括六个不同的夹具，其他具体实施可包括多于或少于六个夹具。尽管图6和图8所示的夹具34看起来是平坦的，但在其他具体实施中，夹具可以是图案化的、成角度的、弯曲的、阶梯式的、下移安置的、或半蚀刻的。图案化的、成角度的、弯曲的、下移安置的、蚀刻的或阶梯式的夹具可与管芯和/或间隔件结合使用，该管芯和/或间隔件具有在沿着夹具的不同位置处具有不同高度/位置/厚度的表面。在包括下移安置的夹具的特定的具体实施中，下移安置部分可添加有阶梯式结构。下移安置部分可以是单测量或双测量系统。参见图7，其示出了图6的多个夹具的底视图，并且参见图9，其示出了图7的多个夹具的底部透视图。在各种具体实施中，形成半导体衬底的方法可包括将粘合剂36施加到多个夹具34的底部。在特定的具体实施中，粘合剂可包含银烧结材料。银烧结材料可通过(非限制性示例)诸如丝网印刷或膜层压的分配技术施加到夹具上。烧结材料可在对应于耦接到衬底的管芯和间隔件的区域中施加到夹具。在其他具体实施中，可在将粘合剂耦接到夹具之前，将粘合剂施加到管芯和间隔件。
参见图10，示出了耦接在管芯和多个间隔件之上的多个夹具的顶视图。在将夹具34耦接到管芯26和间隔件28之后，如图10所示，该方法可包括第二次固化粘合剂。参见图11，示出了烧结工具中的图10的半导体模块的横截面侧视图。在各种具体实施中，形成半导体封装件的方法可包括固化夹具34与管芯26和间隔件28之间的烧结材料38。该方法可包括通过压力烧结过程将夹具34键合到管芯26和间隔件28，该压力烧结过程可包括通过烧结工具32向夹具34、管芯26和间隔件28施加压力，如图11所示。在各种具体实施中，可结合压力，向烧结材料38施加热、低热或不施加热。在其他具体实施中，键合过程可包括施加热而不施加任何压力到管芯26、间隔件28或夹具34。
在各种具体实施中，虽然可使用两个固化步骤，但在其他方法具体实施中，可使用单一固化步骤，其中烧结工具用于同时固化所有烧结材料。
参见图12，示出了半导体模块的顶部透视图。在各种具体实施中，图12的半导体模块44与图1的半导体模块相同。在各种具体实施中，形成半导体封装件的方法可包括将多个引脚40耦接到衬底24。在此类具体实施中，引脚40可通过将焊膏分配到待耦接到引脚40的衬底区域而耦接到衬底24。引脚40和任何其他元件(诸如热敏电阻)可耦接到焊膏，然后可将焊膏回流，从而将引脚40键合到衬底24和/或将模块组件键合到散热器。在焊膏回流期间，导向夹具可用于将引脚40保持在适当位置。
参见图13，示出了半导体封装件的顶视图，并且参见图14，示出了图13的半导体封装件的顶部透视图。在各种具体实施中，图13-14的半导体封装件42与图12的半导体封装件相同。在各种具体实施中，形成半导体封装件42的方法可包括将壳体46耦接在一个或多个半导体模块44之上。虽然图13的半导体封装件被示出为包括三个半导体模块，但其他半导体封装件可包括或多或少的模块，包括仅一个模块、两个模块、一个部分模块、四个模块或多于四个模块。形成半导体封装件的方法还可包括将半导体封装件42耦接到半导体模块的与耦接到壳体的一侧相对的一侧上的背板48。尽管未示出，但该方法还可包括将本文所公开的任何类型的封装剂施加在壳体46内和半导体模块44之上。
图13-图14的半导体封装件的具体实施的任何部件或元件或制备图13-图14的半导体封装件的方法可用于本文所公开的任何其他具体实施中。
参见图15，示出了半导体模块的另一个具体实施的顶视图。在各种具体实施中，图15的半导体模块50可与图1的半导体模块2相似。半导体模块50包括衬底52。在各种具体实施中，衬底可以是DBC衬底或本文所公开的任何其他类型的衬底。衬底可耦接到多个管芯(被夹具覆盖)并且还可包括一个或多个间隔件(被夹具覆盖)。管芯可为本文所公开的任何类型的管芯，并且间隔件可与本文所公开的任何其他间隔件相同或相似。管芯和间隔件可通过粘合剂耦接到衬底52，在具体实施中，该粘合剂可为银烧结材料。在其他具体实施中，管芯和间隔件可通过焊料耦接到衬底52。
如图15所示，半导体模块包括耦接在多个管芯和一个或多个间隔件之上的第一夹具56和第二夹具58。虽然图15被示出为具有两个夹具，但其他具体实施可包括多于两个夹具或仅单个夹具。第一夹具56和第二夹具58可为本文所公开的任何类型的夹具，并且可包括与其所覆盖的各种管芯和间隔件的尺寸、放置和形状相对应的尺寸和图案。第一夹具56和第二夹具58可通过粘合剂耦接到管芯和隔片上，该粘合剂可为银烧结材料。在其他具体实施中，第一夹具56和第二夹具58可通过焊料耦接到管芯和间隔件。在包括一个或多个夹具的具体实施中，与管芯互连的夹具可提供半导体模块的低导通状态电阻(RDS)。夹具还可能够充分利用管芯的顶部金属化。另外，当利用夹具来消除用于形成引线键合的力时，夹具可降低对管芯的损坏风险。夹具可最终导致改善的功率管理、更好的热性能和更高的可靠性。
参见图16至图40，示出了在形成图15的半导体封装件的方法的具体实施中的各个步骤处的半导体封装件。具体参见图16，示出了晶圆的顶视图。晶圆60可包括多个管芯62。多个管芯62可包括本文所公开的任何类型的管芯。参见图17，其示出了从晶圆分离的多个管芯的顶视图。形成半导体封装件的方法包括分离多个管芯62。可通过(非限制性示例)机械锯、激光、喷水法、等离子蚀刻或任何其它分离技术将管芯62分离。参见图18，示出了由烧结材料覆盖的图17的多个管芯的顶视图。在各种具体实施中，形成半导体封装件的方法包括将粘合剂(其可为烧结材料64)分配到多个管芯62的源焊盘区域之上。在特定的具体实施中，粘合剂可包括银烧结材料。烧结材料64可使用本文所公开的任何其他技术来丝网印刷、模版印刷、层压或沉积。虽然具体实施示出了烧结材料64在分离之后被施加到管芯62，但在其他具体实施中，烧结材料可在分离之前施加到管芯。参见图19，示出了正在被固化的图18的多个管芯的顶视图。如图所示，该方法可包括通过施加热来固化烧结材料64。可将烧结材料64加热至介于约80C至约150C之间的温度，但在其他具体实施中，可将其加热至大于或小于该温度的温度。
参见图20，示出了多个夹具的第一具体实施的顶视图。夹具66可包含本文所公开的任何类型的材料。在特定的具体实施中，夹具66可为铜或铜合金。夹具66可被图案化成对应于管芯和/或间隔件的特定布局。如图所示，夹具可横跨夹具66的面68为平坦的。参见图21，其示出了图20的多个夹具的底视图，并且参见图22，其示出了图20的多个夹具的底部透视图。如图所示，夹具66可横跨夹具66的与面68相对的面70为图案化的、阶梯式的、弯曲的或半蚀刻的。这可通过图24描绘，其示出了图20的夹具66的侧视图的一部分。如图24所示，夹具的厚度为阶梯式的。夹具中的步骤可通过(非限制性示例)压模或半蚀刻过程形成。在各种具体实施中，如果要耦接到具有不等厚度的管芯，图20的夹具则可使用。如图24所示，夹具66的第一部分72(其可为较厚部分)可为约175μm厚，并且夹具66的第二部分74(其可为较薄部分)可为约50μm厚。在其他具体实施中，相应部分的厚度可大于或小于图24所示的厚度。在其他具体实施中，夹具66可包括具有不同厚度的多于两个的部分。
在其他具体实施中，夹具可不为蚀刻的或阶梯式的，或者可具有平坦的第一面和相对的第二面。如图23所示，示出了夹具的侧视图。图23的夹具76可在其耦接的管芯具有相等厚度时使用。如图23所示，夹具76的厚度是一致的。在各种具体实施中，夹具76的厚度可为175μm，而在其他具体实施中，夹具的厚度可大于或小于175μm。
参见图25，其示出了由烧结材料覆盖的多个管芯和间隔件的顶视图。在特定的具体实施中，烧结材料78可以是银烧结材料。烧结材料78可使用本文先前公开的任何方法耦接到管芯62。在各种具体实施中，可使用类似于将烧结材料施加到管芯的方法的方法将烧结材料施加到间隔件80。在各种具体实施中，形成半导体封装件的方法包括将管芯62和间隔件80耦接到夹具。参见图26，其示出了耦接到蚀刻夹具的多个管芯和间隔件的侧视图。如图26所示，该方法可包括利用夹具与管芯和间隔件之间的烧结材料78将多个管芯62和间隔件80耦接在夹具66之上。在各种方法具体实施中，可使用热管芯放置技术将管芯和/或间隔件翻转并耦接到夹具。参见图27，示出了被压力烧结到夹具上的图26的多个管芯和间隔件的侧视图。如图27所示，在管芯62已翻转之后，可将管芯62、间隔件80和夹具66放置到烧结工具82中并经受烧结过程。烧结过程可类似于本文所公开的任何烧结过程。由于阶梯式或蚀刻的夹具66，管芯62和间隔件80之间的高度可相等。
参见图28-29，示出了在用于将具有相等厚度的管芯耦接到平面夹具(诸如图23的夹具76)的方法的具体实施的步骤中的封装件的具体实施。具体参见图28，其示出了耦接到夹具76的多个管芯82和间隔件84的侧视图。参见图29，示出了烧结工具中的图28的多个管芯和间隔件的侧视图。管芯82和间隔件84可使用与图26至图27所示相同的方法耦接到夹具76，唯一的区别是夹具不是阶梯式的，并且管芯82和间隔件84中的每一个包括类似的厚度。
参见图30，示出了在压力烧结之后耦接到夹具的图29的多个管芯和间隔件的横截面侧视图。相似地，参见图31，示出了在压力烧结之后耦接到夹具的图27的多个管芯和间隔件的侧视图。参见图32，示出了耦接到夹具的图31的多个管芯和间隔件的底视图。参见图33，示出了耦接到图31的夹具的多个管芯和间隔件的顶视图。
具体参见图34，示出了耦接在多个管芯和间隔件之上的烧结材料的侧视图，该多个管芯和间隔件耦接到图30的夹具。在各种具体实施中，该方法可包括在耦接到夹具76的管芯82和间隔件84键合到夹具之后将它们翻转，并且将粘合剂(其可为包含烧结材料86的本文所公开的任何类型的粘合剂)耦接在管芯82和间隔件84之上，该管芯和间隔件耦接到平面夹具76。烧结材料86可使用本文所公开的任何技术施加。
具体参见图35，示出了耦接在多个管芯和间隔件之上的烧结材料的侧视图，该多个管芯和间隔件耦接到图31的夹具。在各种具体实施中，该方法可包括在耦接到夹具66的管芯62和间隔件80键合到夹具之后将它们翻转，并且将粘合剂(其可为包括烧结材料92的本文所公开的任何类型的粘合剂)耦接在管芯62和间隔件80之上，该管芯和间隔件耦接到蚀刻夹具66。烧结材料92可使用本文所公开的任何技术施加。
参见图36，示出了耦接在衬底之上的烧结材料的侧视图。在各种具体实施中，也可将粘合剂(其可为烧结材料88)施加在衬底90之上。因此，烧结材料可同时施加到衬底、管芯和间隔件。在其他具体实施中，烧结材料耦接在管芯和间隔件之上或衬底之上，但不在两者之上。在具有烧结材料的具体实施中，可通过施加可为本文所公开的任何温度的热量来干燥烧结材料。
参见图37，示出了耦接到烧结工具中的图31的多个管芯、间隔件和夹具的衬底的侧视图。形成半导体封装件的方法包括将管芯62和间隔件80耦接在衬底94之上。在各种具体实施中，管芯62和间隔件80可利用烧结工具96通过压力烧结过程耦接到衬底。烧结过程可以是本文所公开的任何类型的烧结过程。
参见图38，示出了耦接到烧结工具中的图30的多个管芯、间隔件和夹具的衬底的侧视图。形成半导体封装件的方法包括将管芯82和间隔件84耦接在衬底98之上。在各种具体实施中，管芯82和间隔件84可利用烧结工具100通过压力烧结过程耦接到衬底98。烧结过程可以是本文所公开的任何类型的烧结过程。
如图37和图38所示，形成半导体封装件的方法的各种具体实施可包括在管芯和间隔件键合到夹具之后将耦接到夹具的管芯和间隔件翻转。
参见图39，示出了烧结过程之后键合在衬底之上的夹具的顶视图。参见图40，示出了半导体模块的顶视图。图40的半导体模块104可与图15的半导体模块50相同或相似。在各种具体实施中，形成半导体封装件的方法可包括将电连接器102耦接在管芯的选定端子与衬底94之间。
图15的半导体封装件的具体实施的任何部件或元件或制备图15的半导体封装件或图40的模块的方法具体实施的步骤或过程可用于本文所公开的任何其他具体实施中。
参见图41，示出了半导体模块的透视图。图41的半导体模块106可类似于图1的半导体模块，不同之处在于，半导体模块106包括重新分布层(RDL)108，而不是夹具。在此类具体实施中，RDL 108和间隔件可形成模块和管芯之间的互连。RDL还将一个或多个管芯与间隔件电连接。在此类具体实施中，模块可不包括引线键合并且不包括夹具。RDL 108可包括任何类型的金属、其合金、它们的组合或其他导电材料，并且可具有对应于模块的管芯和间隔件的图案。在特定的具体实施中，RDL 108可包括金属电迹线，其可镀/涂覆有银、钯、镍、金或任何其它金属。电迹线可仅在RDL的一侧上。在各种实施方式中，RDL 108可以包括绝缘层110。绝缘层110可耦接在多个管芯和间隔件之上。间隔件可在衬底和RDL 108之间形成附加的连接。在各种具体实施中，间隔件通过本文所公开的任何焊料或粘合剂(包含银烧结材料)直接耦接到衬底和RDL两者。管芯和间隔件可通过RDL 108耦接在一起，而不是经由夹具形成连接。管芯和间隔件可通过粘合剂诸如银烧结材料耦接到RDL。在各种具体实施中，绝缘层110可包含(非限制性示例)氮化硼、氧化铝、氮化铝、氮化硅、钼衍生物、石墨烯衍生物或其他绝缘材料。在各种具体实施中，RDL与管芯的互连可提供半导体模块的低导通状态电阻(RDS)。形成于RDL 108中或形成到其的绝缘层110也可能够充分利用管芯的顶部金属化。此外，由于用作RDL 108的一部分的绝缘层110消除了用于形成引线键合的力，因此绝缘层110可降低对管芯的损坏风险。具有绝缘层110的RDL 108可最终导致改善的功率管理、更好的热性能和更高的可靠性。在各种具体实施中，绝缘层110可包括一个或多个开口，以给引脚、热敏电阻器或被配置为耦接到模块的任何其他器件提供足够的间隙。
参见图42，示出了半导体封装件的顶部透视图。在各种具体实施中，半导体封装件112可包括耦接到壳体114和背板116的图41所示的半导体模块106中的一个或多个。在图42所示的具体实施中，半导体封装件中包括三个模块。在各种具体实施中，壳体114可包括分隔半导体模块106的一个或多个支柱118。尽管未示出，但在各种具体实施中，壳体114的内部可填充有覆盖半导体模块106的密封剂。密封剂可包含灌封化合物，并且在特定的具体实施中，可包含凝胶灌封化合物。在此类具体实施中，引脚120可通过封装剂进行暴露。
参考图43至图53，示出了形成半导体封装件的方法。参见图43，示出了衬底的顶视图。参见图44，示出了耦接在图43的衬底之上的多个管芯和间隔件的顶视图，并且参见图45，示出了烧结工具中的多个管芯和间隔件的侧视图。在各种具体实施中，图43至图45所示的方法可与图3至图5所示的方法类似。
参见图46，示出了RDL的底视图，并且参见图47，示出了图46的RDL的底部透视图。RDL 122可包含本文所公开的任何类型的材料。在各种具体实施中，RDL 122可包括绝缘层124和耦接到或至少部分地嵌入在绝缘层124内的导电迹线126。导电迹线126可包括对应于多个管芯和间隔件的图案，以帮助适应通过管芯和/或间隔件与RDL 122之间的互连的最大功率传输。参见图48，示出了具有耦接到RDL的烧结材料的图46的绝缘层的底视图。在各种具体实施中，形成半导体封装件的方法包括将粘合剂施加到RDL的选定部分。在特定的具体实施中，粘合剂可以是烧结材料128，包括银烧结材料。在此类具体实施中，烧结材料128可使用本文所公开的任何技术来丝网印刷、膜层压、模版印刷或分配在RDL 122上。
参见图49，示出了耦接在多个管芯和间隔件之上的RDL的顶视图。在各种具体实施中，形成半导体封装件的方法包括将RDL 122耦接在多个管芯和间隔件之上。在将RDL 122耦接到管芯和间隔件之后，如图49所示，该方法可包括固化烧结材料。参见图50，示出了烧结工具中的图49的RDL、管芯和间隔件的横截面侧视图。在各种具体实施中，形成半导体封装件的方法可包括将RDL 122键合到管芯130和间隔件132。RDL 122可利用烧结工具134通过压力烧结过程(包括本文所公开的任何烧结或键合过程)键合到管芯130和间隔件132。
参见图51，示出了半导体模块的顶部透视图。图51的半导体模块136可与图41的半导体模块106相同或相似。在各种具体实施中，形成半导体封装件的方法可包括将多个引脚138耦接到衬底140。在此类具体实施中，引脚138可通过将焊膏分配到待耦接到引脚的衬底区域而耦接到衬底140。引脚138和任何其他元件(诸如热敏电阻)可耦接到焊膏，然后可将焊膏回流，从而将引脚138键合到衬底140。在焊膏回流期间，导向夹具可用于将引脚138保持在适当位置。
参见图52，示出了半导体封装件的顶视图，并且参见图53，示出了半导体封装件的顶部透视图。半导体封装件142可与图42的半导体封装件相同或相似。在各种具体实施中，形成半导体封装件的方法可包括将壳体144耦接在一个或多个半导体模块136之上。虽然图52的半导体封装件被示出为包括三个半导体模块，但其他半导体封装件可包括或多或少的模块，包括仅一个模块、两个模块、四个模块或多于四个模块。形成半导体封装件142的方法还可包括将半导体封装件耦接到背板146。尽管未示出，但该方法还可包括将本文所公开的任何类型的封装剂施加在壳体144内和半导体模块136之上。
图42的半导体封装件的具体实施的任何部件或元件或制备图52-图53的半导体封装件的方法的具体实施的方法步骤可用于本文所公开的任何其他具体实施中。
在以上描述中提到半导体封装件的特定实施方式以及实施部件、子部件、方法和子方法的地方，应当显而易见的是，可在不脱离其实质的情况下作出多种修改，并且这些实施方式、实施部件、子部件、方法和子方法可应用于其他半导体封装件。

Claims (10)

1.一种半导体封装件，包括：
一个或多个管芯，所述一个或多个管芯耦接在衬底之上；
导电间隔件，所述导电间隔件耦接在所述衬底之上；和
夹具，所述夹具耦接在所述一个或多个管芯和所述导电间隔件之上并且耦接到所述一个或多个管芯和所述导电间隔件；
其中所述夹具将所述一个或多个管芯与所述导电间隔件电耦接。
2.根据权利要求1所述的封装件，其中所述夹具包括具有第一厚度的第一部分和具有第二厚度的第二部分。
3.根据权利要求1所述的封装件，其中所述导电间隔件为竖直连接系统。
4.一种半导体封装件，包括：
一个或多个管芯，所述一个或多个管芯耦接在衬底之上；
导电间隔件，所述导电间隔件耦接在所述衬底之上；和
重新分布层RDL，所述RDL包含耦接在所述一个或多个管芯和所述导电间隔件之上的氮化硼；
其中所述RDL将所述一个或多个管芯与所述导电间隔件电连接。
5.根据权利要求4所述的封装件，其中所述导电间隔件通过焊料或粘合剂中的一者直接耦接到所述衬底和所述RDL两者。
6.根据权利要求5所述的封装件，其中所述焊料或所述粘合剂中的所述一者包含银烧结材料。
7.一种形成半导体封装件的方法，包括：
将烧结材料施加在多个管芯的第一侧或夹具的第一侧中的一者之上；
将烧结材料施加到导电间隔件的第一侧或所述夹具中的一者；
通过所述烧结材料将所述导电间隔件和多个管芯压力烧结到所述夹具；
将烧结材料施加到所述多个管芯的第二侧或衬底中的一者，该第二侧与所述多个管芯的第一侧相对；
将烧结材料施加到所述导电间隔件的第二侧或所述衬底中的一者，该第二侧与所述导电间隔件的第一侧相对；以及
通过所述烧结材料将所述衬底压力烧结到所述导电间隔件和多个管芯。
8.根据权利要求7所述的方法，其中在将所述多个管芯和所述导电间隔件压力烧结到所述夹具之后，将所述多个管芯和所述导电间隔件翻转，然后所述多个管芯和所述导电间隔件随后被压力烧结到所述衬底。
9.根据权利要求7所述的方法，还包括蚀刻所述夹具。
10.根据权利要求7所述的方法，其中在所述多个管芯和所述导电间隔件被压力烧结到所述衬底之后，所述多个管芯和所述导电间隔件被压力烧结到所述夹具。
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