JP7006015B2 - 半導体モジュールの製造方法 - Google Patents
半導体モジュールの製造方法 Download PDFInfo
- Publication number
- JP7006015B2 JP7006015B2 JP2017160487A JP2017160487A JP7006015B2 JP 7006015 B2 JP7006015 B2 JP 7006015B2 JP 2017160487 A JP2017160487 A JP 2017160487A JP 2017160487 A JP2017160487 A JP 2017160487A JP 7006015 B2 JP7006015 B2 JP 7006015B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor
- heat sink
- solder
- metal block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Die Bonding (AREA)
Description
12、112:半導体素子
12a、112a:半導体素子の上面
12b、112b:半導体素子の下面
18:金属ブロック
20、120:上側放熱板
22、122:下側放熱板
26、126:モールド樹脂
28、30、32、128、130、132:はんだ
106:プライマ
108:リードフレーム
Claims (1)
- 半導体モジュールの製造方法であって、
半導体素子の一方の面に、はんだを介して第1導体板を接合する第1工程と、
前記第1工程後の前記半導体素子の他方の面を、はんだを介して第2導体板に接合する第2工程と、を備え、
前記第1導体板のサイズは、前記半導体素子のサイズよりも小さく、前記第2導体板のサイズは、前記半導体素子のサイズよりも大きく、
前記第1導体板の線膨張係数は、前記半導体素子の線膨張係数よりも大きい、半導体モジュールの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017160487A JP7006015B2 (ja) | 2017-08-23 | 2017-08-23 | 半導体モジュールの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017160487A JP7006015B2 (ja) | 2017-08-23 | 2017-08-23 | 半導体モジュールの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019040955A JP2019040955A (ja) | 2019-03-14 |
JP7006015B2 true JP7006015B2 (ja) | 2022-01-24 |
Family
ID=65726803
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2017160487A Active JP7006015B2 (ja) | 2017-08-23 | 2017-08-23 | 半導体モジュールの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7006015B2 (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011029589A (ja) | 2009-06-30 | 2011-02-10 | Denso Corp | 半導体装置およびその製造方法 |
-
2017
- 2017-08-23 JP JP2017160487A patent/JP7006015B2/ja active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011029589A (ja) | 2009-06-30 | 2011-02-10 | Denso Corp | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
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JP2019040955A (ja) | 2019-03-14 |
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