CN104170082B - 系统级封装件及其制造方法 - Google Patents

系统级封装件及其制造方法 Download PDF

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CN104170082B
CN104170082B CN201380010431.XA CN201380010431A CN104170082B CN 104170082 B CN104170082 B CN 104170082B CN 201380010431 A CN201380010431 A CN 201380010431A CN 104170082 B CN104170082 B CN 104170082B
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substrate
package
semiconductor chip
laminate
contact pad
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CN104170082A (zh
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B·兰格
J·诺伊豪斯勒
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

提供一种系统级封装件及其制造方法。系统级封装件包括具有基板(4)设置在其内部的层合体。半导体芯片(2)嵌入到层合体中，并且半导体通过烧结的键合层键合到基板(4)的接触垫(6)，其中烧结的键合层由烧结膏制成。基板和提供层合体的其它层的层合以及烧结膏的烧结可以在单一、共同的固化步骤中执行。

Description

系统级封装件及其制造方法
技术领域
本发明的实施例涉及系统级封装件(SIP)，其包括具有基板和设置在其中的半导体芯片的层合体。另外，其它实施例涉及制造系统级封装件的方法。
背景技术
对成本降低的小型电子系统的需求的不断增长要求可靠和经济有效的半导体封装件具有小的形状因素。对于便携式电子产品，更小的封装和更小的子系统封装已经成为主流。尺寸减小不再仅仅集中于封装表面区域，封装件的厚度和重量也应该减小。
满足不断增长的客户需求的其中一种方法被称为“系统级封装件”，它被开发以解决许多应用诸如计算和通信所面临的日渐增多的挑战。系统级封装件，例如购自德州仪器公司(美国德克萨斯州达拉斯市)MicroSlP(μSIP)的封装件，包括半导体芯片、控制器，例如在层合基板中。另外，有源和/或无源电子组件(诸如电感器)通过将它们设置在层合基板或层合体的上表面的顶部上而被包含在系统级封装件中。
然而，半导体芯片的键合仍然基于引线框，这意味着芯片是利用铜夹片键合到引线框，引线框馈出到封装件底侧。铜夹片需要占用封装件内的空间。因此，相对于组装工艺速度可以对空间进行改进。
发明内容
根据本发明的一方面，提供一种系统级封装件，其包括层合体，所述层合体包括设置在其中的基板。优选地，基板被预先压制。半导体芯片嵌入在层合体中，并且半导体芯片的至少一个接触区域通过烧结的键合层键合到基板的接触垫，所述键合层由烧结膏制成。
根据本发明的一方面，系统级封装件可以在联合(combined)的压制和烧结工艺中制造。换言之，热和压力均被施加到形成层合体的堆叠体(stack)上。压制步骤通常从印刷电路板的制造中得知，并且通常在约200℃范围的工艺温度下执行。有利地，并且根据本发明的一方面，可以确定这种压制步骤的工艺参数也适于执行烧结工艺。因此，提供联合的压制和烧结步骤。烧结膏的烧结发生并且在用于堆叠体的层合的同一工艺步骤内提供烧结的键合层。
根据本发明的另一方面，提供一种制造系统级封装件的方法。将烧结膏施加到基板的接触垫和/或半导体芯片的接触区域。优选地，烧结膏的施加通过膏印刷执行，并且烧结膏被施加到半导体芯片的接触区域或基板的接触垫的二者之一。半导体芯片的接触区域放置在基板的接触垫上。换言之，半导体芯片的接触区域和基板的接触垫相互叠合(register)。将基板和所放置的半导体芯片以及形成系统级封装件的层合体的其它层堆叠到一起。最后，对堆叠体执行联合压制和烧结步骤。在这种联合压制和烧结步骤期间，堆叠体的基板和其它层被层合以提供层合体。进一步，在联合压制和烧结步骤期间，烧结膏的烧结被执行以提供基板的接触垫与半导体芯片的接触区域之间的电连接。换言之，堆叠体的层合和电接触在共同的单一工艺步骤中执行。
在联合压制和烧结步骤期间，所述堆叠体可暴露于热和压力中，如同通常所知的印刷电路板的制造。进一步，所述方法可包括预先压制基板的步骤，并且在压制和烧结堆叠体之前将半导体芯片设置在所述预先压制的基板上。进一步地，烧结膏的部分预烧结可以在最后的压制和烧结步骤之前执行。
附图说明
图1示出用于制造系统级封装件的简化堆叠体的示意图，示出了在放置半导体芯片之后并在烧结和压制堆叠体之前的堆叠，
图2示出图1的堆叠体的示意图，其中填充材料被插入后续基板之间，
图3示出通过固化从图1和图2得到的堆叠体来制造简化的系统级封装件的示意图，
图4示出图3的简化的系统级封装件的示意图，其中插入通孔以提供系统级封装件的上、中和下互联表面之间的连接，
图5示出没有下基板的进一步简化的系统级封装件的示意图，
图6示出没有与上表面和下表面相邻的基板的另一个简化的系统级封装件的示意图，
图7示出包括并排放置的两个功率场效应晶体管(FET)和堆叠在FET顶部的控制器的进一步简化的系统级封装件的示意图，
图8示出包括并排放置的两个功率FET和放置在上表面上的无源组件的另一个简化的系统级封装件的示意图，
图9示出包括并排放置的两个功率FET和无源组件的简化系统级封装件的示意图，其中芯片直接堆叠成芯片堆叠芯片的结构(die-on-die configuration)，
图10和图11示出包括半导体芯片和提供高电流连接的金属块的进一步简化的系统级封装件的示意图。
具体实施方式
图1示出用于制造系统级封装件的一种简化堆叠体。示出了在放置半导体芯片2到各个基板4上之后并在烧结和压制堆叠体之前的堆叠。优选地，基板4被预先压制，并且进一步优选地，它们由印刷电路板材料诸如纤维增强树脂制成。基板4的接触垫6优选由铜制成，并具有由不活泼(noble)金属制成的镀层7。当考虑电势序时，镀层7的材料优选比铜更不活泼。优选地，采用镍银(NiAu)或镍金(NiAg)用于镀层7。有利地，例如，NiAu镀层7阻止铜(Cu)接触垫6在烧结过程中氧化。进一步地，存在设置在半导体芯片2的接触区域中的镀层7。半导体芯片2的前面和后面都可以提供有NiAu镀层7。换言之，每个接触区域或接触垫6(其被指定通过烧结的连接而进行耦合或接触)都提供有不活泼金属涂层7，以阻止烧结的电接触发生氧化。
导电通孔8(为了清晰起见，只有一些通孔8用附图标记标注)穿通基板4。对于设置在堆叠体中间的基板4，通孔8用于将设置在基板4的第一表面上的相应接触垫6与设置在基板4的相反表面上的另一接触垫6电耦合。优选地，导电通孔8是铜填充的钻孔。在上基板4处，通孔8将设置在基板4内表面处的接触垫6与设置在上表面28处的上接触垫10电耦合。类似的操作应用于下基板4，通孔8用于将设置在内表面处的接触垫6与设置在堆叠体的下表面26处的下接触垫12耦合。其它有源和/或无源组件可以设置在上表面28处，并且可以耦合到上接触垫12。如果系统级封装件安装到印刷电路板，则堆叠体的下表面26通常面朝印刷电路板。系统级封装到印刷电路板的电耦合可通过下接触垫12提供。
在图1的实施例中，基板4的接触垫6，更精确的是上基板和中间基板4的下接触垫6的镀层7设有烧结膏14，其优选通过烧结膏印刷施加。优选地，烧结膏14由比Cu更不活泼的金属或金属合金制成。这也是考虑了电势序并且优选材料为基于Ag的烧结膏14。对于系统级封装件的制造，将烧结膏14施加于半导体芯片2的接触区域和基板4的接触垫6中的任一个或两者。优选地，并且根据图1的实施例，将烧结膏14印刷到基板4的接触垫6。然后将半导体芯片2放置在基板4的相应接触垫6上的烧结膏14的顶部上，这表示半导体芯片2的接触区域与基板4的接触垫6叠合。
在图1的实施例中，半导体芯片2的背面已经设置有烧结膏，并且已执行预烧结步骤，以便将半导体芯片2的背面附接到基板4。在预烧结步骤中，烧结膏变成烧结的键合层16，其设置在芯片2的背面和基板4的上接触垫6之间。例如，半导体芯片2是功率MOSFET，并且示出的堆叠体用于提供堆叠的功率FET结构。
图2示出从图1得知的堆叠体，其中填充材料18插入在相邻基板层4之间。填充材料18在堆叠步骤期间被添加到堆叠体，并且优选地，填充材料18被预切割以适应半导体芯片2。填充材料18还可以适应附加的有源和/或无源组件(未示出)，这些组件可以集成在系统级封装件中。填充材料18用于在后续压制和烧结步骤期间填充堆叠体中的空隙。
在联合压制和烧结步骤中，图2的堆叠体暴露于热和压力，其中执行该步骤的参数可以在通常从印刷电路板的制造中得知的温度和压力的范围中。例如，可采用约200℃的固化温度。在所述联合压制和烧结步骤期间，执行基板4和填充材料18的层合以提供系统级封装件的层合体。同时，对烧结膏14进行烧结，以便耦合或键合基板4的接触垫6和半导体芯片2的连接区域。有利地，系统级封装件可以在联合工艺步骤中制造，这意味着层合和烧结是在单一共同的工艺步骤中执行。这简化了系统级封装件的制造工艺。进一步有利的是，半导体芯片2直接键合到相应的导电路径或基板4的接触垫6。不需要引线框。引线框以及半导体芯片2与引线框之间所需的键合线的键合工艺的弃用对于制造成本是有利的，并且进一步加速制造过程。
图3示出包括层合体的简化的系统级封装件20，其中层合体基本上由基板4、固化的填充材料22和嵌入的半导体芯片2制成。在联合压制和烧结步骤中，先前已经施加或印刷在上基板和中间基板4的下接触垫6上的烧结膏垫16变成烧结的键合层16。半导体芯片2的接触区域通过烧结的键合层16耦合到基板4的接触垫6。
在图3的系统级封装件20中，半导体芯片2经由导电通孔8耦合到上接触垫10和下接触垫12。其它有源和/或无源电子组件可以嵌入在上接触垫10上或耦合到上接触垫10。例如，对于给定的堆叠的功率MOSFET结构，这些其它有源和/或无源电子组件(未示出)可以是电感器或电容器，以便提供具有较小形状因素和较小封装的高度集成的功率变换器。系统级封装件2的下接触垫12可通过采用任意常规键合或焊接技术耦合到电子设备的印刷电路板。
图4示出图3的系统级封装件20，然而，根据图4的实施例，垂直连接件24(其可以是铜填充的通孔)被插入到系统级封装件20中。如果需要，垂直连接件24用于将系统级封装件20的上接触垫10与下接触垫12和中间基板4的接触垫12耦合。系统级封装件20还可以包括电子组件(未示出)，其嵌入到层合体中。例如，控制器可以集成到系统级封装件20中，并且可以用于控制功率MOSFET(即半导体芯片2)，以便提供高度集成的功率级。这些其它有源和/或无源电子组件可通过垂直连接件24耦合到系统级封装件20的相应上和/或下接触垫10、12。优选地，其它电子组件，例如，控制器芯片或小电容器嵌入在系统级封装件20的第二层中。因此，上侧28的空间可被利用以用于模块所需的较大电子部件或组件。
根据本发明的另一个实施例，同一半导体芯片2的接触区域可经由基板4耦合。换言之，半导体芯片2的第一接触区域可耦合到基板4的接触垫6，并且所述基板4的另一个接触垫6耦合到所述半导体芯片2的另一个接触区域。根据本发明的一方面，另一个接触区域可以是另一个半导体芯片2的接触区域。后续实施例允许经由基板4耦合两个或更多个半导体芯片2。各个接触区域和接触垫6之间的电连接可由烧结膏14制成的烧结的键合层16提供。有利地，这一方面消除了复杂的芯片间引线键合的需要。可以简化各系统级封装件组装到的PCB的复杂布线。
尤其是当功率MOSFET被用作半导体芯片2时，半导体芯片2的热耦合会是重要的问题。因此，可以有利地提供这样的系统级封装件20，即不具有与系统级封装件20的上和/或下表面28、26相邻的基板层4。
图5示出根据本发明的一个实施例的另一个简化的系统级封装件20，其中基板4不与下表面26相邻。因此，尤其对于下部半导体芯片2，到印刷电路板具有非常高效的热传递，其中印刷电路板可以设置成相邻于系统级封装件20的下表面26。在原理上，图5中的系统级封装件20的结构从图4获知，除了没有基板4相邻于下表面26。因此，图5的系统级封装件20的结构将不再重复说明。
图6示出根据本发明的另一个实施例的另一步简化的系统级封装件20。为提供系统级封装件20的上部芯片2到上表面28以及下部芯片2到下表面26的高效热耦合，可以有利地分配与下表面26相邻的基板4，以及分配与上表面28相邻的基板4。因此，根据图6的实施例的系统级封装件20只包括位于系统级封装件20中心的单个基板4。这对于上部半导体芯片和下部半导体芯片而言，具有非常高效的散热。根据图6的实施例的系统级封装件20的结构在原理上从图5获知，除了省略与上表面28相邻的基板4。因此，对于系统级封装件20的结构的说明不再重复。
图7示出根据本发明的另一个实施例的简化的系统级封装件20。系统级封装件20包括基板层4，其设置在系统级封装件20的中心并且与嵌入第一和第二半导体芯片2的固化的填充材料22相邻，其中第一半导体芯片和第二半导体芯片以堆叠的方式设置在下层中。进一步地，控制器30设置在系统级封装件20的上层中。系统级封装件20的下表面26处没有基板层，以便提供从半导体芯片2(根据图7中的实施例，其为功率MOSFET)到印刷电路板的高效散热，其中所述印刷电路板可以与系统级封装件20的下侧26相邻。
半导体芯片2通过烧结的键合层16键合到嵌入于系统级封装件20的下表面26中的下接触垫12和基板4的接触垫6。类似的操作应用于控制器30，所述控制器30通过烧结的键合层16键合到基板层4。然而，也可以采用标准的芯片附接方法键合控制器30。如已经关于图1至图6中的实施例提到的，根据图7的实施例的系统级封装件20可以是层叠的，并且为提供半导体芯片2与控制器30的键合的层合体(主要包括基板4和填充材料，被示为固化的填充材料22)的层合以及烧结膏垫的烧结是在单个联合的工艺步骤中执行。可通过使用常规技术将用于耦合控制器30的其它接触件32插入系统级封装件20的上表面28中。控制器30到下接触垫12的耦合可通过垂直连接件24提供，其中所述垂直连接件24可以是铜填充的通孔并且用于将控制器30的上侧与下接触垫12耦合。上表面28顶部上的附加层能够提供用于上部设置的外部组件的空间和互连。
图8示出类似于根据图7的系统级封装件20的配置的简化的系统级封装件20。然而，基板4没有设置在堆叠体的中心。基板4设置成相邻于系统级封装件20的上表面28。利用常规技术将控制器30耦合于基板4的接触垫6。基板4的接触垫6到下接触垫12的耦合可通过垂直连接件24提供，其中所述垂直连接件24可以是铜填充的通孔。半导体芯片2和控制器30(半导体芯片2仍然可以是功率MOSFET)嵌入在固化的填充材料22中。半导体芯片2通过从图7得知的烧结的键合层16耦合到下接触垫12。然而，半导体芯片2和控制器30设置成芯片堆叠芯片的结构，这意味着芯片2和控制器30直接互相堆叠在其上，中间没有基板。芯片2、30的键合通过烧结的键合层16执行。控制器芯片30的背面(其镀有不活泼金属镀层7)相邻于烧结的键合层16，其进一步相邻于半导体芯片2的不活泼金属镀层7。
图9示出另一个简化的系统级封装件20，其包括两个半导体芯片2，其中所述两个半导体芯片2可以是半导体半桥结构的功率MOSFET。系统级封装件20包括基板4，其相邻于系统级封装件20的上表面28。基板4包括接触垫6，其通过烧结的键合层16耦合到半导体芯片2的接触区域。半导体芯片2的背面通过烧结的键合层16耦合到下接触垫12。有利地，可以提供从半导体芯片2到印刷电路板的高效散热，其中所述印刷电路板可以相邻于系统级封装件20的下表面26。设置在半导体芯片2的上部有源侧的半导体芯片2的接触区域还可以通过垂直连接件24耦合到下接触垫12，其中所述垂直连接件24延伸通过层合体向下到达基板层4的接触垫6。外部散热器(未示出)或其他有源和/或无源元件34可以附接到上表面28。仅示例，其他元件34通过垂直连接件24耦合到下接触垫12。进一步地，上表面28的顶部上可以存在额外基板层(未示出)，其能够提供用于额外有源和/或无源外部组件的空间。
图10示出包括两个半导体芯片2的简化的系统级封装件20，其中所述两个半导体芯片可以是半导体半桥结构的功率MOSFET。进一步地，根据图10中的实施例的系统级封装件20包括金属块36，其用作高电流导电路径。其它有源和/或无源电子组件(未示出)可集成到系统级封装件20中。半导体芯片2通过烧结的键合层16耦合到基板4的接触垫6和下接触垫12，其中所述烧结的键合层16相邻于接触垫6、12的相应镀层7。金属块36的上表面和下表面也设有镀层7。优选地，将Cu块用作金属块36。为阻止Cu在烧结工艺期间发生氧化，金属块36上具有不活泼金属镀层7。Cu的氧化将有可能损坏烧结的键合的质量，但由于存在镀层7，因此可以不考虑这种现象。金属块36用作高电流连接件，提供从半导体芯片2的上侧经由接触垫6和金属块36到电路板的导电路径，其中所述电路板可设置成相邻于系统级封装件20的下表面。
通常，金属块36的集成与半导体芯片2的集成具有可比性。换言之，如果有必要或需要，上述引用的实施例中的每个半导体芯片2可以用适当电镀的金属块26替代。金属块36在系统级封装件20中的集成和设置可由高电流连接件的需求驱动。
图11示出另一个简化的系统级封装件20，其与根据图10的系统级封装件20具有可比性。为了清晰起见，仅示出单个半导体芯片2。然而，图11中的系统级封装件可以类似于图10中的实施例配置，这意味着系统级封装件可包括设置成半桥结构的两个半导体芯片2。在图11中，图11左侧的垂直连接件24由填充的通孔提供。然而，垂直连接件可由金属球36提供，其示出在系统级封装件20的右侧。金属球36包括不活泼金属镀层7，并且被烧结，经由烧结的键合层16一边到达接触垫6，另一边到达接触垫12。金属球36的嵌入可类似于金属块36的集成，金属块36被示出在系统级封装件20的中心。
尽管已在本文参考具体实施例描述了本发明，但并不限于这些实施例，并且毫无疑义的，本领域技术人员将想到落入要求保护的本发明的范围内的其它替代实施例。

Claims (11)

1.一种系统级封装件，所述系统级封装件具有：
层合体；
设置在所述层合体内部的基板；
所述基板上的至少一个接触垫；和
嵌入于所述层合体中的半导体芯片，
其中所述半导体芯片的至少一个接触区域通过烧结的键合层键合到所述基板的所述至少一个接触垫，其中所述半导体芯片的接触区域由金属或金属合金制成或镀有金属或金属合金，当考虑电势序时，所述金属或金属合金比铜更不活泼。
2.根据权利要求1所述的系统级封装件，其中所述半导体芯片的所述接触区域具有铜基和设置在所述铜基上的金属涂层，所述金属涂层包含银或金。
3.根据权利要求1所述的系统级封装件，其中所述基板的所述接触垫具有铜基和设置在所述铜基上的金属涂层，所述金属涂层包含银或金。
4.一种系统级封装件，所述系统级封装件具有：
层合体；
设置在所述层合体内部的基板；
所述基板上的至少一个接触垫；和
嵌入于所述层合体中的半导体芯片，
其中所述半导体芯片的至少一个接触区域通过烧结的键合层键合到所述基板的所述至少一个接触垫，其中所述基板的接触垫由金属或金属合金制成或镀有金属或金属合金，当考虑电势序时，所述金属或金属合金比铜更不活泼。
5.一种系统级封装件，所述系统级封装件具有：
层合体；
设置在所述层合体内部的基板；
所述基板上的至少一个接触垫；和
嵌入于所述层合体中的半导体芯片，
其中所述半导体芯片的至少一个接触区域通过烧结的键合层键合到所述基板的所述至少一个接触垫，其中，所述烧结的键合层由包括金属或金属合金的烧结膏制成，当考虑电势序时，所述金属或金属合金比铜更不活泼。
6.一种系统级封装件，所述系统级封装件具有：
层合体；
设置在所述层合体内部的基板；
所述基板上的至少一个接触垫；和
嵌入于所述层合体中的半导体芯片，
其中所述半导体芯片的至少一个接触区域通烧结的键合层键合到所述基板的所述至少一个接触垫，其中所述半导体芯片耦合到所述封装件的上接触垫和/或下接触垫，所述上接触垫和/或下接触垫设置在所述层合体的上表面或下表面，其中没有基板被设置成相邻于所述层合体的所述上表面和/或下表面。
7.一种系统级封装件，所述系统级封装件具有：
层合体；
设置在所述层合体内部的基板；
所述基板上的至少一个接触垫；和
嵌入于所述层合体中的半导体芯片，
其中所述半导体芯片的至少一个接触区域通过烧结的键合层键合到所述基板的所述至少一个接触垫，其中，多个半导体芯片嵌入所述层合体中，并且其中所述多个半导体芯片的接触区域通过烧结膏制成的烧结的键合层相互键合，并且其中所述多个半导体芯片直接堆叠成芯片堆叠芯片的结构，而不在所述芯片之间设置基板。
8.一种系统级封装件，所述系统级封装件具有：
层合体；
设置在所述层合体内部的第一基板；
所述第一基板上的至少一个接触垫；
嵌入于所述层合体中的半导体芯片，
其中所述半导体芯片的至少一个接触区域通过烧结的键合层键合到所述第一基板的所述至少一个接触垫；
设置在所述第一基板上的多个半导体芯片，其中第一半导体芯片和第二半导体芯片设置在所述第一基板的相对表面上，从而形成堆叠的半导体结构；
第二基板，其被设置成关于所述第一半导体芯片或第二半导体芯片与所述第一基板相对；和
第三基板，其被设置成关于所述第一基板与所述第二基板相对，以便形成具有分别设置在上表面和下表面上的所述第二基板和所述第三基板的封装件，并提供关于所述第一基板对称的堆叠封装件。
9.根据权利要求8所述的系统级封装件，进一步包括高导电性材料的金属块，当考虑电势序时，所述金属块具有由比铜更不活泼的金属或金属合金制成的涂层。
10.根据权利要求9所述的系统级封装件，其中所述金属块是铜块并且所述涂层包含银和/或金。
11.一种制造系统级封装件的方法，所述方法包括：
将第一基板嵌入于层合体中，
对所述第一基板的多个接触垫和/或第一半导体芯片的多个接触区域施加烧结膏，
将所述第一半导体芯片的所述接触区域放置在所述第一基板的所述接触垫上，
将所述第一基板和所放置的第一半导体芯片与形成所述系统级封装件的层合体的其它层堆叠到一起，其中所述其它层包括：
至少第二半导体芯片，其设置在所述第一基板的相对表面上，从而形成堆叠的半导体结构；
第二基板，其被设置成关于所述第一半导体芯片或第二半导体芯片与所述第一基板相对；
第三基板，其被设置成关于所述第一基板与所述第二基板相对，以便形成具有分别设置在上表面和下表面上的所述第二基板和所述第三基板的封装件，并提供关于所述第一基板对称的堆叠封装件；以及
对所述堆叠执行联合的压制和烧结步骤，以便层合所述第一基板和所述其它层，从而提供所述层合体并执行所述烧结膏的烧结以提供所述接触垫与所述接触区域之间的电连接，其中，在所述联合的压制和烧结步骤中提供层合和电接触。
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