CN112714539A - 电子组件及制造电子组件的方法 - Google Patents

电子组件及制造电子组件的方法 Download PDF

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Publication number
CN112714539A
CN112714539A CN201911019157.8A CN201911019157A CN112714539A CN 112714539 A CN112714539 A CN 112714539A CN 201911019157 A CN201911019157 A CN 201911019157A CN 112714539 A CN112714539 A CN 112714539A
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China
Prior art keywords
pcb
copper block
copper
sintering
flip
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CN201911019157.8A
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English (en)
Inventor
杨程
D·尚关
姚力
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Flextronics Co ltd
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Flextronics Co ltd
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Application filed by Flextronics Co ltd filed Critical Flextronics Co ltd
Priority to CN201911019157.8A priority Critical patent/CN112714539A/zh
Priority to US16/709,750 priority patent/US11270974B2/en
Publication of CN112714539A publication Critical patent/CN112714539A/zh
Priority to US17/668,921 priority patent/US20220238482A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/066—Heatsink mounted on the surface of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity

Abstract

一种电子组件和一种制造电子组件的方法，所述方法包含将电子组件表面安装到印刷电路板PCB；将倒装芯片裸片集成电路IC施加到所述PCB；以及对所述倒装芯片IC进行底部填充以固定所述PCB。所述方法还包含将铜块烧结到所述PCB，其中所述铜块与所述IC热连通，并充当去除由所述倒装芯片IC产生的热量的热路径。

Description

电子组件及制造电子组件的方法
技术领域
本公开涉及将高功率装置电性地且机械地连接到电路板的方法，且具体地，涉及减小印刷电路板的整体厚度并在随后的制造步骤中增加其对温度的弹性的方法。
背景技术
有多种方法能将功率装置连接到印刷电路板(PCB)。由于这些功率装置中的一些功率装置(例如射频(RF)晶体管)产生的热量，因此需要将导热材料添加到封装以管理这种产生的热量。通常，具有这些RF晶体管的集成电路(IC)安装在铜块或铜币上。可以在图1A中的PCB 100中看到这种配置的实例，所述PCB包含通过热结合剂106(例如，导热粘合剂或环氧树脂)连接到铜块104的IC 102。铜块104粘合到PCB 100。图1A描绘了具有平坦铜块的实例。引线接合108将IC 102连接到PCB 100。
图1B描绘的替代方案包含插入PCB 100中的T形铜块。可以看出，铜块104可以比图1A描绘的铜块更薄，且实际上比PCB 100更薄。在这种情况下，铜块的底侧可以经过覆层和镀覆以用于接地连接。然而，铜块104的厚度和形状可以是用于PCB 100的处理技术的任何合适的厚度和形状。在铜块的厚度等于或大于PCB 100的情况下，铜块104的两侧需要进行闪蒸以达到期望厚度。
在图1C中可以看到将IC 102连接到PCB 100的第三种方法，其中作为预浸料层压过程的一部分将铜块104插入到PCB 100中。嵌入式铜块104在顶部和底部均是平坦的。作为其制造过程的一部分，这些方法还可能需要将铜层嵌入到PCB中。
然而，这些方法有很多不足之处。他们可能需要蚀刻铜块以形成输入/输出焊盘，这可能会导致板翘曲。PCB板的厚度是有限的，由于铜块与PCB之间需要粘合，因此它不能太薄。另外，还有面积比限制(即，与整个板面积相比，铜块不能太大)。此外，在预浸料层压中，至少需要4层板来镶嵌铜。无论PCB是无芯设计(任何层工艺)还是具有去除了铜箔的芯，2层仍需要层压。此外，当采用大尺寸的铜块时，存在翘曲控制的挑战。
需要一种能解决已知技术的缺点和缺陷的将IC连接到PCB的方法。
发明内容
本公开的一个方面涉及一种制造电子组件的方法，所述方法包含：将电子组件表面安装到印刷电路板(PCB)，将倒装芯片裸片集成电路(IC)施加到所述PCB，对所述倒装芯片IC进行底部填充以固定所述PCB。所述方法还包含将铜块烧结到所述PCB，其中所述铜块与所述IC热连通，并充当去除由所述倒装芯片IC产生的热量的热路径。
实施方案可以包含以下特征中的一或多者。所述方法进一步包含在所述PCB中布设空腔以接收所述倒装芯片IC，其中通过热结合剂将所述铜块热连接到所述倒装芯片IC。所述方法进一步包含研磨所述铜块的背侧以进行表面加工，其中所述铜块为T形，其中所述铜块是平坦的，其中所述烧结是低温烧结，其中在压力下执行所述低温烧结。所述方法进一步包含将所述PCB分离以隔离单个电子组件。所述方法进一步包含将铜柱烧结到所述PCB并将所述铜块连接到所述铜柱。
本公开的另一方面涉及一种制造电子组件的方法，所述方法包含布设印刷电路板(PCB)以形成开口。所述方法还包含将铜块烧结到所述PCB，使得所述铜块布置在所述开口中；将电子组件表面安装到所述PCB；将集成电路(IC)附接到所述铜块；将所述IC引线接合到所述PCB。所述方法还包含包覆模制所述PCB。
实施方案可以包含以下特征中的一或多者。所述方法进一步包含研磨所述铜块的背侧以进行表面加工，其中所述开口是穿过所述PCB的孔，其中所述开口是所述PCB中的空腔，其中通过热结合剂将所述铜块热连接到所述IC，其中所述铜块为T形，其中所述铜块是平坦的，其中所述烧结是低温烧结，其中在压力下执行所述低温烧结。
本公开的又一方面涉及一种电子组件，所述电子组件包含：印刷电路板，所述印刷电路板包含在其中形成的开口。所述电子组件还包含放置在所述开口中并连接到所述印刷电路板的集成电路(IC)。所述电子组件还包含热连接到所述(IC)且烧结到所述PCB的铜块。
附图说明
下文参考图式描述本公开的各种方面，图式并入本说明书中并且构成本说明书的一部分，其中：
图1A是使用已知技术制造的PCB的横截面图；
图1B是使用已知技术制造的另一PCB的横截面图；
图1C是使用已知技术制造的又一PCB的横截面图；
图2A是根据本公开的PCB的横截面图；
图2B是根据本公开的另一PCB的横截面图；
图2C是根据本公开的堆叠封装PCB组合件的横截面图；
图3A是根据本公开的倒装芯片PCB的横截面图；
图3B是根据本公开的另一倒装芯片PCB的横截面图；
图4是根据本公开的用于倒装芯片PCB制造的流程图；以及
图5是根据本公开的用于PCB制造的流程图。
具体实施方式
下文参考附图更详细地描述本公开的示例性实施例的另外细节和方面。
本公开涉及使用烧结技术将铜块连接到PCB的方法。如本文所使用，术语PCB包含电子器件制造中使用的集成电路(IC)封装衬底。根据本公开，将铜块直接烧结到PCB上。这允许减小铜块的大小，并且不需要厚的铜蚀刻。此外，这些烧结技术不需要在PCB中嵌入铜层。这些优点使PCB可以更薄，而不会经受翘曲的最坏影响和制造过程中的其它破坏影响。虽然由于烧结仍可能会发生一些翘曲，但是使用本文描述的低温技术能减少这些影响。
本公开的一个方面是本文描述的方法发生的制造过程的级别。传统的币焊接是发生在互连级别的电子器件层次结构的2级的PCB组合件制造过程。本公开涉及发生在互连级别的电子器件层次结构的1级的封装级别过程。以这种方式，IC可以在较低的互连级别直接连接到铜块(导热焊盘)，从而减少了在2级互连级别所需的处理步骤。
图2A是根据本公开的一个方面的PCB 200的图示。PCB 200包含孔201，IC 202和铜块204的一部分位于所述孔中。IC 202通过结合剂206粘合到T形铜块204。引线接合208将IC202电连接到PCB 200。通过应用烧结材料210和烧结技术将铜块204粘合到PCB 200。烧结可以是低温烧结(例如约200℃)，并且可以在加压条件下或在非加压条件下进行。烧结将PCB200电连接到铜块204，但是在比传统焊接工艺更低的温度下进行。另外或替代地，有可能在较高温度下烧结并且仍体验到本公开的益处，因为在后续处理步骤(例如回流焊接)中烧结将不会熔化。还通过已经被施加到PCB 200的底侧上的输入/输出(I/O)焊盘214的烧结材料将铜柱212烧结到所述I/O焊盘214。
应理解，可以通过导热和/或导电粘合剂将IC 202粘合到铜块204。替代地，也可以使用与将铜块204烧结到PCB 200时所使用材料相同或不同的材料将IC 202烧结到铜块204。
烧结材料可以是纳米颗粒烧结材料，或可用于连接电力电子器件制造的其它烧结材料。虽然粘合剂可以用于电子器件制造，但它们的热导率往往低于市售金属互连，因此在形成例如图2A所示的组合件时不太理想。相比之下，基于所采用的材料和工艺结果，烧结具有多个优势。像焊接一样，烧结的最终结果是例如将PCB 200接合到铜块204的固体金属互连，因此具有相对较高的热导率，通常比使用粘合剂所获得的热导率高得多。然而，并且对于本申请而言重要的是，与焊接或粘合剂不同，互连在施加热量时将不容易回流。因此，在后续将表面安装装置(SMD)连接到PCB 200的表面安装技术(SMT)工艺期间，烧结连接不会熔化。烧结的这一方面使得PCB的多步骤处理更容易实现，因为可以随时制造衬底(例如，PCB 200和铜块204)，并且可以进行后续的SMT工艺而不必担心损坏PCB与铜块的互连。
图2B描绘了烧结到平坦铜块204的PCB 200的类似构造。与图2A中的T形铜块204不同，平坦铜块204使图2B中的组合件的整体厚度尺寸与图2A中的相同，尽管图2B中的IC 202明显更厚。
图2C描绘了堆叠封装组合件216，其中第二PCB 218电连接到图2B的PCB 200。尽管在图2C中未示出，但是通常将使用模制技术来包封PCB 200以保护IC 202。模铸通孔(也未示出)也可以是堆叠封装结构的一部分，以有助于两个PCB的互连。最后，可以根据需要包封整个组合件，以加强组合件并帮助维持组件的正确定位。
图3A描绘了本公开的另一方面，其使用倒装芯片设计中的烧结材料310采用烧结将铜块304连接到PCB 300以形成倒装芯片组合件316。如本领域中已知的，倒装芯片设计的使用进一步促进了整体组合件大小的缩减。这是通过将IC 302连接到PCB 300的一侧同时可以将其它电子组件添加到PCB 300的第二侧(例如，使用SMT工艺)来实现的。如上所述，使用例如粘合剂之类的结合剂306或其它技术将IC 302热连接到铜块304，并使用例如球栅阵列320或替代图2A到2C的实例中的引线接合208的其它合适的技术将IC 302连接到PCB200。图3A的铜块304具有T形。
再次在图3A中，还使用已经被施加到PCB 300的底侧上的输入/输出(I/O)焊盘314的烧结材料将铜柱312烧结到所述I/O焊盘314。如图3A中所描绘，PCB 300具有空腔322，而非具有延伸穿过PCB 200(图2A)的孔201。凹口接收IC 302并允许连接到PCB 300。铜块304有效地提升了IC 302，以确保在空腔322中与PCB 300接触。铜块304可以是任何形状，包含在图2A中示出的T形或图3A中示出的平坦形状。
图3B描绘了图3A的倒装芯片设计的替代方案，其中PCB 300没有空腔322。因此，可以采用附加的铜柱312并将其连接到铜块304。
图4是根据本公开的用于制造倒装芯片组合件的流程图。作为第一步骤402，制造衬底(例如，PCB 300)并将其接收在组装系统中。在步骤404，将空腔322布设到PCB 300中。空腔322的大小和形状设计成可接收IC 302，并且在采用T形铜块(例如，图2A中的204)的情况下，接收铜块的至少一部分。如将了解，空腔322的布设可以在PCB制造期间发生，使得在步骤402中所接收的PCB已经在其中加工了空腔。在步骤406，可以使用SMT将PCB 300的第二侧上与IC 302将要连接的一侧相对的组件机械地且电性地连接到PCB 300。
接下来在步骤408，可以将IC 302施加到PCB 300并电连接到PCB 300。在将IC 302连接到PCB 300之后，可以在步骤410对IC进行底部填充。底部填充是将包封剂和粘合剂施加到IC 302的底侧(连接到PCB 300的侧)的步骤。底部填充材料填充了PCB 300和IC 302的互连之间的间隙，保护了电连接(例如，球栅阵列320)，并将IC 302进一步固定到PCB 300。在步骤410进行底部填充之后，在步骤412将铜块304烧结到PCB 300。步骤412包含将烧结材料施加到期望的位置，并且施加压力以将那些材料融合在一起并将它们结合到铜块304和PCB 300两者。这也可以包含施加热量以帮助将烧结材料(通常为颗粒形式)转变为固体，并且可以在真空条件下执行以防止腐蚀。此外，此步骤可以包含铜块304或铜柱312所需的任何附加准备。
烧结之后，在步骤414将铜块304研磨至期望的厚度，并进行精加工以去除任何不期望的材料。最后，在步骤416，可以从同时形成在较大片材中的一组PCB中分离出单个PCB300。例如，可以一次在同一衬底上制造100个单独的PCB。尽管形成在同一衬底上(例如，准备接收100个IC 302和100个铜块304的PCB)，但是可以使用切割锯、激光切割机和其它技术切割此同一衬底，以分离单个PCB 300用作较大系统的电子组件。
图5描绘了形成图2A或2B的PCB 200的过程。再次，过程通过在步骤502接收PCB200开始。如上所述，并且结合分离步骤518，PCB 200可以是被设计成接收任意数量(例如100个)的IC 202和铜块204的衬底。接着，将开口(孔201或空腔322)布设到PCB 200中。
在步骤506，将铜块204烧结到PCB 200。如上所述，步骤506包含将烧结材料施加到期望的位置，并且施加压力以将那些材料融合在一起并将它们结合到铜块204和PCB 200两者。这也可以包含施加热量以帮助将烧结材料(通常为颗粒形式)转变为固体，并且可以在真空条件下执行以防止腐蚀。此外，此步骤可以包含铜块204或铜柱212所需的任何附加准备。
一旦烧结了PCB 200和铜块204，就可以在步骤508进行电气和电子组件的表面安装。在SMT之后，可以将IC 202附接到铜块204。如上所述，这可以通过使用导热粘合剂或本文描述的其它技术或所属领域的技术人员已知的技术来实现。然后，在步骤512通过将IC202引线接合到PCB上的触点来将IC 202电连接到PCB。在引线接合之后，可以包覆模制整个PCB 200(例如，用包封剂覆盖)以保护电气和电子组件、用于引线接合的引线和IC 202。
在步骤516进行包覆模制之后，可以将铜块的铜研磨掉，并进行表面加工以从其表面去除任何不希望的材料。最后，在步骤518，如上所述，可以从同时形成在较大片材中的一组PCB中分离出单个PCB 200。
虽然已在附图中示出了本公开的几个实施例，但是并不意图将本公开限于这些实施例，因为希望本公开具有如本领域将允许的广泛的范围且对说明书的理解也是如此。还设想以上实施例的任何组合，且所述组合在要求保护的发明的范围内。因此，上文的描述不应解释为限制性的，而仅仅是作为特定实施例的例证。所属领域的技术人员将设想在本文所附的权利要求书的范围和精神内的其它修改。

Claims (20)

1.一种制造电子组件的方法，其包括：
将电子组件表面安装到印刷电路板PCB；
将倒装芯片集成电路IC施加到所述PCB；
对所述倒装芯片IC进行底部填充以固定所述PCB；以及
将铜块烧结到所述PCB，其中所述铜块与所述IC热连通，并充当去除由所述倒装芯片IC产生的热量的热路径。
2.根据权利要求1所述的方法，其进一步包括在所述PCB中布设空腔以接收所述倒装芯片IC。
3.根据权利要求1所述的方法，其中通过热结合剂将所述铜块热连接到所述倒装芯片IC。
4.根据权利要求1所述的方法，其进一步包括研磨所述铜块的背侧以进行表面加工。
5.根据权利要求1所述的方法，其中所述铜块为T形。
6.根据权利要求1所述的方法，其中所述铜块是平坦的。
7.根据权利要求1所述的方法，其中所述烧结是低温烧结。
8.根据权利要求7所述的方法，其中在压力下执行所述低温烧结。
9.根据权利要求1所述的方法，其进一步包括将所述PCB分离以隔离单个电子组件。
10.根据权利要求1所述的方法，其进一步包括将铜柱烧结到所述PCB并将所述铜块连接到所述铜柱。
11.一种制造电子组件的方法，其包括：
布设印刷电路板PCB以形成开口；
将铜块烧结到所述PCB，使得所述铜块布置在所述开口中；
将电子组件表面安装到所述PCB；
将集成电路IC附接到所述铜块；
将所述IC引线接合到所述PCB；以及
包覆模制所述PCB。
12.根据权利要求11所述的方法，其进一步包括研磨所述铜块的背侧以进行表面加工。
13.根据权利要求11所述的方法，其中所述开口是穿过所述PCB的孔。
14.根据权利要求11所述的方法，其中所述开口是所述PCB中的空腔。
15.根据权利要求11所述的方法，其中通过热结合剂将所述铜块热连接到所述IC。
16.根据权利要求11所述的方法，其中所述铜块为T形。
17.根据权利要求11所述的方法，其中所述铜块是平坦的。
18.根据权利要求11所述的方法，其中所述烧结是低温烧结。
19.根据权利要求18所述的方法，其中在压力下执行所述低温烧结。
20.一种电子组件，其包括：
印刷电路板，其包含在其中形成的开口；
集成电路IC，其放置在所述开口中并连接到所述印刷电路板；以及
铜块，其热连接到所述IC且烧结到所述PCB。
CN201911019157.8A 2019-10-24 2019-10-24 电子组件及制造电子组件的方法 Pending CN112714539A (zh)

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