TW201230286A - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
TW201230286A
TW201230286A TW100132479A TW100132479A TW201230286A TW 201230286 A TW201230286 A TW 201230286A TW 100132479 A TW100132479 A TW 100132479A TW 100132479 A TW100132479 A TW 100132479A TW 201230286 A TW201230286 A TW 201230286A
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TW
Taiwan
Prior art keywords
substrate
semiconductor device
control element
disposed
passive component
Prior art date
Application number
TW100132479A
Other languages
Chinese (zh)
Inventor
Yuji Karakane
Yoriyasu Ando
Original Assignee
Toshiba Kk
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Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201230286A publication Critical patent/TW201230286A/en

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    • H—ELECTRICITY
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Abstract

According to an embodiment, a semiconductor device includes a substrate, a control element provided on the substrate, a resin provided on the control element and a memory element provided above the control element. The memory element is in contact with the resin and electrically connected to the control element provided within a region therebeneath in plan view parallel to a surface of the substrate.

Description

201230286 六、發明說明： 【發明所屬之技術領域】 本發明之實施形態係關於一種半導體裝置及其製造方 法。 本申請案係基於且主張2010年12月17日申請的先前日本 專利申請案第201 0-28 1844號之優先權的權利；該案之全 部内容以引用之方式併入本文中。 【先前技術】 先别，一種將複數個記憶元件與控制元件配置於一個封 裝中之半導體裝置被廣泛普及，且求得半導體記憶裝置之 大谷量化與便利性之提升。另一方面，該等之半導體裝置 之用途亦有所擴大，為使其亦可搭載於如可攜式終端之小 型機器上’而期望封裝尺寸之小型化。 若在作為封裝基底之基板上，平面地佈置記憶元件、控 制元件及各種被動零件，則必然會使封裝尺寸變大。因 此，設法將料之半導心件及零件立體配置。例如，可 在晶片尺寸較大之記憶元件上搭載控制元件。 热叫，牛導體元件 «况工甘>r至叫艰。例如 會使將配置於記憶元件上之㈣元件、與設置於基板上 外部端子之間電性連接的金屬線變長，無法傳送高頻 號。又，亦存在需要用以將控制元件連接於外部 他中繼元件，而提高製造成本之情形。因此，謀求 提高高頻特性’小型且低成本之半導體裝置。 【發明内容】 158624.doc 201230286 造明之實施形態係提供一種小型之半導體裝置及其製 本發明之實施形態之半導體I置，其特徵在於具備··基 板’及配置於上述基板上之控制元件。且包含：覆蓋上述 控制元件之樹脂；及配置於上述控制元件上，連接於上述 樹脂，並藉由上述控制元件予以控制之記憶元件；自上方 俯視，上述控制元件係配置於上述記憶元件之正下方區 ^ ° 00 種小型之半導體裝置 根據本發明之實施形態，可提供一 及其製造方法。 【實施方式】 以下，就本發明之實施形態一面參照圖面—面予以說 明。另，以下實施形態中，圖面中相同之部分使用相同符 號且適當省略其詳細說明，就不同部分予以適當說明。 (第1實施形態） 圖1係顯示第1實施形態之半導體裝置1〇〇之剖面之模式 圖。此處所例示之半導體裝置100係收容於所謂bga(b& Grid Array :球柵陣列）型之半導體封裝中之半導體記情裝 置〇 又 半導體裝置100具備：記憶元件50A〜5〇c、控制元件 20、及被動零件30。 a己憶元件50A〜50C為例如NAND型快閃記憶體。抑制_ 件20為记憶體控制器’其控制記憶元件5〇a〜50C之動作 被動零件30為電阻及電容等之電路零件。此處，自上方俯 158624.doc 201230286 視之面積以記憶元件50A〜50C為最大》 如圖1所示，半導體裝置1〇〇包含：基板10、配置於基板 10上之控制元件20、及配置於基板1〇上之被動零件3〇。 控制元件20係經由設置於背面之接著層21而安裝於基板 1〇之表面l〇a。且’控制元件20之電極焊墊23與設置於基 板10之表面10a之連接端子17之間，係藉由金屬線22電性 連接。 被動零件30被焊錫固定於基板1〇之表面i〇a，同時連接 設置於基板10之表面l〇a之布線（未圖示）。 再者’控制元件20與被動零件30被絕緣性樹脂40覆蓋。 且’記憶元件50A係連接於絕緣性樹脂40而配置於控制元 件20及被動零件30上。 s己憶元件50A〜50C如圖1所示，係以露出電極焊墊5 j之 方式錯開位置成階梯狀積載。且’設置於一方之端之電極 焊墊51A〜51C與設置於基板1〇之表面1〇a之連接端子18之 間，係藉由金屬線52連接。此處’自上方俯視，於記憶元 件50A〜50C之正下方區域内配置有控制元件2〇及被動零件 30。即’可將半導體記憶裝置小型化。 連接子17及18經由形成於基板1〇之内部之布線層（未 圖示）而電性連接於設置於基板10之背面l〇b之焊球15。 且，焊球15連接於外部電路，並將記憶元件5〇A〜5〇c及控 制元件20、與外部電路之間電性連接。此處，藉由將被動 零件30配置於基板1〇上，可縮短被動零件3〇與輸入外部信 號之焊球15之間的距離。其結果，可有效地去除雜訊。 158624.doc 201230286 連接端子17與連接端子18之間係藉由設置於基板⑺之表 面10a之布線（未圖示）而電性連接，且控制元件2〇係控制庀 憶元件50A〜50C。 ° 再者，記憶元件50A〜50C及控制元件2〇、被動零件係 • 被密封樹脂60覆蓋，對外界密封。 ’、 ‘ 其次，參照圖2至圖5說明半導體裝置1〇〇之製造過程。 如圖2(a)所不，於基板1〇之表面1〇a安裝被動零件。具 體而言，於配置被動零件30之表面10a之特定位置印刷焊 錫膏。且，將被動零件30載置於焊錫膏上並以回焊方式焊 踢黏合。 基板10可使用例如包含多層布線之環氧玻璃基板。 其次，如圖2(b)所示，將控制元件20安裝於基板1〇之表 面1 0 a。在控制元件2 〇之背面，例如設置有包含環氧樹脂 等熱硬化性樹脂之接著層21，可將控制元件2〇壓接於表面 10a。再者’藉由加熱基板1〇使接著層21硬化而固定控制 元件20。 且’如圖2(c)所示’藉由金屬線22將控制元件2〇之電極 焊墊23與連接端子17之間連接。 • 如此’藉由使用金屬線22連接將端子17與電極焊墊23之 : 間連接’可任意選擇控制元件20之種類《例如，在未使用 金屬線之所謂覆晶型之控制元件中，須使電極焊墊之間隔 與連接端子1 7之間隔一致。因此，基板需使用對應於控制 元件之專用基板或適合特定規格之基板。 又’在所謂覆晶型之控制元件中，須使電極焊墊之間距 158624.doc 201230286 與形成於基板l 〇之内部之布線層之間距相符。因此，無法 配置電極焊墊間距短的控制元件。特別是控制記憶元件之 控制元件20 ’須使用電極焊墊23之間距較基板1〇之布線層 之間距更短者。而如本實施形態，藉由使用金屬線22連接 連接端子17與電極焊墊23之間，可配置電極焊墊23之間距 較基板10之布線層之間距更短之控制元件2〇。 其次’如圖3(a)所示’將記憶元件50Α安裝於基板10之 表面10a。於記憶元件50Α之背面上設置有樹脂層40a。樹 脂層40a例如含有熱硬化性之環氧樹脂，其彈性模數小而 柔軟，可設置為所謂B-階段之狀態（半硬化狀態）。 因此，如圖3(b)所示，記憶元件50A係將控制元件20及 被動零件30包入於樹脂層40a而安裝於基板1〇。此時，因 樹脂層40a柔軟’故可抑制連結控制元件2〇之電極焊墊23 與連接端子17之金屬線22變形。 其次，加熱基板1 〇，形成使覆蓋控制元件2〇及被動零件 30之樹脂層40a硬化之絕緣性樹脂40 »其結果，記憶元件 50A係在控制元件20及被動零件30上，以毗連於絕緣性樹 脂40之狀態固定。而於記憶元件5〇A上可積載記憶元件 50B及 50C。 樹脂層40a例如可藉由將DAF(Die Attach Film晶粒附著 膜）黏貼於設置有記憶元件50A之半導體晶圓之背面而形 成。又’亦可藉由於半導體晶圓之背面塗布含熱硬化性樹 脂之接著劑並使其乾燥而形成。 可將樹脂層40a之硬化前黏度設為例如1〜loooo pa· s， 158624.doc 201230286 將硬化後之彈性模數設為例如〗〜〗〇〇〇 MPa» 其次，如圖4(a)所示，依序安裝記憶元件50B及5〇c。於 記憶元件50B及50C之背面設置有接著層43，其可分別貼 合於記憶元件50A之表面、及記憶元件50B之表面。 繼而’如圖4(b)所示，將記憶元件5〇A〜50C以使設置於 其各自之一端之電極焊墊51A〜5 1C露出之方式成階梯狀積 載。 其次’藉由加熱基板1〇使接著層43硬化，使階梯狀積載 之記憶元件50A〜50C固定。且，以金屬線52連接電極焊墊 51A〜51C與連接端子18之間。 繼而’如圖5所示’將密封樹脂6〇成形於基板1〇上，並 將記憶元件50A〜50C及控制元件2〇、被動零件30樹脂密 封。然後，於基板1 0之背面側附設焊球丨5即可完成半導體 裝置100。 上述半導體裝置100中，控制元件20及被動零件30立體 配置於記憶元件50A之下。藉此，可實現依存於記憶元件 尺寸之最小的封裝尺寸。另一方面’可將連接控制元件2〇 之電極焊墊23與設置於基板1〇之表面1〇a之連接端子17之 間的金屬線22縮短，而亦可抑制高頻特性之劣化。 再者，使用設置於記憶元件50A之背面之樹脂層4〇a，可 形成覆蓋控制元件20及被動零件3〇之絕緣性樹脂4〇，故可 簡化半導體裝置100之構成。 圖6係顯示第1實施形態之變形例之半導體裝置1 1 〇之剖 面之模式圖。半導體裝置110在以金屬線32連接被動零件 158624.doc 201230286 3〇之電極33與設置於基板10之布線19之間之點上，有別於 圖1所示之半導體裝置100。例如為提高與金屬線之密著 性’於被動零件30之電極33上宜實施金屬鍍敷。 如此’藉由將被動零件30之電性連接手段變為金屬線 32’可省略尚溫之回焊步驟。再者，因可在與控制元件2〇 相同之組裝步驟中實施引線接合，故可簡化製造步驟。 圖7係顯示第1實施形態之另一變形例之半導體裝置12〇 之剖面之模式圖。半導體裝置120,在於覆蓋控制元件2〇 及被動零件30之絕緣性樹脂45上安裝記憶元件50A此點上 有別於圖1所示之半導體裝置記憶元件5〇a與積載於 其上^又之记憶元件50B及5 0C相同’具備設置於背面之接 著層43，可黏貼於絕緣性樹脂45上。 即’本變形例之半導體裝置120，預先將覆蓋控制元件 20及被動零件30之絕緣性樹脂45成形，並於其上安裝記憶 元件50A。記憶元件50A係經由設置於背面之接著層43而 與絕緣性樹脂45連接。 半導體裝置120中’無須在記憶元件50A之背面上設置厚 的樹脂層40a(參照圖3(a)) ’故可謀求製造步驟之簡化。 (第2實施形態） 圖8係顯示第2實施形態之半導體裝置2〇〇之剖面之模式 圖。 如圖8所示’半導體裝置200’在於基板70之内部配置有 被動零件30此點上有別於圖1所示之半導體裝置丨〇〇。 基板70具有在第1基底71與第2基底75之間將絕緣層72與 158624.doc -10- 201230286 布線層73交互積層之多層構造。例如，第1基底71與第2基 底7 5係環氧玻璃基板》絕緣層7 2可使用將烯碳織維等添加 於環氧樹脂而複合成形之絕緣膜。 又’第1基底71與第2基底75之間配置有複數個布線層 73。該布線層73可使用銅箔。位於上下之布線層73之間係 藉由凸塊74電性連接，且將設置於第2基底之表面75&上之 布線（未圖示）與附設於第1基底之背面71b之焊球15之間電 性連接。該布線層73及凸塊74係例如藉由熱壓接而一體 化。另，代替使用布線層73與凸塊74之方法，亦可於基板 7〇中形成貫通第1基底71與第2基底75之間之通孔，且於該 通孔中形成導電體，並將設置於第2基底之表面75a上之布 線與附設於第1基底之背面71 b之焊球15之間電性連接。 第2基底之表面75a之布線係連接於連接端子I?及μ，且 將控制元件20及記憶元件50A〜C與焊球15電性連接。 另一方面，被動零件30係内建於第！基底71與第2基底75 之間且，經由5又置於第1基底71之表面之布線79與布線 層73 ’而連接於設置於第2基底75表面之布線。且，在第i 基底71與第2基底75之間，以覆蓋布線層73、凸塊74及被 動零件30之方式配置絕緣層72並藉由熱壓接而一體化。 例如，如圖8所示，被動零件3〇係焊接於第！基底上，並 電性連接於布線79。 如圖8所示，第2基底75上安裝有控制元件2〇，控制元件 2〇之電極焊墊23係經由金屬線22而電性連接於配置在第2 基底75&上之連接端子17。控制元件2〇被絕緣性樹脂4〇覆 158624.doc 201230286 蓋，連接於絕緣性樹脂40並配置有記憶元件50Αβ且，記 憶元件50Α上積載有記憶元件5〇β及5〇c。 本貫施形態之半導體裝置2〇〇中，記憶元件5〇α係配置於 控制元件2 0及被動零件3 〇上’可謀求封裝尺寸之小型化。 且’控制元件20之電極焊墊23與設置於第2基底之表面75 a 之布線之一部分之接線端子17之間，係以短金屬線22連 接’可抑制高頻特性之劣化。又，藉由將控制元件2〇之電 極焊塾23電性連接於位於基板77之最上層之第2基底75a， 可縮短§£>憶元件50A與控制元件20之布線距離。其結果， 可高速進行半導體裝置200之動作。 再者，由於被動零件3〇係内建於基板70，故可簡化半導 體裝置200之組裝步驟，並減低製造成本。又，藉由將被 動零件30配置於第1基底71上，可縮短被動零件3〇與輸入 外部信號之焊球15之距離。其結果，可有效地去除雜訊。 又’如圖8所示’亦可將控制元件2〇内建於基板7〇，從 而可進一步簡化組裝步驟。 然而’將作為主動元件之控制元件2〇内建於基板7〇，有 成為使半導體裝置2〇〇之成品率降低且製造成本提高之主 要原因之情形。例如，當控制元件2〇在基板7〇之製造過程 中發生故障時，該異常只有在安裝記憶元件50A〜50C後進 行的製品檢查中得到確認。因此，有記憶元件5〇A〜5〇c及 其安裝成本造成浪費之虞。 再者’在基板70之製造過程中，若使用電場電鍍法形成 布線’則有電流流動於控制元件20致使其故障之虞。因 158624.doc -12- 201230286 此，雖有必要代替電場電鍍法，使用無電場電鍍法，但無 電場電鍍法成本高，又會產生基板70之製造成本增加之問 題。 對此，本實施形態之半導體裝置2〇〇，係將被動零件3〇 ' 内建於基板70中，將控制元件20安裝於基板70上。因此， • 基板之布線可使用電場電鑛法形成。且，被.動零件30幾 乎不會在基板70之製造過程中發生故障，故無須擔心成品 率降低。 圖9係顯示第2實施形態之變形例之半導體裝置2 1 〇之剖 面之模式圖。半導體裝置210，與圖8所示之半導體裝置 200相同，係將被動零件30配置於基板77之内部。另一方 面，將控制元件20配置於設置於基板77之凹部80之底面81 此點有別於半導體裝置200。 如圖9所示’控制元件20係藉由埋入凹部80之絕緣性樹 脂40覆蓋。又，控制元件20之電極焊墊23係以金屬線22連 接於第2基底78之連接端子17。且’記憶元件50A係配置於 内建在基板77中之被動零件30及控制元件20上，且連接安 裝於絕緣性樹脂40。絕緣性樹脂40如圖3(a)所示，可藉由 • 在記憶元件50A之背面設置樹脂層40而形成。 : 如圖9所示，凹部8 0係自設置於第2基底7 8之開口朝第1 基底71之方向形成。且，可將凹部80之深度設置為較控制 元件20之厚度更深。又，連接端子17係設置於第2基底78 之絕緣層72之相反側之表面的凹部80之開口周圍。 第2實施形態之變形例之半導體裝置210具有與第2實施 158624.doc • 13- 201230286 形態相同之效果。_，藉由將控制元件20之電極焊墊23電 性連接於位於基板77之最上層之第2基底仏，可縮短記憶 兀件50A與控制元件20之布線距離。其結果可使半導體 裝置200高速地進行動作。再者，半導體裝置2ι。中，由於 控制元件20係配置於基板77之凹部，故與圖8所示之半導 體裝置200相比，可減小封裝之厚度。 圖10係顯示第2實施形態之另一變形例之半導體裝置22〇 之剖面之模式圖。半導體裝置220，將被動零件3〇内建於 基板77中，且將控制元件2〇配置於設置在基板”中之凹部 80此點上’與圖9所示之半導體裝置21〇相同。 另一方面，半導體裝置22〇中，凹部8〇之内部係以絕緣 性樹脂45填埋，且控制元件2〇被絕緣性樹脂45覆蓋。且， 在將s己憶元件50A連接安裝於絕緣性樹脂45此點上有別於 半導體裝置210。記憶元件50A具有設置於背面之接著層 4 7 ’經由接著層4 7而黏貼於絕緣性樹脂4 5上。 圖11係顯示半導體裝置220之製造過程之一部分之模式 剖面圖。 首先’準備内建有被動零件80之基板77。其後，形成露 出第1基底71之上表面之凹部80。 如圖11(a)所示’於設置於基板77中之凹部80之底面 81(第1基底71之上表面）上安裝控制元件20。控制元件2〇之 背面設置有例如含熱硬化性樹脂之接著層21，可使其壓接 於凹部80之底面81。且，藉由加熱基板77使接著層21硬 化，可使控制元件20固定黏著於凹部80之底面81。 I58624.doc 14 201230286 其次，使用金屬線22連接控制元件2〇之電極焊墊23與設 置於基板77之表面77a上之連接端子17。另，第作施形態 之變形例，可藉由之後經過圖3至圖5之步驟而製造。其 後，於凹部80之内部填充絕緣性樹脂45。絕緣性樹脂化可 使用例如熱硬化性之環氧樹脂。環氧樹脂可使用擴散至丫_ 丁内酯等溶劑中之低黏度者。藉此，可抑制金屬線22之變 形及產生氣孔，可均一地填充凹部8〇之内部。 其次，加熱基板77蒸散溶劑，且使環氧樹脂硬化。 其次，如圖11(b)所示，於控制元件2〇及被動零件3〇上安 裝記憶元件50A。 記憶元件50A之背面，例如設置有B_階段之接著層47， 可將其役者黏貼於絕緣性樹脂4 5之表面。接著層4 7可塗布 例如熱硬化性樹脂而形成。又，亦可黏貼DAF » 再者，如圖10所示，可積載記憶元件5〇Β及50C。設置 於記憶元件50Β及50之背面之接著層43、與設置於記憶元 件50Α之接著層47可為相同者，亦可令接著層47厚於接著 層43 〇 第2實施形態之變形例之另一例之半導體裝置220具有與 第2實施形態相同之效果。再者，如上所述，可降低覆蓋 控制元件20之絕緣性樹脂45填充時之黏度，抑制控制元件 20之金屬線22之變形，且抑制凹部80之内部產生氣孔。 且，填埋凹部80之絕緣性樹脂45，與黏貼記憶元件50A 之接著層47係單獨設置。因此，如圖9所示之半導體裝置 210，無須使用設置於記憶元件50A之背面上之樹脂層填埋 158624.doc 201230286 凹部80，可僅作為薄的接著層47。藉此，可使用與積載於 上段之記憶元件50B及5〇C相同之接著層，故能夠簡化記 憶元件50A之製造過程。 (第3實施形態） 圖12係顯示第3實施形態之半導體裝置300之剖面之模式 圖。半導體裝置300在未形成有被動零件30此點上有別於 第1實施形態。在該實施形態中亦可獲得與第1實施形態相 同之效果。 (第4實施形態） 圖13係顯示第4實施形態之半導體裝置400之剖面之模式 圖。半導體裝置400在未形成有被動零件30此點上有別於 第2實施形態。在該實施形態中亦可獲得與第2實施形態相 同之效果。 以上’雖已說明第1及第4實施形態之半導體裝置，但實 施形態並不限定於此。例如’搭載於半導體裝置之記憶元 件之數目不限定3個’可積載3個以上之記憶元件，亦可3 個以下。 雖然已說明本發明之數個實施形態，但該等實施形態僅 係作為實例而提出，並非意欲限制本發明之範疇。該等之 新賴實施形態可以其他各種形態實施，在不脫離發明之主 旨之範圍内，可作出各種省略、替代及變更。隨附申請專 利範圍及其之荨效物意欲涵蓋此等形式或修改，如同此等 形式或修改落在本發明之範疇及精神内一般。 【圖式簡單說明】 i58624.doc 16 201230286 圖1係顯示第1實施形態之半導體裝置之剖面之模式圖。 圖2(Α)·(〇係顯示第1實施形態之半導體裝置之製造過程 之模式剖面圖。 圖3(A)、（B)係顯示接續圖2之半導體裝置之製造過程之 模式剖面圖。 圖4(A)、（B)係顯示接續圖3之半導體装置之製造過程之 模式剖面圖。 圖5係顯示接續圖4之半導體裝置之製造過程之模式剖面 圖。 圖6係顯示第1實施形態之變形例之半導體裝置之剖面之 模式圖。 圖7係顯示第1實施形態之另一變形例之半導體裝置之剖 面之模式圖。 圖8係顯示第2實施形態之半導體裝置之刮面之模式圖。 圖9係顯示第2實施形態之變形例之半導體裝置之剖面之 模式圖。 圖10係顯示第2實施形態之另一變形例之半導體裝置之 剖面之模式圖。 圖11(A)、（B)係顯示第2實施形態之變形例之半導體裝 置之製造過程之模式剖面圖。 圖12係顯示第3實施形態之半導體裝置之剖面之模式 圖。 圖13係顯示第4實施形態之半導體裝置之剖面之模式 圖0 158624.doc -17- 201230286 【主要元件符號說明】 10 基板 10a 表面 10b 背面 15 焊球 17 連接端子 18 連接端子 19 布線 20 控制元件 21 接著層 22 金屬線 23 電極焊墊 30 被動零件 32 金屬線 33 電極 40 絕緣性樹脂 40a 樹脂層 43 連接層 45 絕緣性樹脂 50A 記憶元件 50B 記憶元件 50C 記憶元件 51A 電極焊墊 51B 電極焊墊 158624.doc -18 201230286 51C 電極焊墊 52 金屬線 60 密封樹脂 70 基板 71 第1基底 72 絕緣層 73 布線層 74 凸塊 75 第2基底 75a 第2基底 77 基板 78 第2基底 79 布線 80 凹部 81 底面 100 半導體裝置 110 半導體裝置 120 半導體裝置 200 半導體裝置 210 半導體裝置 220 半導體裝置 300 半導體裝置 400 半導體裝置 158624.doc •19201230286 VI. Description of the Invention: TECHNICAL FIELD Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same. The present application is based on and claims the benefit of priority to Japanese Patent Application Serial No. PCT--------- [Prior Art] In the prior art, a semiconductor device in which a plurality of memory elements and control elements are arranged in one package is widely used, and the quantization and convenience of the semiconductor memory device are improved. On the other hand, the use of such semiconductor devices has also been expanded, and it is desired to be mounted on a small device such as a portable terminal. If the memory element, the control element, and various passive parts are arranged in a planar manner on the substrate as the package substrate, the package size is inevitably increased. Therefore, try to arrange the semi-conducting core and parts of the material in three dimensions. For example, a control element can be mounted on a memory element having a large wafer size. Hot call, cattle conductor components «condition workers Gan" r tough. For example, the (four) element placed on the memory element and the metal line electrically connected to the external terminal provided on the substrate are lengthened, and the high frequency number cannot be transmitted. Moreover, there is also a need to increase the manufacturing cost by connecting the control element to the external relay element. Therefore, it is desired to improve the high-frequency characteristics of a small-sized and low-cost semiconductor device. According to the embodiment of the invention, there is provided a small-sized semiconductor device and a semiconductor device according to an embodiment of the present invention, comprising: a substrate; and a control element disposed on the substrate. And comprising: a resin covering the control element; and a memory element disposed on the control element and connected to the resin and controlled by the control element; wherein the control element is disposed on the memory element from a top view The lower area ^ 00 small semiconductor device according to an embodiment of the present invention can provide a method of manufacturing the same. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same portions are denoted by the same reference numerals, and the detailed description thereof will be appropriately omitted, and the different portions will be appropriately described. (First Embodiment) Fig. 1 is a schematic view showing a cross section of a semiconductor device 1 according to a first embodiment. The semiconductor device 100 exemplified herein is a semiconductor sensible device housed in a so-called bGA (battery grid array) type semiconductor package, and the semiconductor device 100 includes memory elements 50A to 5〇c and a control element 20 And passive parts 30. The memory elements 50A to 50C are, for example, NAND type flash memories. The suppression unit 20 is a memory controller. The operation of the control memory elements 5a to 50C is a circuit component such as a resistor or a capacitor. Here, the area is 158624.doc 201230286, and the area of the memory element 50A to 50C is the largest. As shown in FIG. 1, the semiconductor device 1 includes a substrate 10, a control element 20 disposed on the substrate 10, and a configuration. Passive part 3〇 on the substrate 1〇. The control element 20 is mounted on the surface 10a of the substrate 1 via an adhesive layer 21 provided on the back surface. Further, the electrode pad 23 of the control element 20 and the connection terminal 17 provided on the surface 10a of the substrate 10 are electrically connected by a metal wire 22. The passive component 30 is fixed to the surface i〇a of the substrate 1 by soldering, and is connected to a wiring (not shown) provided on the surface 10a of the substrate 10. Further, the control element 20 and the passive component 30 are covered with an insulating resin 40. Further, the memory element 50A is connected to the insulating resin 40 and disposed on the control element 20 and the passive component 30. As shown in Fig. 1, the memory elements 50A to 50C are staggered in a staggered manner so as to expose the electrode pads 5j. Further, the electrode pads 51A to 51C provided at one end are connected to the connection terminals 18 provided on the surface 1a of the substrate 1A by metal wires 52. Here, the control element 2A and the passive component 30 are disposed in a region directly below the memory elements 50A to 50C as viewed from above. That is, the semiconductor memory device can be miniaturized. The connectors 17 and 18 are electrically connected to the solder balls 15 provided on the back surface 10b of the substrate 10 via a wiring layer (not shown) formed inside the substrate 1A. Further, the solder ball 15 is connected to an external circuit, and electrically connects the memory elements 5A to 5C and the control element 20 to an external circuit. Here, by arranging the passive component 30 on the substrate 1 , the distance between the passive component 3 〇 and the solder ball 15 to which the external signal is input can be shortened. As a result, noise can be effectively removed. 158624.doc 201230286 The connection terminal 17 and the connection terminal 18 are electrically connected by a wiring (not shown) provided on the surface 10a of the substrate (7), and the control element 2 controls the memory elements 50A to 50C. Further, the memory elements 50A to 50C, the control element 2, and the passive component are covered by the sealing resin 60 and sealed to the outside. ‘, ‘ Next, the manufacturing process of the semiconductor device 1 说明 will be described with reference to FIGS. 2 to 5 . As shown in Fig. 2(a), a passive component is mounted on the surface 1〇a of the substrate 1〇. Specifically, the solder paste is printed at a specific position on the surface 10a where the passive component 30 is disposed. Further, the passive component 30 is placed on the solder paste and soldered and bonded by reflow soldering. As the substrate 10, for example, an epoxy glass substrate including a plurality of layers of wiring can be used. Next, as shown in Fig. 2(b), the control element 20 is mounted on the surface 10 a of the substrate 1 . On the back surface of the control element 2, for example, an adhesive layer 21 containing a thermosetting resin such as an epoxy resin is provided, and the control element 2 is press-bonded to the surface 10a. Further, the control element 20 is fixed by heating the substrate 1 to harden the adhesive layer 21. And, as shown in Fig. 2(c), the electrode pad 23 of the control element 2 is connected to the connection terminal 17 by the metal wire 22. • The type of the control element 20 can be arbitrarily selected by connecting the terminal 17 and the electrode pad 23 by using a metal wire 22: "For example, in a so-called flip chip type control element in which a metal wire is not used, The interval between the electrode pads is made to coincide with the interval between the connection terminals 17. Therefore, the substrate needs to use a dedicated substrate corresponding to the control element or a substrate suitable for a specific specification. Further, in the so-called flip-chip type control element, the distance between the electrode pads 158624.doc 201230286 and the wiring layer formed inside the substrate 须 must be made to match. Therefore, it is not possible to configure a control element with a short electrode pad pitch. In particular, the control element 20' for controlling the memory element must use a shorter distance between the electrode pads 23 than the wiring layer of the substrate. On the other hand, in the present embodiment, by connecting the connection terminal 17 and the electrode pad 23 by using the metal wire 22, the control element 2A having a shorter distance between the electrode pads 23 and the wiring layer of the substrate 10 can be disposed. Next, the memory element 50 is mounted on the surface 10a of the substrate 10 as shown in Fig. 3(a). A resin layer 40a is provided on the back surface of the memory element 50A. The resin layer 40a contains, for example, a thermosetting epoxy resin having a small elastic modulus and a so-called B-stage state (semi-hardened state). Therefore, as shown in Fig. 3 (b), the memory element 50A is mounted on the substrate 1 by enclosing the control element 20 and the passive component 30 in the resin layer 40a. At this time, since the resin layer 40a is soft, deformation of the metal wire 22 connecting the electrode pad 23 of the control element 2 and the connection terminal 17 can be suppressed. Next, the substrate 1 is heated to form an insulating resin 40 which cures the resin layer 40a covering the control element 2 and the passive component 30. As a result, the memory element 50A is attached to the control element 20 and the passive component 30 to be adjacent to the insulation. The state of the resin 40 is fixed. The memory elements 50B and 50C can be stowed on the memory element 5A. The resin layer 40a can be formed, for example, by adhering a DAF (Die Attach Film) to the back surface of the semiconductor wafer on which the memory element 50A is provided. Further, it may be formed by applying a thermosetting resin-containing adhesive to the back surface of the semiconductor wafer and drying it. The pre-hardening viscosity of the resin layer 40a can be set, for example, to 1 loooo pa·s, 158624.doc 201230286. The elastic modulus after hardening is set to, for example, 〖~〗 〇〇〇 MPa» Next, as shown in Fig. 4(a) The memory elements 50B and 5〇c are sequentially mounted. Adhesive layers 43 are provided on the back surfaces of the memory elements 50B and 50C, which are respectively attached to the surface of the memory element 50A and the surface of the memory element 50B. Then, as shown in Fig. 4 (b), the memory elements 5A to 50C are stacked in a stepped manner so that the electrode pads 51A to 5CC provided at one of the ends thereof are exposed. Next, the bonding layer 43 is cured by heating the substrate 1 to fix the memory elements 50A to 50C stacked in a stepped manner. Further, the electrode pads 51A to 51C and the connection terminal 18 are connected by a metal wire 52. Then, as shown in Fig. 5, the sealing resin 6 is formed on the substrate 1A, and the memory elements 50A to 50C and the control element 2 and the passive component 30 are resin-sealed. Then, the solder ball 5 is attached to the back side of the substrate 10 to complete the semiconductor device 100. In the above semiconductor device 100, the control element 20 and the passive component 30 are three-dimensionally disposed under the memory element 50A. Thereby, the smallest package size depending on the size of the memory element can be realized. On the other hand, the metal wire 22 connecting the electrode pad 23 of the control element 2 and the connection terminal 17 provided on the surface 1A of the substrate 1 can be shortened, and deterioration of high frequency characteristics can be suppressed. Further, by using the resin layer 4a provided on the back surface of the memory element 50A, the insulating resin 4 covering the control element 20 and the passive component 3 can be formed, so that the configuration of the semiconductor device 100 can be simplified. Fig. 6 is a schematic view showing a cross section of a semiconductor device 1 1 according to a modification of the first embodiment. The semiconductor device 110 is different from the semiconductor device 100 shown in Fig. 1 in that a metal wire 32 is connected between the electrode 33 of the passive component 158624.doc 201230286 and the wiring 19 provided on the substrate 10. For example, in order to improve the adhesion to the metal wire, metal plating is preferably applied to the electrode 33 of the passive component 30. Thus, by changing the electrical connection means of the passive component 30 into the metal wire 32', the temperature reflow step can be omitted. Furthermore, since wire bonding can be performed in the same assembly step as the control element 2, the manufacturing steps can be simplified. Fig. 7 is a schematic view showing a cross section of a semiconductor device 12A according to another modification of the first embodiment. The semiconductor device 120 is characterized in that the memory device 50A is mounted on the insulating resin 45 covering the control element 2 and the passive component 30. The semiconductor device memory device 5A is different from the semiconductor device memory device 5A shown in FIG. The memory elements 50B and 50C are the same 'having an adhesive layer 43 provided on the back surface, and can be adhered to the insulating resin 45. In other words, in the semiconductor device 120 of the present modification, the insulating resin 45 covering the control element 20 and the passive component 30 is formed in advance, and the memory element 50A is mounted thereon. The memory element 50A is connected to the insulating resin 45 via an adhesive layer 43 provided on the back surface. In the semiconductor device 120, it is not necessary to provide a thick resin layer 40a (see Fig. 3(a)) on the back surface of the memory element 50A, so that the manufacturing steps can be simplified. (Second Embodiment) Fig. 8 is a schematic view showing a cross section of a semiconductor device 2 according to a second embodiment. As shown in Fig. 8, the 'semiconductor device 200' is different from the semiconductor device shown in Fig. 1 in that a passive component 30 is disposed inside the substrate 70. The substrate 70 has a multilayer structure in which an insulating layer 72 and a 158624.doc -10- 201230286 wiring layer 73 are alternately laminated between the first substrate 71 and the second substrate 75. For example, the first substrate 71 and the second substrate 75-based epoxy glass substrate "insulating layer 7 2" may be an insulating film obtained by adding an olefin carbon woven or the like to an epoxy resin and forming a composite film. Further, a plurality of wiring layers 73 are disposed between the first substrate 71 and the second substrate 75. The wiring layer 73 can use a copper foil. The wiring layers 73 located between the upper and lower layers are electrically connected by the bumps 74, and the wiring (not shown) provided on the surface 75 & of the second substrate and the back surface 71b attached to the first substrate are soldered. The balls 15 are electrically connected. The wiring layer 73 and the bumps 74 are integrated by, for example, thermocompression bonding. Further, instead of using the wiring layer 73 and the bump 74, a through hole penetrating between the first substrate 71 and the second substrate 75 may be formed in the substrate 7A, and a conductor may be formed in the via hole. The wiring provided on the surface 75a of the second substrate is electrically connected to the solder ball 15 attached to the back surface 71b of the first substrate. The wiring of the surface 75a of the second substrate is connected to the connection terminals I? and μ, and the control element 20 and the memory elements 50A to C are electrically connected to the solder balls 15. On the other hand, the passive parts 30 are built in the first! The wiring 79 and the wiring layer 73' which are placed between the substrate 71 and the second substrate 75 via the surface of the first substrate 71 are connected to the wiring provided on the surface of the second substrate 75. Further, between the i-th substrate 71 and the second substrate 75, the insulating layer 72 is disposed so as to cover the wiring layer 73, the bumps 74, and the driven member 30, and is integrated by thermocompression bonding. For example, as shown in Figure 8, the passive part 3 is welded to the first! The substrate is electrically connected to the wiring 79. As shown in Fig. 8, the control element 2 is mounted on the second substrate 75, and the electrode pads 23 of the control element 2 are electrically connected to the connection terminals 17 disposed on the second substrate 75& via the metal wires 22. The control element 2 is covered with an insulating resin 4 158624.doc 201230286, and is connected to the insulating resin 40 and disposed with the memory element 50Αβ, and the memory element 5〇β and 5〇c are stacked on the memory element 50Α. In the semiconductor device 2 of the present embodiment, the memory element 5 〇 α is disposed on the control element 20 and the passive component 3 ’, and the package size can be reduced. Further, the electrode pad 23 of the control element 20 and the terminal 17 of a portion of the wiring provided on the surface 75a of the second substrate are connected by the short metal wire 22 to suppress deterioration of high frequency characteristics. Further, by electrically connecting the electrode pad 23 of the control element 2 to the second substrate 75a located at the uppermost layer of the substrate 77, the wiring distance between the memory element 50A and the control element 20 can be shortened. As a result, the operation of the semiconductor device 200 can be performed at high speed. Furthermore, since the passive component 3 is built in the substrate 70, the assembly steps of the semiconductor device 200 can be simplified and the manufacturing cost can be reduced. Further, by arranging the driven component 30 on the first base 71, the distance between the passive component 3 and the solder ball 15 to which the external signal is input can be shortened. As a result, noise can be effectively removed. Further, as shown in Fig. 8, the control element 2 can also be built in the substrate 7 to further simplify the assembly process. However, the control element 2, which is an active element, is built in the substrate 7A, which is a major cause of lowering the yield of the semiconductor device 2 and increasing the manufacturing cost. For example, when the control element 2 故障 fails during the manufacturing process of the substrate 7 ,, the abnormality is confirmed only in the product inspection performed after the memory elements 50A to 50C are mounted. Therefore, there are memory elements 5〇A~5〇c and their installation costs are wasteful. Further, in the manufacturing process of the substrate 70, if the wiring is formed by the electric field plating method, a current flows to the control element 20 to cause a malfunction. 158624.doc -12- 201230286 Therefore, it is necessary to use the electroless plating method instead of the electric field plating method, but the electroless plating method is expensive, and the manufacturing cost of the substrate 70 is increased. On the other hand, in the semiconductor device 2 of the present embodiment, the passive component 3' is built in the substrate 70, and the control element 20 is mounted on the substrate 70. Therefore, the wiring of the substrate can be formed by electric field electrowinning. Further, the driven member 30 hardly fails in the manufacturing process of the substrate 70, so there is no need to worry about a decrease in yield. Fig. 9 is a schematic view showing a cross section of a semiconductor device 2 1 according to a modification of the second embodiment. Similarly to the semiconductor device 200 shown in Fig. 8, the semiconductor device 210 has the passive component 30 disposed inside the substrate 77. On the other hand, the control element 20 is disposed on the bottom surface 81 of the recess 80 provided on the substrate 77, which is different from the semiconductor device 200. As shown in Fig. 9, the control element 20 is covered by an insulating resin 40 embedded in the recess 80. Further, the electrode pad 23 of the control element 20 is connected to the connection terminal 17 of the second substrate 78 by a metal wire 22. Further, the memory element 50A is disposed on the passive component 30 and the control element 20 built in the substrate 77, and is connected to the insulating resin 40. As shown in Fig. 3 (a), the insulating resin 40 can be formed by providing a resin layer 40 on the back surface of the memory element 50A. As shown in FIG. 9, the recessed portion 80 is formed from the opening provided in the second base 7 8 toward the first base 71. Also, the depth of the recess 80 can be set to be deeper than the thickness of the control element 20. Further, the connection terminal 17 is provided around the opening of the concave portion 80 on the surface on the opposite side of the insulating layer 72 of the second substrate 78. The semiconductor device 210 according to the modification of the second embodiment has the same effects as those of the second embodiment 158624.doc • 13-201230286. By electrically connecting the electrode pad 23 of the control element 20 to the second substrate 位于 located at the uppermost layer of the substrate 77, the wiring distance between the memory element 50A and the control element 20 can be shortened. As a result, the semiconductor device 200 can be operated at a high speed. Furthermore, the semiconductor device 2i. Since the control element 20 is disposed in the concave portion of the substrate 77, the thickness of the package can be reduced as compared with the semiconductor device 200 shown in Fig. 8. Fig. 10 is a schematic view showing a cross section of a semiconductor device 22A according to another modification of the second embodiment. The semiconductor device 220 has the passive component 3 built into the substrate 77, and the control element 2 is disposed at the point of the recess 80 provided in the substrate "the same as the semiconductor device 21A shown in FIG. 9. In the semiconductor device 22, the inside of the recessed portion 8 is filled with the insulating resin 45, and the control element 2 is covered with the insulating resin 45. Further, the s-resonant element 50A is connected and mounted to the insulating resin 45. This point is different from the semiconductor device 210. The memory element 50A has an adhesive layer 4' disposed on the back surface adhered to the insulating resin 45 via the adhesive layer 47. Fig. 11 shows a part of the manufacturing process of the semiconductor device 220. First, a profile of a substrate 77 having a passive component 80 is prepared. Thereafter, a recess 80 is formed which exposes the upper surface of the first substrate 71. As shown in Fig. 11(a), it is disposed in the substrate 77. The control element 20 is attached to the bottom surface 81 of the recess 80 (the upper surface of the first base 71). The back surface of the control element 2 is provided with, for example, a thermosetting resin-containing adhesive layer 21 which is crimped to the bottom surface 81 of the recess 80. And by heating the substrate 77 The bonding layer 21 is hardened, and the control element 20 can be fixedly adhered to the bottom surface 81 of the recess 80. I58624.doc 14 201230286 Next, the electrode pad 23 of the control element 2 is connected to the surface 77a of the substrate 77 by using the metal wire 22. The connection terminal 17. The modification of the embodiment can be manufactured by the steps of Fig. 3 to Fig. 5. Thereafter, the insulating resin 45 is filled inside the recess 80. Insulation resinization can be used. For example, a thermosetting epoxy resin can be used as a low viscosity which is diffused into a solvent such as 丫-butyrolactone, whereby deformation of the metal wire 22 and generation of pores can be suppressed, and the concave portion 8 can be uniformly filled. Next, the substrate 77 is heated to evaporate the solvent, and the epoxy resin is cured. Next, as shown in Fig. 11(b), the memory element 50A is mounted on the control element 2A and the passive component 3A. The back of the memory element 50A For example, a B_stage adhesive layer 47 is provided, and the occupant can be adhered to the surface of the insulating resin 45. Then, the layer 47 can be formed by coating, for example, a thermosetting resin. Further, the DAF can be attached. As shown in Figure 10 The memory elements 5A and 50C may be stowed. The adhesive layer 43 disposed on the back surface of the memory devices 50A and 50 may be the same as the adhesive layer 47 disposed on the memory device 50, or the adhesive layer 47 may be thicker than the adhesive layer 43. The semiconductor device 220 of another example of the modification of the second embodiment has the same effect as that of the second embodiment. Further, as described above, the viscosity at the time of filling the insulating resin 45 covering the control element 20 can be reduced, and the control can be suppressed. The metal wire 22 of the element 20 is deformed, and the inside of the concave portion 80 is prevented from generating pores. Further, the insulating resin 45 filling the concave portion 80 is provided separately from the adhesive layer 47 of the adhesive memory element 50A. Therefore, the semiconductor device 210 shown in Fig. 9 can be used only as a thin adhesive layer 47 without filling the recessed portion 80 with a resin layer provided on the back surface of the memory element 50A. Thereby, the same layer as the memory elements 50B and 5C stacked on the upper stage can be used, so that the manufacturing process of the memory element 50A can be simplified. (Third Embodiment) Fig. 12 is a schematic view showing a cross section of a semiconductor device 300 according to a third embodiment. The semiconductor device 300 is different from the first embodiment in that the passive component 30 is not formed. Also in this embodiment, the same effects as those of the first embodiment can be obtained. (Fourth Embodiment) Fig. 13 is a schematic view showing a cross section of a semiconductor device 400 according to a fourth embodiment. The semiconductor device 400 is different from the second embodiment in that the passive component 30 is not formed. Also in this embodiment, the same effects as those of the second embodiment can be obtained. Although the semiconductor devices of the first and fourth embodiments have been described above, the embodiment is not limited thereto. For example, the number of memory elements mounted on a semiconductor device is not limited to three, and three or more memory elements can be stacked, or three or less. While a number of embodiments of the invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. The present invention may be embodied in a variety of other forms, and various omissions, substitutions and changes can be made without departing from the spirit of the invention. The accompanying claims and their equivalents are intended to cover such forms or modifications, and such forms or modifications are within the scope and spirit of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a cross section of a semiconductor device according to a first embodiment. 2(Α)·(〇) shows a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. Fig. 3(A) and (B) are schematic cross-sectional views showing a manufacturing process of the semiconductor device continued from Fig. 2. 4(A) and 4(B) are schematic cross-sectional views showing the manufacturing process of the semiconductor device of Fig. 3. Fig. 5 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 4. Fig. 6 is a view showing the first embodiment. Fig. 7 is a schematic view showing a cross section of a semiconductor device according to another modification of the first embodiment. Fig. 8 is a view showing a scraped surface of the semiconductor device according to the second embodiment. Fig. 9 is a schematic view showing a cross section of a semiconductor device according to a modification of the second embodiment. Fig. 10 is a schematic view showing a cross section of a semiconductor device according to another modification of the second embodiment. (B) is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a modification of the second embodiment. Fig. 12 is a schematic view showing a cross section of the semiconductor device according to the third embodiment. Fig. 13 is a view showing a fourth embodiment. half Schematic diagram of the section of the body device 0 158624.doc -17- 201230286 [Description of main components] 10 Substrate 10a Surface 10b Back 15 Solder ball 17 Connection terminal 18 Connection terminal 19 Wiring 20 Control element 21 Next layer 22 Metal wire 23 Electrode Pad 30 Passive part 32 Metal wire 33 Electrode 40 Insulating resin 40a Resin layer 43 Connection layer 45 Insulating resin 50A Memory element 50B Memory element 50C Memory element 51A Electrode pad 51B Electrode pad 158624.doc -18 201230286 51C Electrode welding Pad 52 Metal wire 60 Sealing resin 70 Substrate 71 First substrate 72 Insulating layer 73 Wiring layer 74 Bump 75 Second substrate 75a Second substrate 77 Substrate 78 Second substrate 79 Wiring 80 Concave portion 81 Bottom surface 100 Semiconductor device 110 Semiconductor device 120 semiconductor device 200 semiconductor device 210 semiconductor device 220 semiconductor device 300 semiconductor device 400 semiconductor device 158624.doc • 19

Claims (1)

201230286 七、申請專利範圍： 1·—種半導體裝置，其特徵為包含： 基板； 配置於上述基板上之控制元件； 覆蓋上述控制元件之樹脂；及 配置於上述控制元件上，連接於上述樹脂，並藉由上 述控制元件予以控制之記憶元件；且 自上方俯視，上述控制元件係配置於上述記憶元件之 正下方區域内。 2·如請求項1之半導體裝置，其中 進而包含配置於上述基板上或上述基板内部之被動零 件，且 上述被動零件係配置於上述記憶元件之正下方區域 内。 3_如請求項2之半導體裝置，其中 具備藉由上述控制元件予以控制之複數個記憶元件， 上述複數個記憶元件係將其各自之位置成階梯狀錯開 而積載，且 在與配置有上述控制元件之上述基板之表面平行地俯 視時’上述控制元件與上述被動零件配置於上述複數個 記憶元件之正下方區域内。 4.如請求項2之半導體裝置，其中 上述被動零件係配置於上述基板上， 上述樹脂係覆蓋上述控制元件及上述被動零件。 158624.doc 201230286 5. 如請求項2之半導體裝置，其中 上述基板包含第1基底、第2基底、及設置於該等之間 之絕緣層； 上述控制元件與上述記憶元件係配置於與上述絕緣層 相反側之上述第2基底上； 上述被動零件係配置於上述第1基底與上述第2基底之 間，且被上述絕緣層覆蓋。 6. 如請求項！之半導體裝置，其中上述控制元件與設置於 上述基板之端子之間係經由金屬線連接。 7·如請求項1之半導體裝置，其中上述被動零件與設置於 上述基板之布線之間係經由金屬線連接。 8.如請求項丨之半導體裝置，其中上述控制元件與上述記 憶元件係經由設置於上述基板之布線連接，上述控制元 件係控制上述記憶元件。 9_如凊求項1之半導體裝置’其中上述控制元件係配置於 没置於上述基板中之凹部之底面。 10.如請求項9之半導體裝置，其中上述凹部較上述控制元 件之厚度更深。 η·如請求項9之半導體裝置，其中上述被動零件係配置於 上述基板之内部。 12.如請求項9之半導體裝置，其中 上述基板包含第】基底、第2基底、及設置於該等之間 之絕緣層； 上述凹部係自設置於上述第2基底之開口朝上述第}基 158624.doc 201230286 底之方向設置； 上述被動零件係配置於上述第丨基底與上述第2基底之 間，且被上述絕緣層覆蓋。 13. 如請求項12之半導體裝置，其中上述控制元件係經由金 屬線而連接於設置於上述第2基底之與上述絕緣層相反 側的表面之端子。 14. 如請求項12之半導體裝置，其中上述被動零件係焊接於 上述第1基底上，且與設置於上述第2基底之與上述絕緣 層相反側之表面的端子電性連接。 15. 如請求項1之半導體裝置，其中上述樹脂含有熱硬化性 成分。 16. 如請求項1之半導體裝置，其包含設置於上述基板之與 配置有上述控制元件之表面相反之背面之焊球； 上述控制元件及上述被動零件、與上述焊球電性連 接。 17. —種半導體裝置之製造方法，其特徵為： 準備基板，該基板包含配置於基板上之控制元件、及 配置於上述基板上或上述基板内部之被動零件； 準備記憶元件，該記憶元件具備設置於背面之樹脂 層；及 經由覆蓋上述控制元件之上述樹脂層而將上述記憶元 件黏貼於上述基板上。 18. 如請求項17之半導體裝置之製造方法，其中上述樹脂層 為半硬化狀態之熱硬化性樹脂。 158624.doc 201230286 19. 20. 如請求項17之半導體裝置之製造方法， 丹1f上述樹脂層 為晶粒附著膜（Die attach film)。 一種半導體裝置之製造方法，其特徵為： 準備基板，該基板包含配置於基板上之控制元件、及 配置於上述基板上或上述基板内部之被動零件； 準備記憶元件，該記憶元件具備設置於背面之接著 層； 以樹脂覆蓋上述控制元件；及 經由上述接著層將上述記憶元件黏貼於上述樹脂上。 158624.doc201230286 VII. Patent application scope: 1. A semiconductor device, comprising: a substrate; a control element disposed on the substrate; a resin covering the control element; and a control element disposed on the control element and connected to the resin And a memory element controlled by the control element; and viewed from above, the control element is disposed in a region directly under the memory element. The semiconductor device according to claim 1, further comprising a passive component disposed on the substrate or inside the substrate, wherein the passive component is disposed in a region directly under the memory element. The semiconductor device according to claim 2, further comprising: a plurality of memory elements controlled by said control element, wherein said plurality of memory elements are staggered and staggered in their respective positions, and said control is arranged When the surface of the substrate of the element is viewed in parallel, the control element and the passive component are disposed in a region directly under the plurality of memory elements. 4. The semiconductor device according to claim 2, wherein said passive component is disposed on said substrate, and said resin covers said control element and said passive component. The semiconductor device of claim 2, wherein the substrate comprises a first substrate, a second substrate, and an insulating layer disposed between the substrates; and the control element and the memory device are disposed in insulation with the memory device The second substrate is on the opposite side of the layer; the passive component is disposed between the first substrate and the second substrate, and is covered by the insulating layer. 6. As requested! In the semiconductor device, the control element and the terminal provided on the substrate are connected via a metal wire. The semiconductor device according to claim 1, wherein the passive component and the wiring provided on the substrate are connected via a metal wire. 8. The semiconductor device according to claim 1, wherein said control element and said memory element are connected via a wiring provided on said substrate, and said control element controls said memory element. A semiconductor device according to claim 1, wherein said control element is disposed on a bottom surface of a recess not disposed in said substrate. 10. The semiconductor device of claim 9, wherein the recess is deeper than the thickness of the control element. The semiconductor device of claim 9, wherein the passive component is disposed inside the substrate. 12. The semiconductor device of claim 9, wherein the substrate comprises a second substrate, a second substrate, and an insulating layer disposed between the substrates; and the recess is formed from the opening of the second substrate toward the first substrate 158624.doc 201230286 The bottom direction is disposed; the passive component is disposed between the second base and the second base, and is covered by the insulating layer. 13. The semiconductor device according to claim 12, wherein said control element is connected to a terminal provided on a surface of said second substrate opposite to said insulating layer via a metal wire. 14. The semiconductor device according to claim 12, wherein said passive component is soldered to said first substrate, and is electrically connected to a terminal provided on a surface of said second substrate opposite to said insulating layer. 15. The semiconductor device of claim 1, wherein the resin contains a thermosetting component. 16. The semiconductor device of claim 1, comprising: a solder ball disposed on a back surface of the substrate opposite to a surface on which the control element is disposed; the control element and the passive component being electrically connected to the solder ball. 17. A method of manufacturing a semiconductor device, comprising: preparing a substrate including a control element disposed on the substrate; and a passive component disposed on the substrate or inside the substrate; preparing a memory element having the memory element a resin layer provided on the back surface; and the memory element is adhered to the substrate via the resin layer covering the control element. 18. The method of producing a semiconductor device according to claim 17, wherein the resin layer is a thermosetting resin in a semi-hardened state. The method of manufacturing the semiconductor device of claim 17, wherein the resin layer is a die attach film. A method of manufacturing a semiconductor device, comprising: preparing a substrate including a control element disposed on the substrate; and a passive component disposed on the substrate or inside the substrate; preparing a memory element having a memory element disposed on the back surface a second layer; covering the control element with a resin; and adhering the memory element to the resin via the adhesive layer. 158624.doc
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