WO2013120366A1 - 一种阵列基板及其制造方法和显示设备 - Google Patents

一种阵列基板及其制造方法和显示设备 Download PDF

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Publication number
WO2013120366A1
WO2013120366A1 PCT/CN2012/084415 CN2012084415W WO2013120366A1 WO 2013120366 A1 WO2013120366 A1 WO 2013120366A1 CN 2012084415 W CN2012084415 W CN 2012084415W WO 2013120366 A1 WO2013120366 A1 WO 2013120366A1
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layer
electrode layer
gate
source
drain electrode
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French (fr)
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成军
陈海晶
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • OLEDs Organic light-emitting displays
  • LCDs are a new generation of display devices that have many advantages over liquid crystal displays, such as: self-illumination, fast response, wide viewing angle, and the like.
  • OLEDs can be used for flexible displays, transparent displays, 3D displays, and more.
  • each pixel controls the switching of the pixel through a thin film transistor, so that each pixel can be independently controlled by the driving circuit without causing crosstalk or the like to other pixels.
  • the array substrate includes a thin film transistor and a gate lead-out region or a source lead-out region, and the thin film transistor includes at least a gate, a source, a drain, a gate insulating layer, and an active layer.
  • the active layer is mainly silicon, and amorphous silicon or polycrystalline silicon can be used.
  • a thin film transistor using amorphous silicon as an active layer is limited in characteristics (such as mobility, on-state current, etc.), it is difficult to be used in applications requiring large current and fast response, such as an organic light-emitting display and a large size.
  • Thin film transistors using polysilicon as the active layer are superior to amorphous silicon in that they can be used in organic light-emitting displays. However, due to their poor uniformity, it is still difficult to prepare large-sized panels. Although the problem of uneven polysilicon characteristics can be dealt with by adding a compensation circuit, the number of thin film transistors and capacitors in the pixel is increased, the number of masks and the difficulty of fabrication are increased, resulting in a decrease in yield and a decrease in yield. In addition, if LTPS (low temperature polysilicon) technology such as ELA (excimer laser annealing) is used to crystallize amorphous silicon, expensive equipment and maintenance costs are required.
  • LTPS low temperature polysilicon
  • ELA excimer laser annealing
  • oxide semiconductors are receiving increasing attention.
  • the characteristics of a thin film transistor in which an oxide semiconductor is an active layer are superior to those of a thin film transistor in which an amorphous silicon is used as an active layer, such as mobility, on-state current, switching characteristics, and the like.
  • the thin film transistor in which an oxide semiconductor is used as an active layer is inferior to the characteristics of a thin film transistor in which polysilicon is used as an active layer, it is sufficient for applications requiring fast response and large current, such as high frequency, high ratio, large size. Displays and organic light-emitting displays, and the like.
  • the uniformity of the oxide is good, and there is no need to increase the compensation circuit because there is no uniformity problem compared with polysilicon.
  • FIGS. 1a and 1b are cross-sectional views of the array substrate, including the substrate 100, the gate electrode layer 101, and the gate insulating layer.
  • the etch stop layer 104 is designed such that the source electrode layer 105a and the drain electrode layer 105b overlap the etch stop layer 104 by a step below the source electrode layer 105a and the drain electrode 105b.
  • An embodiment of the present invention provides an array substrate, including: a substrate; a gate electrode layer, a gate insulating layer, an active layer, an etch barrier layer, a source/drain electrode layer, a passivation layer, and a transparent electrode on the substrate a layer, wherein: the gate electrode layer includes a gate electrode, the source/drain electrode layer includes a source electrode layer and a drain electrode layer, and an area of the etch barrier layer is greater than or equal to an area of the active layer, and is set useful a first via hole connected to the active layer in the source electrode layer and the drain electrode layer.
  • Another embodiment of the present invention provides a method for fabricating an array substrate, comprising: sequentially forming a gate electrode layer, a gate insulating layer, an active layer, and an etch barrier layer on a substrate, wherein an area of the etch barrier layer is greater than or equal to The area of the active layer, the gate electrode layer includes a gate electrode and a gate lead line at the gate lead-out region; a first via hole is formed in the etch barrier layer; and a source electrode layer and a drain electrode layer are formed The source electrode layer and the drain electrode layer are connected to the active layer through the first via hole; a passivation layer is formed, and the passivation layer is etched; and a transparent electrode layer is formed, the transparent electrode A layer is connected to the drain electrode layer and the gate lead line.
  • a further embodiment of the present invention provides a method for fabricating an array substrate, comprising: sequentially forming a source/drain electrode layer and an etch barrier layer on a substrate, the source/drain electrode layer including a source electrode layer and a drain electrode layer, and a source lead-out a source lead line of the region; forming a first via hole respectively at positions corresponding to the source electrode layer and the drain electrode layer in the etch barrier layer; forming an active layer and a gate insulating layer, the active The layer is connected to the source electrode layer and the drain electrode layer through the first via hole, the area of the etch barrier layer is greater than or equal to the area of the active layer; forming a gate electrode layer; forming a passivation layer, and forming the passivation layer Etching the layer; forming a transparent electrode layer, the transparent electrode layer and the source lead line Connected to the drain electrode layer.
  • Yet another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.
  • Figures la and lb are cross-sectional views of an array substrate of a bottom gate structure in the prior art
  • FIGS. 2a and 2b are cross-sectional views of an array substrate of a bottom gate structure according to an embodiment of the present invention
  • FIGS. 3a and 3b are cross-sectional views of an array substrate of a top gate structure according to an embodiment of the present invention
  • FIGS. 4a-4j are diagrams of the present invention The cross-sectional view of the array substrate corresponding to each step in the method for fabricating the array substrate of the bottom gate structure provided by the embodiment;
  • 5a-51 are cross-sectional views of array substrates corresponding to respective steps in a method for fabricating an array substrate of a top gate structure according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device.
  • the area of the etch barrier layer is greater than or equal to the area of the active layer, and the source electrode layer and the drain electrode layer are The connection of the active layer is provided with a via hole, thereby preventing the source electrode layer, the drain electrode layer or the active layer from appearing an additional step when it is bordered with the etch barrier layer.
  • the array substrate provided by the embodiment of the present invention includes:
  • the area of the etch barrier layer 104 is greater than or equal to the area of the active layer 103, and is provided for the source A via hole in which the electrode layer 105a and the drain electrode layer 105b are connected to the active layer 103.
  • the outer step is avoided.
  • the etch stop layer 104 may further cover the entire substrate and be provided with via holes in the gate lead-out region or the source lead-out region.
  • the source electrode layer 105a, the drain electrode layer 105b, and the gate electrode layer 101 are drawn out during the fabrication of the backplane of the oxide array substrate, a via hole is usually formed in the passivation layer 106 and the gate insulating layer 102.
  • a via hole is usually formed in the passivation layer 106 and the gate insulating layer 102.
  • the hole depth of the gate electrode layer 101 is different from that of the gate electrode layer 101.
  • the selection ratio of the source electrode layer 105a, the drain electrode layer 105b and the gate insulating layer 102 is high, and the process slightly fluctuates to cause the source electrode layer 105a to leak.
  • the metal of the pole layer 105b is etched or the gate insulating layer 102 is not completely etched.
  • the gate electrode of the thin film transistor is connected to the gate line, and the gate line extends to the gate lead-out area to become a gate lead and is connected to the driving circuit. Since the hole leading to the gate lead is too deep, the most typical depth is 600 nm, and at this depth, at least three different layers are formed, the material of each layer is different, and the etching rate of the uppermost layer is different from the etching rate of each film below. This not only makes the etching atmosphere ratio difficult to master, but also causes the photoresist reaction to generate an organic substance at the bottom of the hole due to the etching time being too long, so that the metal electrode is disconnected when it is taken out.
  • the transparent electrode may be made of ITO or may be made of other materials such as graphene or Ag (silver) wire. Since the hole for extracting the gate electrode is too deep, the transparent electrode is connected from the uppermost end to the lowermost end of the hole, and if the thickness of the transparent electrode is too thin, the wire is broken. If the transparent electrode is too thick, the etching of the transparent electrode is difficult.
  • the etch barrier layer 104 covers the entire substrate, and a via hole is disposed in the gate lead-out region or the source lead-out region, and is in the via hole of the gate lead-out region or the source lead-out region.
  • a conductive material 113 is provided; the gate electrode layer 101 is connected to the transparent electrode layer 107 through the filler 113 in the gate lead-out region, or the source electrode layer 105a is transparently connected by the filler 113 in the via hole of the source lead-out region.
  • Electrode layer 107 For example, the source of the thin film transistor is connected to the source lead-out area through the data line, in the source lead-out area
  • the data line leads connected to the data lines are connected to other components or circuits through vias in the source lead-out area.
  • the gate of the thin film transistor is connected to the gate lead-out region through a gate line, and in the gate lead-out region (for example, the region shown in FIG. 2b), the gate line lead connected to the gate line passes through the via of the gate lead-out region and other components or circuits connection.
  • the etch stop layer 104 is formed, not only a part of the etch stop layer 104 is left on the upper portion of the active layer, but a via hole is provided in the gate lead-out area or the source lead-out area to realize the connection of the layers, so that one etching can be performed.
  • the etching barrier layer and the gate insulating layer are both etched without increasing the number of etchings.
  • a via connection can be formed at the via hole.
  • the metal that is, the conductive filler 113, reduces the depth of the via holes to be formed when the passivation layer 106 is etched, thereby reducing the process difficulty.
  • the diameter of the through hole may be set to lum ⁇ 10um.
  • through holes for connecting the source electrode layer and the drain electrode layer to the active layer are provided, specifically:
  • a first via hole is provided for penetrating the etch barrier layer for the active layer to communicate with the source electrode layer and the drain electrode layer.
  • a through hole is disposed in the gate lead-out area, as shown in FIG. 2b, specifically including:
  • the array substrate further includes a fourth via hole 110 penetrating the passivation layer 106 that communicates with the transparent electrode layer 107 and the drain electrode layer 105b.
  • 105b is called a drain electrode layer
  • 105a is called a source electrode layer.
  • the source and drain electrodes of the field effect transistor are actually symmetrical structures, and when one is used as the source electrode, the other is used as the drain electrode, and the roles of the two can be interchanged as needed. Therefore, in some cases, 105b may be referred to as a source electrode layer, and 105a may be referred to as a drain electrode layer, which is not limitative of the present invention.
  • the source lead-out region is not shown, since the source lead-out line of the source lead-out region is located in the same layer as the source-drain electrode layer, it is above the gate insulating layer and the etch stop layer, under the passivation layer. Therefore, in the bottom gate structure, the connection of the source lead wires to other components only needs to form a via hole in the passivation layer.
  • the transparent conductive layer 107 shown in FIG. 2a and the transparent conductive layer 107 shown in FIG. 2b are given the same names and reference numerals. However, there may be no connection between the two, and they may have different roles. For example, the transparent electrode layer 107 of FIG.
  • the transparent electrode layer 107 of FIG. 2b can be used as a connection line, but is not limited thereto.
  • the layer 107 shown in Figure 2b can also be formed from an opaque conductive material.
  • through holes for connecting the source electrode layer and the drain electrode layer to the active layer are provided, specifically:
  • a first via hole is provided for penetrating the etch barrier layer for the active layer to communicate with the source electrode layer and the drain electrode layer.
  • a through hole is disposed in the source lead-out area, as shown in FIG. 3b, specifically including:
  • the array substrate further includes: a fifth via hole 110 penetrating the passivation layer 106 in which the gate electrode layer 101 communicates with the transparent electrode layer 107.
  • the filler 113 is simultaneously etched while the source electrode layer 105a and the drain electrode layer 105b are formed, and the filler 113 in the second via hole is in the same layer as the source electrode layer 105a and the drain electrode layer 105b.
  • the filler 113 in the third via hole is in the same layer as the gate electrode layer 101 and has the same material for the source lead.
  • the surface of the filler 113 and the source/drain electrode layer or the gate electrode layer 101 may be made as horizontal as possible during fabrication so that the fourth via hole and the first via hole
  • the five via holes may be etched using the same depth so as to perform the selection ratio setting when etching is performed to obtain the fourth via holes and the fifth via holes.
  • the gate lead-out region is not shown, since the gate lead-out line of the gate lead-out region is in the same layer as the gate electrode layer, it is above the gate insulating layer and the etch stop layer, under the passivation layer, Therefore, in the top gate structure, the connection of the gate lead wires to other components only needs to form via holes in the passivation layer.
  • the depth of the first via hole is the same as the thickness of the etch stop layer 104, or the first The depth of the via hole is greater than the thickness of the etch barrier layer by 1 to 60 nm.
  • the depth of the first via hole is slightly larger than the thickness of the etch barrier layer 104 as long as the active layer 103 is not penetrated, so that the source electrode The layer and the drain electrode layer can be in contact with the active layer 103;
  • the depth of the second via hole and the third via hole is equal to the thickness of the etch barrier layer and the gate insulating layer, or the depths of the second via hole and the third via hole are greater than the thickness of the etch barrier layer and the gate insulating layer and l- 100 nm, in the same way, in general, the depths of the second via hole and the third via hole are slightly larger than the thickness of the etch barrier layer and the gate insulating layer, as long as the gate electrode layer or the source electrode layer is not penetrated, thereby
  • the transition metal can be preferably in contact with the gate electrode layer or the source electrode layer;
  • the depth of the fourth via hole and the fifth via hole is equal to the thickness of the passivation layer, or the depth of the second via hole and the third via hole is greater than the thickness of the passivation layer by l-100 nm, and, in general, the fourth pass
  • the depth of the hole and the fifth via hole is slightly larger than the thickness of the passivation layer as long as the gate electrode layer or the source electrode layer is not penetrated, so that the transparent electrode layer can be better contacted with the gate electrode layer or the source electrode layer.
  • the embodiment of the present invention provides a method for fabricating an array substrate, comprising: step S401, sequentially forming a gate electrode layer 101, a gate insulating layer 102, an active layer 103, and an etch barrier layer 104 on the substrate, and etching blocking
  • the area of the layer is greater than or equal to the area of the active layer, as shown in FIGS. 4a and 4b;
  • the gate electrode layer 101 includes a gate electrode of the thin film transistor (shown as 101 in FIG. 4a) and a gate at the gate lead-out region.
  • Lead wire shown as 101 in Figure 4b);
  • Step S402 etching the etch barrier layer and the gate insulating layer to form a first via hole for penetrating the etch barrier layer for the active layer to communicate with the source electrode layer and the drain electrode layer, as shown in FIG. 4c and FIG. 4d.
  • Step S404 forming a passivation layer, and etching the passivation layer, as shown in FIG. 4g and FIG. 4h; Step S405, forming a transparent electrode layer, and connecting the transparent electrode layer 107 to the source electrode layer and the gate electrode layer, as shown in 4i, shown in Figure 4j.
  • the etching barrier layer and the gate insulating layer are etched to form a first via hole for the active layer to communicate with the source electrode layer and the drain electrode layer, and the first via hole is penetrated.
  • a drain filler layer material having the same material for performing a transition connection between the gate electrode layer (gate lead) and the transparent electrode layer (such as 113 in FIG. 4f) for performing between the gate electrode layer and the transparent electrode layer
  • the transition-connected filler is connected to the gate electrode layer (gate lead) through the second via.
  • the etching stopper layer and the gate insulating layer may be etched by via holes.
  • step S404 the passivation layer is etched, specifically:
  • step S404 the depths of the fourth via hole and the fifth via hole may be made the same so that the selection ratio is set when the fourth via hole and the fifth via hole are obtained by etching.
  • a gate electrode material is first deposited on the substrate 100 and patterned into a gate electrode layer 101 by photolithography; a gate insulating layer 102 is disposed on the gate electrode layer 101, and an active layer is formed on the gate insulating layer 102.
  • An etch stop layer 104 is deposited on the active layer 103 and the gate insulating layer 102, and the portions to be connected are etched on the etch barrier layer 104 by photolithography, where the portions include the gate electrode layer 101, and the source
  • the electrode layer 105a and the drain electrode layer 105b are connected to the two sides of the active layer 103; next, a source/drain metal is deposited on the etch barrier layer 104, and the source electrode layer 105a and the drain electrode layer 105b and the gate lead-out portion are formed by photolithography.
  • the filling layer 113 forms a passivation layer 106 and a transparent electrode layer 107.
  • the transparent electrode layer 107 is connected to the source electrode layer 105a and the gate electrode layer 101 through via holes of the passivation layer 106, respectively.
  • Mo molybdenum
  • Mo b molybdenum-niobium alloy
  • A1 aluminum
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • the gate electrode layer 101 preferably has a single layer or a multilayer composite film composed of Mo, Al or an alloy containing Mo, Al.
  • the gate insulating layer 102 may be composed of SiOx (silicon oxide), SiNx (silicon nitride), HfOx (yttria), AlOx (alumina), or a multilayer laminated film composed of two or more of them.
  • the gate insulating layer is made of a special PECVD (plasma enhanced chemical vapor deposition) technique, characterized in that the film layer contains a low low hydrogen content, and the gate insulating layer or the active layer surface forms a good contact, so that the insulating layer The chemical composition between the active layer and the active layer is difficult to diffuse.
  • PECVD plasma enhanced chemical vapor deposition
  • the thickness of the gate insulating layer can be controlled to be 100 nm to 400 nm, and the gate insulating layer is preferably a multilayer structure in which SiOx, SiNx, or both are combined.
  • the active layer 103 may be made of a film containing In (indium), Ga (gallium), Zn (express), 0 (oxygen), Sn (tin), amorphous silicon, wherein the film must contain oxygen and other Two or more elements such as IGZO (Indium Oxide), IZO (Indium Oxide), InSnO (Indium Tin Oxide), InGaSnO (InGaAs).
  • the active layer is preferably IGZO and IZO, and the thickness is preferably controlled at 10 to 100 nm.
  • the etch barrier layer 104 may be composed of SiOx SiNx HfOx AlOx or a multilayer laminated film composed of two or three of them. Etch Barrier Features The layer contains a low low hydrogen content. A via hole is formed in a region where the source electrode layer, the drain electrode layer and the active layer of the etch barrier layer are connected to the active layer, and the gate electrode layer is taken out to extract the gate electrode layer, the source electrode layer, the drain electrode layer, and the active layer. All of the places where no connection is required can be covered with an etch barrier.
  • the source electrode layer 105a, the drain electrode layer 105b, and the filler 113 are formed by sputtering a source/drain metal, and then photolithographically forming a source electrode layer, a drain electrode layer, and a filler 113.
  • the material of the source electrode layer 105a and the drain electrode layer 105b may be a single layer or a multilayer composite laminate formed of one or more materials of Mo MoNb Al AlNd Ti Cu, preferably composed of Mo A1 or an alloy containing Mo A1 . Single or multi-layer composite film.
  • the source electrode layer 105a and the drain electrode layer 105b are connected to the active layer 103 through the via holes of the etch barrier layer 104, and the filler 113 is connected to the gate electrode layer 101 through the via holes of the etch barrier layer 104.
  • the source electrode layer 105a and the drain electrode layer 105b and the filler 113 have a thickness of 50 to 500.
  • the passivation layer 106 may be composed of SiOx SiNx HfOx AlOx or a multilayer laminated film composed of two or more of them.
  • the passivation layer may be formed by a special PECVD technique, characterized in that the film layer has a low low hydrogen content. And having good surface characteristics, making it difficult for the chemical components between the passivation layer and the active layer to diffuse each other.
  • the transparent electrode layer 107 On the passivation layer is a transparent electrode layer 107, and the transparent electrode layer 107 can be made of an ITO (indium tin oxide) material, and amorphous ITO is prepared by a sputtering film formation, and then crystallized by annealing.
  • the transparent electrode layer 107 has a thickness of 20 to 150 nm.
  • the transparent electrode layer 107 is connected to the source electrode layer 105a through the fourth via hole, and is connected to the filler on the gate electrode layer through the fifth via hole.
  • the embodiment of the present invention further provides a method for fabricating an array substrate, comprising: step S501, sequentially forming a source/drain electrode layer and an etch barrier layer on the substrate, wherein an area of the etch barrier layer is greater than or equal to an area of the active layer 5a and 5b; the source-drain electrode layer includes a source electrode layer and a drain electrode layer of the thin film transistor (as shown in 105a and 105b of FIG. 5a) and is located at the source The source lead of the lead-out area (shown as 105a in Figure 5b);
  • Step S502 etching the etch barrier layer to form a first via hole for penetrating the etch barrier layer for the active layer to communicate with the source electrode layer and the drain electrode layer;
  • Step S503 forming an active layer and a gate insulating layer, wherein the active layer is connected to the source electrode layer and the drain electrode layer through the first via hole, as shown in FIG. 5c-5f;
  • Step S504 forming a gate electrode layer, as shown in FIG. 5g and FIG. 5h;
  • Step S505 forming a passivation layer, and etching the passivation layer, as shown in FIG. 5i and FIG. 5j;
  • Step S506 forming a transparent electrode layer, and connecting the transparent electrode layer to the gate electrode layer and the drain electrode layer, as shown in FIG. 5k and Figure 51 shows.
  • the method further includes:
  • Etching the gate insulating layer and the etch barrier layer to form a third via hole penetrating the etch barrier layer and the gate insulating layer for connecting the source lead and the transparent electrode layer in the source/drain electrode layer (as shown in FIG. 5f Show);
  • a filler having the same material as that of the gate electrode layer for performing the transition connection between the source wiring and the transparent electrode layer is formed on the third via hole (as shown by 113 in Fig. 5h).
  • the gate insulating layer and the etch barrier layer are etched, and the gate insulating layer and the etch barrier layer may be etched by via holes.
  • step S505 the passivation layer is etched, specifically:
  • step S505 the depths of the fourth via hole and the fifth via hole may be made the same, so that the selection ratio is set when the fourth via hole and the fifth via hole are obtained by etching.
  • a source electrode layer 105a and a drain electrode layer 105b are disposed on the substrate 100, and an etch stop layer 104 is formed on the source electrode layer 105a and the drain electrode layer 105b, and an active layer 103 is formed on the etch barrier layer.
  • a gate insulating layer 102 is deposited on the active layer 103, and a portion to be connected is etched on the gate insulating layer by photolithography, where the portion includes the source electrode layer 105a, the source electrode layer 105a and the drain electrode layer 105b is connected to the gate electrode layer 101, and then a gate metal is deposited on the gate insulating layer 102, and the gate electrode is photolithographically formed to form a gate 113 and a filler 113 at the lead portion of the source electrode layer 105a to form a passivation.
  • Layer 106, transparent electrode 107 through passivation layer 106 The holes are connected to the gate electrode layer 101 and the source electrode layer 105a, respectively.
  • each layer is consistent with the embodiment of the bottom gate structure, and will not be described herein.
  • the number of insulating layers on the gate lead of the gate lead-out region in the bottom gate structure is large (gate insulating layer, etch stop layer, and passivation layer),
  • the gate lead can be easily connected to other components;
  • the source lead (or data line lead) of the source lead-out region The upper insulating layer has a large number of layers (etching barrier layer, gate insulating layer, and passivation layer), and therefore, by using a transitional connection metal layer formed simultaneously with the gate electrode layer, the gate wiring can be easily connected to other components.
  • the embodiment of the invention further provides a display device, which comprises the array substrate provided by the embodiment of the invention.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device.
  • the area of the etch barrier layer is greater than or equal to the area of the active layer, and the source and drain electrode layers are The connection of the source layer is provided with a through hole, thereby avoiding the source electrode layer and the drain electrode
  • An array substrate comprising:
  • a gate electrode layer a gate insulating layer, an active layer, an etch barrier layer, a source/drain electrode layer, a passivation layer, and a transparent electrode layer on the substrate, wherein:
  • the gate electrode layer includes a gate electrode
  • the source/drain electrode layer includes a source electrode layer and a drain electrode layer
  • the etch barrier layer has an area greater than or equal to an area of the active layer, and is provided with a first via hole for connecting the source electrode layer and the drain electrode layer to the active layer.
  • the gate electrode layer further includes a gate lead line at a gate lead-out area
  • the source/drain electrode layer further including a source lead line located at a source lead-out area
  • the etch stop layer covers the entire substrate, and a through hole is disposed in the gate lead-out area or the source lead-out area.
  • the gate insulating layer, the etch stop layer and the passivation layer are sequentially covered on the gate lead line, and have a penetration barrier at a position corresponding to the gate lead line a second via of the layer and the gate insulating layer, and a fifth via penetrating the passivation layer.
  • the etch stop layer, the gate insulating layer and the passivation layer are sequentially overlying the source lead line and the drain electrode, and corresponding to the source lead line and the drain electrode And a third via hole penetrating the etch stop layer and the gate insulating layer, and a fourth via hole penetrating the passivation layer.
  • a depth of the first through hole is the same as a thickness of the etching stopper layer, or a depth of the first through hole Greater than the thickness of the etch stop layer.
  • a method of manufacturing an array substrate comprising:
  • the gate electrode layer Forming a gate electrode layer, a gate insulating layer, an active layer, and an etch barrier layer on the substrate, wherein an area of the etch barrier layer is greater than or equal to an area of the active layer, the gate electrode layer includes a gate electrode and is located a gate lead line of the gate lead-out area;
  • Forming a first via hole in the etch barrier layer Forming a source electrode layer and a drain electrode layer, wherein the source electrode layer and the drain electrode layer are connected to the active layer through the first via hole;
  • a transparent electrode layer is formed, and the transparent electrode layer is connected to the drain electrode layer and the gate lead line.
  • Forming the source electrode layer and the drain electrode layer forming the same material as the source electrode layer and the drain electrode layer in the second via hole for performing the gate lead line and the transparent electrode layer A metal layer that is connected between the transitions.
  • etching the passivation layer comprises: forming a fourth via hole for penetrating the passivation layer in communication between the drain electrode layer and the transparent electrode layer, And a fifth via hole penetrating the passivation layer for the gate lead layer to communicate with the transparent electrode layer.
  • a method for manufacturing an array substrate comprising:
  • the source-drain electrode layer including a source electrode layer and a drain electrode layer and a source lead-out line at the source lead-out region;
  • a transparent electrode layer is formed, and the transparent electrode layer is connected to the source lead line and the drain electrode layer.
  • Forming the gate electrode layer forming the same material as the gate electrode layer in the third via hole for performing the drain electrode layer and the source lead line and the transparent A metal layer that is connected between the electrode layers.
  • a display device comprising the array substrate according to any one of (1) to (10).
  • the depths of the second via holes and the third via holes are equal to the thickness of the etch barrier layer and the gate insulating layer, or the depths of the second via holes and the third via holes are greater than the etch barrier layer and the gate electrode The thickness of the insulation layer.
  • the depths of the fourth via holes and the fifth via holes are equal to the thickness of the passivation layer, or the depths of the fourth via holes and the fifth via holes are greater than the thickness of the passivation layer.

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Abstract

一种阵列基板及其制造方法和显示设备，阵列基板包括基板（100）、栅电极层（101）、栅极绝缘层（102）、有源层（103）、蚀刻阻挡层（104）、源电极层（105a）、漏电极层（105b）、钝化层（106）以及透明电极层（107），蚀刻阻挡层（104）的面积大于或等于有源层（103）的面积，并在源电极层（105a）、漏电极层（105b）与有源层（103）的连接处设置有通孔。

Description

一种阵列基板及其制造方法和显示设备 技术领域
本发明的实施例涉及一种阵列基板及其制造方法和显示设备。 背景技术
有机发光显示器（OLED )是新一代的显示器件， 与液晶显示器相比， 具有很多优点， 如： 自发光， 响应速度快， 宽视角等等。 OLED可以用于柔 性显示， 透明显示， 3D显示等。
在有源矩阵有机发光显示器中， 每一个像素均通过薄膜晶体管控制该像 素的开关， 因此通过驱动电路， 可以独立控制每一个像素， 不会对其他像素 造成串扰等影响。
阵列基板中包括薄膜晶体管和栅极引出区或源极引出区， 薄膜晶体管至 少包含栅极、 源极、 漏极、 栅绝缘层和有源层。 目前， 有源层主要为硅， 可 以釆用非晶硅或者多晶硅。 釆用非晶硅作为有源层的薄膜晶体管时， 因其特 性的限制 （如迁移率、 开态电流等） ， 难以用于需要较大电流和快速响应的 场合， 如有机发光显示器和大尺寸、 高分辨率、 高刷新频率的显示器等。 釆 用多晶硅作为有源层的薄膜晶体管， 其特性优于非晶硅， 可以用于有机发光 显示器； 但是因其均匀性不佳， 制备中大尺寸的面板仍有困难。 虽然可用增 加补偿电路的方法处理多晶硅特性不均匀的问题， 但同时增加了像素中的薄 膜晶体管和电容的数量， 增加了掩模数量和制作难度， 造成产量减低和良率 下降。 另外， 如果釆用诸如 ELA (准分子激光退火）等的 LTPS (低温多晶 硅）技术来对非晶硅进行晶化， 还需要增加昂贵的设备和维护费用。
因此， 氧化物半导体日益受到重视。 氧化物半导体为有源层的薄膜晶体 管的特性优于非晶硅作为有源层的薄膜晶体管的特性，如迁移率、开态电流、 开关特性等。 虽然氧化物半导体作为有源层的薄膜晶体管的特性不如多晶硅 作为有源层的薄膜晶体管的特性， 但足以用于需要快速响应和较大电流的应 用， 如高频、 高分比率、 大尺寸的显示器以及有机发光显示器等。 氧化物的 均匀性较好， 与多晶硅相比， 由于没有均匀性问题， 不需要增加补偿电路， 在掩模数量和制作难度上均有优势。在制作大尺寸的显示器方面难度也较小。 而且釆用溅射等方法就可以制备， 不需增加额外的设备， 具有成本优势。
目前， 在氧化物阵列基板的制作过程中， 在形成蚀刻阻挡层后形成源电 极层和漏电极层， 图 la和图 lb为阵列基板截面图， 包括基板 100、 栅电极 层 101、 栅极绝缘层 102、 有源层 103、 蚀刻阻挡层 104、 源电极层 105a、 漏 电极层 105b、 钝化层 106以及透明电极层 107。 该蚀刻阻挡层 104的设计， 使得源电极层 105a, 漏电极层 105b与蚀刻阻挡层 104搭界的地方在源电极 层 105a和漏电极 105b的下方多出一个台阶。 在此容易造成源电极层 105a、 漏电极层 105b的断线或有源层 103的过蝕刻， 影响产品的良率。 发明内容
本发明的一个实施例提供一种阵列基板， 包括： 基板； 位于所述基板上 的栅电极层、 栅极绝缘层、 有源层、 蚀刻阻挡层、 源漏电极层、 钝化层以及 透明电极层， 其中： 所述栅电极层包括栅电极， 所述源漏电极层包括源电极 层和漏电极层， 以及所述蝕刻阻挡层的面积大于或等于所述有源层的面积， 并设置有用于源电极层、 漏电极层与所述有源层连接的第一通孔。
本发明的另一个实施例提供一种阵列基板制造方法， 包括： 在基板上依 次形成栅电极层、 栅极绝缘层、 有源层以及蝕刻阻挡层， 所述蝕刻阻挡层的 面积大于或等于所述有源层的面积， 所述栅电极层包括栅电极和位于栅极引 出区域的栅极引出线； 在所述蝕刻阻挡层中形成第一通孔； 形成源电极层和 漏电极层， 所述源电极层和所述漏电极层通过所述第一通孔与所述有源层连 接； 形成钝化层， 并对所述钝化层进行蚀刻； 以及形成透明电极层， 所述透 明电极层与所述漏电极层和所述栅极引出线连接。
本发明的再一个实施例提供一种阵列基板制造方法， 包括： 在基板上依 次形成源漏电极层和蚀刻阻挡层， 所述源漏电极层包括源电极层和漏电极层 以及位于源极引出区域的源极引出线； 在所述蝕刻阻挡层中对应于所述源电 极层和所述漏电极层的位置分别形成第一通孔；形成有源层以及栅极绝缘层 , 所述有源层通过所述第一通孔连接所述源电极层、 漏电极层， 所述蚀刻阻挡 层的面积大于或等于有源层的面积； 形成栅电极层； 形成钝化层， 并对所述 钝化层进行蝕刻； 以及形成透明电极层， 所述透明电极层与所述源极引出线 和所述漏电极层连接。
本发明的又一个实施例提供一种显示设备， 包括根据本发明任一实施例 的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 la和图 lb为现有技术中底栅结构的阵列基板截面图；
图 2a和图 2b为本发明实施例提供的底栅结构的阵列基板截面图； 图 3a和图 3b为本发明实施例提供的顶栅结构的阵列基板截面图； 图 4a-图 4j为本发明实施例提供的底栅结构的阵列基板制造方法中各步 骤对应的阵列基板截面图； 以及
图 5a-图 51为本发明实施例提供的顶栅结构的阵列基板制造方法中各步 骤对应的阵列基板截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供一种阵列基板及其制造方法和显示设备， 通过改善蚀 刻阻挡层的设计， 使蚀刻阻挡层的面积大于或等于有源层的面积， 并在源电 极层、 漏电极层与有源层的连接处设置有通孔， 进而避免源电极层、 漏电极 层或有源层在与蚀刻阻挡层搭界时出现额外的台阶。
如图 2a和图 2b所示， 本发明实施例提供的阵列基板， 包括：
基板 100、栅电极层 101、栅极绝缘层 102、有源层 103、蚀刻阻挡层 104、 源电极层 105a、 漏电极层 105b、 钝化层 106以及透明电极层 107。
蚀刻阻挡层 104的面积大于或等于有源层 103的面积， 并设置有用于源 电极层 105a和漏电极层 105b与有源层 103连接的通孔。
由于蚀刻阻挡层 104的面积大于或等于有源层 103的面积， 并通过通孔 的方式使得源电极层 105a和漏电极层 105b与有源层 103连接， 所以避免了 外的台阶。
为便于控制蚀刻阻挡层 104的形成， 该蚀刻阻挡层 104可以进一步覆盖 整个基板， 并在栅极引出区或源极引出区设置有通孔。
由于在氧化物阵列基板的背板制作过程中， 引出源电极层 105a、 漏电极 层 105b和栅电极层 101时，通常是在钝化层 106和栅极绝缘层 102形成过孔 来实现， 该制作过程存在的很多缺点： 如引出栅电极层的孔较深， 蚀刻难度 较大， 透明电极层 107 在连接栅电极层 101 时也容易断线； 引出源电极层 105a,漏电极层 105b的孔和引出栅电极层 101的孔深度不同，蚀刻孔时对源 电极层 105a, 漏电极层 105b和栅极绝缘层 102的选择比要求很高， 工艺稍 有波动便会导致源电极层 105a, 漏电极层 105b的金属被过刻或栅极绝缘层 102蚀刻不完全。
薄膜晶体管的栅电极与栅线相连， 栅线延伸到栅极引出区成为栅极引线 再与驱动电路相连。 由于引出栅极引线的孔太深， 最典型的深度是 600nm, 在这个深度上至少包含 3层不同的膜层， 每层的材料不同， 最上层的蚀刻速 率与下面每层膜的蚀刻速率都不同。 这样不但蝕刻气氛配比艮难掌握， 而且 由于蚀刻时间太长引起光刻胶反应在孔的底部生成一层有机物， 使金属电极 引出时断路。
透明电极可以由 ITO制作， 也可以由石墨烯、 Ag (银）丝等其它材料制 作。 由于引出栅电极的孔太深， 透明电极从孔最上端连接到最底端， 透明电 极的厚度如果太薄就会导致断线， 如果透明电极太厚又会使透明电极的蚀刻 困难。
因此，本发明实施例提供的阵列基板中，蚀刻阻挡层 104覆盖整个基板， 并在栅极引出区或源极引出区设置有通孔， 在栅极引出区或源极引出区的通 孔中， 设置有能够导电的填充物 113; 栅电极层 101在栅极引出区中通过填 充物 113连接透明电极层 107 ,或者源电极层 105a在源极引出区的通孔中通 过填充物 113连接透明电极层 107。 例如， 薄膜晶体管的源极通过数据线连接到源极引出区， 在源极引出区
(例如图 3b所示区域），与数据线连接的数据线引线通过源极引出区的过孔 与其他部件或电路连接。 薄膜晶体管的栅极通过栅线连接到栅极引出区， 在 栅极引出区（例如图 2b所示区域）， 与栅线连接的栅线引线通过栅极引出区 的过孔与其他部件或电路连接。 由于在形成蚀刻阻挡层 104后， 并非仅仅在 有源层上部保留一部分蚀刻阻挡层 104, 而是在栅极引出区或者源极引出区 设置通孔， 实现各层的连接， 所以可以通过一次蚀刻， 将蚀刻阻挡层和栅极 绝缘层均蚀刻成型， 没有增加蚀刻次数。
蚀刻阻挡层 104上的通孔形成后， 在形成底栅结构中的源电极层和漏电 极层或者在形成顶栅结构中的栅电极层时， 即可在通孔处形成用于进行过渡 连接的金属， 即导电的填充物 113 , 减少了蚀刻钝化层 106时， 所需形成的 通孔的深度， 进而降低了工艺难度。
在本发明实施例中， 通孔的直径可以设置为 lum~10um。
例如， 如图 2a和图 2b所示， 在底栅结构中， 设置有用于源电极层、 漏 电极层与有源层连接的通孔， 具体为：
设置有用于有源层与源电极层、 漏电极层连通的穿透蚀刻阻挡层的第一 通孔。
在栅极引出区设置有通孔， 如图 2b所示， 具体包括：
穿透蚀刻阻挡层 104与栅极绝缘层 102的第二通孔 109和穿透钝化层 106 的第五通孔 111 ;
阵列基板中还包括：漏电极层 105b与透明电极层 107连通的穿透钝化层 106的第四通孔 110。 另外， 需要说明的是， 在以上的说明中 105b称为漏电 极层、 105a称为源电极层。 然而， 场效应晶体管的源电极和漏电极实际上是 对称的结构， 当一者用作源电极， 则另外一者用作漏电极， 而且两者的角色 又可根据情况需要而互换。 因此， 在某些情况下， 105b可以称为源电极层， 而 105a可以称为漏电极层， 这对本发明并不构成限制。
另外， 虽然未示出源极引出区， 但由于源极引出区的源极引出线与源漏 电极层位于同一层， 因此， 其处于栅绝缘层和蚀刻阻挡层之上、钝化层之下， 因此， 在底栅结构中， 源极引出线与其他部件的连接仅需要在钝化层中形成 通孔就可以。 另外， 需要说明的是， 虽然图 2a所示的透明导电层 107和图 2b所示的 透明导电层 107使用了相同的名称和附图标记。 然而， 二者之间可以没有连 接在一起， 并且它们可以具有不同的作用。 例如， 图 2a 的透明电极层 107 可以用作像素电极,但并不限于此；图 2b的透明电极层 107可以用作连接线， 但并不限于此。 此外， 图 2b所示的层 107也可以由不透明的导电材料形成。
如图 3a和图 3b所示， 在顶栅结构中， 设置有用于源电极层、 漏电极层 与有源层连接的通孔， 具体为：
设置有用于有源层与源电极层、 漏电极层连通的穿透蚀刻阻挡层的第一 通孔。
在源极引出区设置有通孔， 如图 3b所示， 具体包括：
穿透蚀刻阻挡层 104与栅极绝缘层 102的第三通孔 112和穿透钝化层 106 的第四通孔 111 ;
阵列基板中还包括： 栅电极层 101与透明电极层 107连通的穿透钝化层 106的第五通孔 110。
在底栅结构中， 填充物 113是在制作源电极层 105a和漏电极层 105b时 同时蚀刻形成，第二通孔中的填充物 113为与源电极层 105a和漏电极层 105b 位于同一层且材质相同的用于进行栅电极层 101 (栅极引线）和透明电极层 107之间过渡连接的金属。
在顶栅结构中， 填充物 113是在制作栅电极层 101时同时蚀刻形成时， 第三通孔中的填充物 113为与栅电极层 101位于同一层且材质相同的用于进 行源极引线和透明电极层 107之间过渡连接的金属。
由于填充物 113和源漏电极层或者栅电极层 101位于同一层， 所以在制 作时， 可以使得填充物 113和源漏电极层或者栅电极层 101表面尽量水平， 以使得第四通孔与第五通孔可以使用相同的深度进行蚀刻， 以便于在进行蚀 刻获得第四通孔和第五通孔时， 进行选择比的设置。
另外， 虽然未示出栅极引出区， 但由于栅极引出区的栅极引出线与栅电 极层位于同一层， 因此， 其处于栅绝缘层和蚀刻阻挡层之上、 钝化层之下， 因此， 在顶栅结构中， 栅极引出线与其他部件的连接仅需要在钝化层中形成 通孔就可以。
通常情况下， 第一通孔的深度与蚀刻阻挡层 104的厚度相同， 或者第一 通孔的深度大于蚀刻阻挡层的厚度 l-60nm, —般来讲， 第一通孔的深度略大 于蚀刻阻挡层 104的厚度， 只要不将有源层 103穿透即可， 以使得源电极层 和漏电极层能够较好的与有源层 103接触；
第二通孔和第三通孔的深度等于蚀刻阻挡层与栅极绝缘层的厚度和， 或 者第二通孔和第三通孔的深度大于蚀刻阻挡层与栅极绝缘层的厚度和 l-100nm, 同样的， 一般情况下， 第二通孔和第三通孔的深度略大于蚀刻阻 挡层与栅极绝缘层的厚度和， 只要不将栅电极层或者源电极层穿透即可， 从 而可以使得过渡连接金属能够较好的与栅电极层或者源电极层接触；
第四通孔和第五通孔的深度等于钝化层的厚度， 或者第二通孔和第三通 孔的深度大于钝化层的厚度 l-100nm, 同样的， 一般情况下， 第四通孔和第 五通孔的深度略大于钝化层的厚度， 只要不将栅电极层或者源电极层穿透即 可， 从而使得透明电极层能够较好的与栅电极层或者源电极层接触。
针对底栅结构， 本发明实施例提供一种阵列基板制造方法， 包括： 步骤 S401、 在基板上依次形成栅电极层 101、 栅极绝缘层 102、 有源层 103以及蝕刻阻挡层 104,蚀刻阻挡层的面积大于或等于有源层的面积，如图 4a、 图 4b所示； 栅电极层 101包括薄膜晶体管的栅电极（如图 4a中的 101 所示 )和位于栅极引出区的栅极引线（如图 4b的 101所示 ) ；
步骤 S402、对蚀刻阻挡层及栅极绝缘层进行蝕刻， 形成用于有源层与源 电极层、 漏电极层连通的穿透蚀刻阻挡层的第一通孔， 如图 4c、 图 4d所示； 步骤 S403、形成源电极层和漏电极层， 源电极层和漏电极层通过第一通 孔连接有源层， 如图 4e、 图 4f所示；
步骤 S404、 形成钝化层， 并对钝化层进行蚀刻， 如图 4g、 图 4h所示； 步骤 S405、形成透明电极层， 透明电极层 107与源电极层连接和栅电极 层连接， 如图 4i、 图 4j所示。
在步骤 S402 中， 在对所述蚀刻阻挡层及栅极绝缘层进行蝕刻， 形成用 于有源层与源电极层、 漏电极层连通的穿透蚀刻阻挡层的第一通孔的同时， 还包括：
形成用于栅电极层（栅极引线）与透明电极层连通的穿透蚀刻阻挡层与 栅极绝缘层的第二通孔（如 4d所示） ；
在形成源电极层和漏电极层的同时， 还在第二通孔上形成与源电极层和 漏电极层材质相同的用于进行栅电极层（栅极引线）和透明电极层之间过渡 连接的填充物（如图 4f中的 113 ) , 该用于进行栅电极层和透明电极层之间 过渡连接的填充物通过第二通孔连接栅电极层（栅极引线） 。
在对蚀刻阻挡层及栅极绝缘层进行蚀刻时， 可以通过过孔的方式， 对蚀 刻阻挡层及栅极绝缘层进行蚀刻。
在步骤 S404中， 对所述钝化层进行蚀刻， 具体为：
对所述钝化层进行蝕刻， 形成用于漏电极层与透明电极层连通的穿透钝 化层的第四通孔（如图 4g所示）， 以及用于栅电极层（栅极引线）与透明电 极层连通的穿透钝化层的第五通孔（如图 4h所示） 。
在步骤 S404 中， 可使得第四通孔和第五通孔的深度相同， 以便于在进 行蚀刻获得第四通孔和第五通孔时， 进行选择比的设置。
具体的， 首先在基板 100上沉积栅电极材料， 并通过光刻图案化制作成 栅电极层 101 ; 在栅电极层 101上设置栅极绝缘层 102, 在栅极绝缘层 102 上形成有源层 103; 在有源层 103和栅极绝缘层 102上沉积蚀刻阻挡层 104, 通过光刻， 在蚀刻阻挡层 104上对需要连接的部位刻孔， 这些部位包括栅电 极层 101引出的地方， 源电极层 105a和漏电极层 105b连接有源层 103两侧 的部位； 接下来在蚀刻阻挡层 104上沉积源漏金属， 进行光刻后形成源电极 层 105a和漏电极层 105b及栅极引出部位的填充物 113, 形成钝化层 106以 及透明电极层 107, 透明电极层 107通过钝化层 106的通孔分别连接源电极 层 105a和栅电极层 101。
在本实施例中， 作为栅电极层 101的材料可选择 Mo (钼）、 Mo b (钼 铌合金） 、 A1 (铝） 、 AlNd (铝钕合金） 、 Ti (钛） 、 Cu (铜） 中的一种或 多种形成的单层或多层复合叠层， 栅电极层 101优先选择 Mo、 A1或含 Mo、 A1的合金组成的单层或多层复合膜。
栅极绝缘层 102, 可以由 SiOx (氧化硅 ) 、 SiNx (氮化硅 ) 、 HfOx (氧 化铪）、 AlOx (氧化铝）或由其中两种或多种组成的多层叠层膜组成。 栅极 绝缘层用特殊的 PECVD (等离子体增强化学气相沉积）技术制作， 其特点 是膜层含有较低的低氢含量、并且栅极绝缘层或有源层表面形成良好的接触， 使绝缘层和有源层之间的化学成分难以互相扩散。 栅极绝缘层的厚度可以控 制在 100nm~400nm, 栅极绝缘层优选 SiOx、 SiNx或两者复合的多层结构。 有源层 103可以由包含 In (铟） 、 Ga (镓） 、 Zn (辞） 、 0 (氧） 、 Sn (锡） 、 非晶硅元素的薄膜制成， 其中薄膜中必须包含氧元素和其他两种或 两种以上的元素， 如 IGZO (氧化铟镓辞） 、 IZO (氧化铟辞） 、 InSnO (氧 化铟锡） 、 InGaSnO (氧化铟镓锡）等。 有源层优先选择 IGZO和 IZO, 厚 度控制在 10~1 OOnm较佳。
蚀刻阻挡层 104可以由 SiOx SiNx HfOx AlOx或由其中两种或三种 组成的多层叠层膜组成。 蚀刻阻挡层特点 层含有较低的低氢含量。 在蚀 刻阻挡层的源电极层、 漏电极层与有源层连接、 栅电极层引出的区域设置通 孔， 用来引出栅电极层、 连接源电极层、 漏电极层和有源层。 在不需要连接 的地方全部可以使用蚀刻阻挡层来覆盖。
源电极层 105a, 漏电极层 105b和填充物 113则是通过溅射法沉积源漏 金属， 再经过光刻形成源电极层、 漏电极层和填充物 113。 源电极层 105a和 漏电极层 105b的材料可以是 Mo MoNb Al AlNd Ti Cu中的一种或多 种材料形成的单层或多层复合叠层， 优先选择 Mo A1或含 Mo A1的合金 组成的单层或多层复合膜。 源电极层 105a和漏电极层 105b通过蚀刻阻挡层 104的通孔与有源层 103连接， 填充物 113通过蚀刻阻挡层 104的通孔与栅 电极层 101连接。 源电极层 105a和漏电极层 105b和填充物 113的厚度为 50~500
钝化层 106, 可以由 SiOx SiNx HfOx AlOx或由其中两种或多种组 成的多层叠层膜组成， 钝化层可以用特殊的 PECVD技术制作， 其特点是膜 层含有较低的低氢含量、 并且有很好的表面特性， 使钝化层和有源层之间的 化学成分难以互相扩散。
在钝化层上是透明电极层 107, 透明电极层 107可以使用 ITO (氧化铟 锡）材料制作， 用溅射成膜的方法制备非晶态的 ITO, 再通过退火使之晶化。 透明电极层 107的厚度为 20~150nm。 透明电极层 107通过第四通孔与源电 极层 105a相连， 通过第五通孔于栅电极层上面的填充物相连。
针对顶栅结构， 本发明实施例还提供一种阵列基板制造方法， 包括： 步骤 S501、 在基板上依次形成源漏电极层、 蚀刻阻挡层， 蚀刻阻挡层的 面积大于或等于有源层的面积，如图 5a和图 5b所示； 源漏电极层包括薄膜 晶体管的源电极层和漏电极层 (如图 5a的 105a和 105b所示）以及位于源极 引出区的源极引线（如图 5b的 105a所示） ；
步骤 S502、 对蚀刻阻挡层进行蚀刻， 形成用于有源层与源电极层、 漏电 极层连通的穿透蚀刻阻挡层的第一通孔；
步骤 S503、形成有源层以及栅极绝缘层， 有源层通过第一通孔连接源电 极层、 漏电极层， 如图 5c-图 5f所示；
步骤 S504、 形成栅电极层， 如图 5g和图 5h所示；
步骤 S505、 形成钝化层， 并对钝化层进行蚀刻， 如图 5i及图 5j所示； 步骤 S506、 形成透明电极层， 透明电极层与栅电极层和漏电极层连接， 如图 5k和图 51所示。
在步骤 S503中， 形成有源层以及栅极绝缘层后， 还包括：
对栅极绝缘层和蚀刻阻挡层进行蚀刻， 形成用于源漏电极层中的源极引 线与透明电极层连通的穿透蚀刻阻挡层与栅极绝缘层的第三通孔（如图 5f 所示） ；
在形成栅电极层的同时， 还在第三通孔上形成与栅电极层材质相同的用 于进行源极引线和透明电极层之间过渡连接的填充物（如图 5h的 113所示）。
对栅极绝缘层和蚀刻阻挡层进行蚀刻， 可以通过过孔的方式， 对栅极绝 缘层和蚀刻阻挡层进行蝕刻。
在步骤 S505中， 对钝化层进行蝕刻， 具体为：
对钝化层进行蝕刻， 形成用于源极引线与透明电极层连通的穿透钝化层 的第四通孔（如图 5j所示 ) , 以及用于栅电极层与透明电极层连通的穿透钝 化层的第五通孔。
在步骤 S505 中， 可以使得第四通孔和第五通孔的深度相同， 以便于在 进行蝕刻获得第四通孔和第五通孔时， 进行选择比的设置。
具体的， 首先在基板 100上设置源电极层 105a和漏电极层 105b, 再在 源电极层 105a和漏电极层 105b上形成刻蚀阻挡层 104, 在刻蚀阻挡层上形 成有源层 103 ,在有源层 103上沉积栅极绝缘层 102, 通过光刻，在栅极绝缘 层上对需要连接的部位刻孔，这些部位包括源电极层 105a引出的地方， 源电 极层 105a和漏电极层 105b连接栅电极层 101的地方， 接下来在栅极绝缘层 102上沉积栅极金属， 对栅极金属光刻后形成栅电极层 101及源电极层 105a 引出部位的填充物 113 ,形成钝化层 106,透明电极 107通过钝化层 106的通 孔分别连接栅电极层 101和源电极层 105a。
各层材料与厚度与底栅结构的实施例一致， 在此不再赘述。
对于以上对底栅结构和顶栅结构的描述中可以知道， 底栅结构中栅极引 出区的栅极引线上面绝缘层层数较多 （栅绝缘层、 蚀刻阻挡层和钝化层） ， 因此， 通过利用与源漏电极层同时形成的过渡连接金属层， 可以使得栅极引 线较易于与其他部件连接； 而对于顶栅极结构， 源极引出区的源极引线（或 者说数据线引线）上面的绝缘层层数较多 (蚀刻阻挡层、栅绝缘层和钝化层）， 因此， 通过利用与栅电极层同时形成的过渡连接金属层， 可以使得栅极引线 较易于与其他部件连接。
本发明实施例还提供一种显示设备，包括本发明实施例提供的阵列基板。 本发明实施例提供一种阵列基板及其制造方法和显示设备， 通过改善蚀 刻阻挡层的设计， 使蚀刻阻挡层的面积大于或等于有源层的面积， 并在源电 、 漏电极层与有源层的连接处设置有通孔， 进而避免源电极层、 漏电极
Figure imgf000012_0001
( 1 )一种阵列基板， 包括：
基板；
位于所述基板上的栅电极层、 栅极绝缘层、 有源层、 蚀刻阻挡层、 源漏 电极层、 钝化层以及透明电极层， 其中：
所述栅电极层包括栅电极， 所述源漏电极层包括源电极层和漏电极层， 以及
所述蝕刻阻挡层的面积大于或等于所述有源层的面积， 并设置有用于源 电极层、 漏电极层与所述有源层连接的第一通孔。
( 2 )如（1 )所述的阵列基板， 其中所述栅电极层还包括位于栅极引出 区域的栅极引出线，所述源漏电极层还包括位于源极引出区域的源极引出线， 且
其中所述蚀刻阻挡层覆盖整个基板， 并在所述栅极引出区或所述源极引 出区设置有通孔。
( 3 )如（2 )所述的阵列基板， 其中在所述栅极引出区或源极引出区的 通孔中设置有导电填充物， 且所述栅极引出线和所述源极引出线通过所述填 充物与所述透明电极层连接。
(4)如（3)所述的阵列基板， 其中所述栅电极、 所述栅绝缘层、 所述 蚀刻阻挡层、 所述源电极层和所述漏电极层构成薄膜晶体管， 且所述薄膜晶 体管为底栅结构，
其中所述栅绝缘层、 所述蚀刻阻挡层和所述钝化层依次覆盖在所述栅极 引出线上， 且在对应于所述栅极引出线的位置处， 具有穿透所述蝕刻阻挡层 和所述栅极绝缘层的第二通孔， 以及穿透所述钝化层的第五通孔。
(5)如（3)所述的阵列基板， 其中所述栅电极、 所述栅绝缘层、 所述 蚀刻阻挡层、 所述源电极层和所述漏电极层构成薄膜晶体管， 且所述薄膜晶 体管为顶栅结构，
其中所述蚀刻阻挡层、 所述栅极绝缘层和所述钝化层依次覆盖在所述源 极引出线以及所述漏电极上， 且在对应于所述源极引出线和所述漏电极的位 置处， 具有穿透所述蚀刻阻挡层和所述栅极绝缘层的第三通孔、 以及穿透所 述钝化层的第四通孔。
(6)如（4)所述的阵列基板， 其中在所述第二通孔中设置有所述导电 填充物， 且所述填充物为与源漏电极层位于同一层且材质相同的金属层。
(7)如（6)所述的阵列基板， 其中所述栅极引出线通过所述导电填充 物以及所述第五通孔与所述透明导电层电连接。
(8)如（5)所述的阵列基板， 其中在所述第三通孔中设置有所述导电 填充物， 且所述填充物为与栅电极层位于同一层且材质相同的金属层。
(9)如（8)所述的阵列基板， 其中所述源极引出线通过所述导电填充 物以及所述第四通孔与所述透明导电层电连接。
( 10 )如（ 1 ) - ( 9 )中任一项所述的阵列基板， 其中 , 所述第一通孔的 深度与所述蝕刻阻挡层的厚度相同， 或者所述第一通孔的深度大于所述蝕刻 阻挡层的厚度。
(11)一种阵列基板制造方法， 包括：
在基板上依次形成栅电极层、 栅极绝缘层、 有源层以及蚀刻阻挡层， 所 述蚀刻阻挡层的面积大于或等于所述有源层的面积， 所述栅电极层包括栅电 极和位于栅极引出区域的栅极引出线；
在所述蝕刻阻挡层中形成第一通孔； 形成源电极层和漏电极层， 所述源电极层和所述漏电极层通过所述第一 通孔与所述有源层连接；
形成钝化层， 并对所述钝化层进行蚀刻； 以及
形成透明电极层， 所述透明电极层与所述漏电极层和所述栅极引出线连 接。
( 12 )如（ 11 )所述的方法， 其中在形成所述第一通孔的同时， 还包括： 形成用于所述栅极引出线与透明电极层连通的穿透所述蚀刻阻挡层与所 述栅极绝缘层的第二通孔； 以及
在形成源电极层和漏电极层的同时， 还在所述第二通孔中形成与所述源 电极层和漏电极层材质相同的用于进行所述栅极引出线和所述透明电极层之 间过渡连接的金属层。
( 13 )如（12 )所述的方法， 其中对所述钝化层进行蝕刻包括： 形成用于所述漏电极层与所述透明电极层连通的穿透钝化层的第四通 孔， 以及用于所述栅极引线层与所述透明电极层连通的穿透钝化层的第五通 孔。
( 14 )如（ 13 )所述的方法， 其中所述第四通孔和第五通孔的深度相同。
( 15 )—种阵列基板制造方法， 包括：
在基板上依次形成源漏电极层和蚀刻阻挡层， 所述源漏电极层包括源电 极层和漏电极层以及位于源极引出区域的源极引出线；
在所述蝕刻阻挡层中对应于所述源电极层和所述漏电极层的位置分别形 成第一通孑 L;
形成有源层以及栅极绝缘层， 所述有源层通过所述第一通孔连接所述源 电极层、 漏电极层， 所述蝕刻阻挡层的面积大于或等于有源层的面积；
形成栅电极层；
形成钝化层， 并对所述钝化层进行蚀刻； 以及
形成透明电极层， 所述透明电极层与所述源极引出线和所述漏电极层连 接。
( 16 )如（15 )所述的方法， 其中在形成所述有源层以及所述栅极绝缘 层后， 还包括：
对所述栅极绝缘层和所述蝕刻阻挡层进行蚀刻， 形成用于所述漏电极层 和所述源极引出线与所述透明电极层连通的穿透蚀刻阻挡层与栅极绝缘层的 第三通孔； 以及
在所述形成所述栅电极层的同时， 还在所述第三通孔中形成与所述栅电 极层材质相同的用于进行所述漏电极层和所述源极引出线与所述透明电极层 之间过渡连接的金属层。
( 17 )如（16 )所述的方法， 其中对钝化层进行蚀刻包括：
形成用于所述漏电极层和所述源极引出线与所述透明电极层连通的穿透 钝化层的第五通孔， 以及用于栅电极层与透明电极层连通的穿透钝化层的第 四通孑
( 18 )如（ 17 )所述的方法， 其中所述第四通孔和第五通孔的深度相同。
( 19 )一种显示设备， 包括如（ 1 ) - ( 10 )任一项所述的阵列基板。 在一个实施例中， 上述第二通孔和第三通孔的深度等于蚀刻阻挡层与栅 极绝缘层的厚度和， 或者第二通孔和第三通孔的深度大于蚀刻阻挡层与栅极 绝缘层的厚度和。
在一个实施例中， 上述第四通孔和第五通孔的深度等于钝化层的厚度， 或者第四通孔和第五通孔的深度大于所述钝化层的厚度。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括：
基板；
位于所述基板上的栅电极层、 栅极绝缘层、 有源层、 蚀刻阻挡层、 源漏 电极层、 钝化层以及透明电极层， 其中：
所述栅电极层包括栅电极， 所述源漏电极层包括源电极层和漏电极层， 以及
所述蝕刻阻挡层的面积大于或等于所述有源层的面积， 并设置有用于源 电极层、 漏电极层与所述有源层连接的第一通孔。
2、如权利要求 1所述的阵列基板，其中所述栅电极层还包括位于栅极引 出区域的栅极引出线， 所述源漏电极层还包括位于源极引出区域的源极引出 线， 且
其中所述蚀刻阻挡层覆盖整个基板， 并在所述栅极引出区或所述源极引 出区设置有通孔。
3、如权利要求 2所述的阵列基板，其中在所述栅极引出区或源极引出区 的通孔中设置有导电填充物， 且所述栅极引出线和所述源极引出线通过所述 填充物与所述透明电极层连接。
4、 如权利要求 3所述的阵列基板， 其中所述栅电极、 所述栅绝缘层、 所 述蚀刻阻挡层、 所述源电极层和所述漏电极层构成薄膜晶体管， 且所述薄膜 晶体管为底栅结构，
其中所述栅绝缘层、 所述蚀刻阻挡层和所述钝化层依次覆盖在所述栅极 引出线上， 且在对应于所述栅极引出线的位置处， 具有穿透所述蝕刻阻挡层 和所述栅极绝缘层的第二通孔， 以及穿透所述钝化层的第五通孔。
5、 如权利要求 3所述的阵列基板， 其中所述栅电极、 所述栅绝缘层、 所 述蚀刻阻挡层、 所述源电极层和所述漏电极层构成薄膜晶体管， 且所述薄膜 晶体管为顶栅结构，
其中所述蚀刻阻挡层、 所述栅极绝缘层和所述钝化层依次覆盖在所述源 极引出线以及所述漏电极上， 且在对应于所述源极引出线和所述漏电极的位 置处， 具有穿透所述蚀刻阻挡层和所述栅极绝缘层的第三通孔、 以及穿透所 述钝化层的第四通孔。
6、如权利要求 4所述的阵列基板，其中在所述第二通孔中设置有所述导 电填充物， 且所述填充物为与源漏电极层位于同一层且材质相同的金属层。
7、如权利要求 6所述的阵列基板，其中所述栅极引出线通过所述导电填 充物以及所述第五通孔与所述透明导电层电连接。
8、如权利要求 5所述的阵列基板，其中在所述第三通孔中设置有所述导 电填充物， 且所述填充物为与栅电极层位于同一层且材质相同的金属层。
9、如权利要求 8所述的阵列基板，其中所述源极引出线通过所述导电填 充物以及所述第四通孔与所述透明导电层电连接。
10、 如权利要求 1-9中任一项所述的阵列基板， 其中， 所述第一通孔的 深度与所述蝕刻阻挡层的厚度相同， 或者所述第一通孔的深度大于所述蝕刻 阻挡层的厚度。
11、 一种阵列基板制造方法， 包括：
在基板上依次形成栅电极层、 栅极绝缘层、 有源层以及蚀刻阻挡层， 所 述蚀刻阻挡层的面积大于或等于所述有源层的面积， 所述栅电极层包括栅电 极和位于栅极引出区域的栅极引出线；
在所述蝕刻阻挡层中形成第一通孔；
形成源电极层和漏电极层， 所述源电极层和所述漏电极层通过所述第一 通孔与所述有源层连接；
形成钝化层， 并对所述钝化层进行蚀刻； 以及
形成透明电极层， 所述透明电极层与所述漏电极层和所述栅极引出线连 接。
12、如权利要求 11所述的方法， 其中在形成所述第一通孔的同时，还包 括：
形成用于所述栅极引出线与透明电极层连通的穿透所述蚀刻阻挡层与所 述栅极绝缘层的第二通孔； 以及
在形成源电极层和漏电极层的同时， 还在所述第二通孔中形成与所述源 电极层和漏电极层材质相同的用于进行所述栅极引出线和所述透明电极层之 间过渡连接的金属层。
13、 如权利要求 12所述的方法， 其中对所述钝化层进行蚀刻包括： 形成用于所述漏电极层与所述透明电极层连通的穿透钝化层的第四通 孔， 以及用于所述栅极引线层与所述透明电极层连通的穿透钝化层的第五通 孔。
14、如权利要求 13所述的方法，其中所述第四通孔和第五通孔的深度相 同。
15、 一种阵列基板制造方法， 包括：
在基板上依次形成源漏电极层和蚀刻阻挡层， 所述源漏电极层包括源电 极层和漏电极层以及位于源极引出区域的源极引出线；
在所述蝕刻阻挡层中对应于所述源电极层和所述漏电极层的位置分别形 成第一通孔；
形成有源层以及栅极绝缘层， 所述有源层通过所述第一通孔连接所述源 电极层、 漏电极层， 所述蝕刻阻挡层的面积大于或等于有源层的面积； 形成栅电极层；
形成钝化层， 并对所述钝化层进行蚀刻； 以及
形成透明电极层， 所述透明电极层与所述源极引出线和所述漏电极层连 接。
16、如权利要求 15所述的方法，其中在形成所述有源层以及所述栅极绝 缘层后， 还包括：
对所述栅极绝缘层和所述蝕刻阻挡层进行蚀刻， 形成用于所述漏电极层 和所述源极引出线与所述透明电极层连通的穿透蚀刻阻挡层与栅极绝缘层的 第三通孔； 以及
在所述形成所述栅电极层的同时， 还在所述第三通孔中形成与所述栅电 极层材质相同的用于进行所述漏电极层和所述源极引出线与所述透明电极层 之间过渡连接的金属层。
17、 如权利要求 16所述的方法， 其中对钝化层进行蝕刻包括： 形成用于所述漏电极层和所述源极引出线与所述透明电极层连通的穿透 钝化层的第五通孔， 以及用于栅电极层与透明电极层连通的穿透钝化层的第 四通孑
18、如权利要求 17所述的方法，其中所述第四通孔和第五通孔的深度相 同。 、 一种显示设备， 包括如权利要求 1-10任一项所述的阵列基板。
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