WO2013083017A1 - 沟槽型绝缘栅双极型晶体管及其制备方法 - Google Patents

沟槽型绝缘栅双极型晶体管及其制备方法 Download PDF

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WO2013083017A1
WO2013083017A1 PCT/CN2012/085714 CN2012085714W WO2013083017A1 WO 2013083017 A1 WO2013083017 A1 WO 2013083017A1 CN 2012085714 W CN2012085714 W CN 2012085714W WO 2013083017 A1 WO2013083017 A1 WO 2013083017A1
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epitaxial layer
igbt
semiconductor substrate
trench
ions
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PCT/CN2012/085714
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English (en)
French (fr)
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唐红祥
孙永生
计建新
马卫清
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无锡华润华晶微电子有限公司
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Priority to US14/363,728 priority Critical patent/US9391182B2/en
Publication of WO2013083017A1 publication Critical patent/WO2013083017A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02499—Monolayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the invention belongs to the technical field of an insulated gate bipolar transistor (IGBT), relates to a method for preparing a trench IGBT, and an IGBT formed by using the preparation method, and particularly relates to a front surface process substantially on a semiconductor substrate.
  • IGBT insulated gate bipolar transistor
  • IGBT is a common power type device, which is one of the mainstream devices for high current switching. It is widely used in high voltage and high current conditions, for example, when the operating voltage is 1200V.
  • the IGBT can be divided into a planar IGBT and a trench IGBT.
  • the front side process and the back side process are included, wherein the front side process is mainly used to complete the gate of the IGBT ( The preparation of Ga te , G ) and the emitter (Emi t ter , E ), the back surface process is mainly used to complete the preparation of the collector (Col lector , C ) of the IGBT.
  • the existing groove type I GBT is mainly formed by the following two methods.
  • the first is to complete the front side process on a single crystal silicon substrate, and then thin the back side of the substrate and multiple times of ion implantation on the back side to form a collector; this method does not depend on the epitaxial process, but relies on high energy ion implantation. And the annealing activation process, the high energy ion implantation equipment has high cost and the process realization cost is relatively high; and the activation rate of the doping source of the collector region formed by ion implantation and annealing is not high, thereby causing the saturation characteristic of the IGBT not to be good.
  • the second method is: epitaxially growing a thick epitaxial layer on a single crystal silicon substrate, and performing a front surface process on the epitaxial layer, and then thinning the silicon substrate on the back surface thereof to form a collector; Use
  • the epitaxial process and the epitaxial layer are mainly used to prepare the IGBT (the buffer layer is formed by the epitaxial layer), the epitaxial layer is relatively thick and the performance of the epitaxial layer is very high (for example, the number of defects), often because the quality of the epitaxial layer is not good enough.
  • the IGBT performance is deteriorated (for example, the overvoltage withstand capability and the overcurrent withstand capability are poor) or the yield is low.
  • One of the objects of the present invention is to improve the performance of a trench type IGBT.
  • Still another object of the present invention is to reduce the manufacturing cost of the trench type IGBT.
  • the present invention provides the following technical solutions.
  • a method of fabricating a trench type IGBT which comprises the steps of:
  • Metallization is performed on the collector region to form a collector.
  • the trench type IGBT is a trench type field stop IGBT
  • the epitaxial growth step includes:
  • a second epitaxial layer for forming a collector region is epitaxially grown on the first epitaxial layer.
  • the second epitaxial layer is thinned.
  • the semiconductor substrate is N-type doped
  • the first epitaxial layer is N-type doped
  • the second epitaxial layer is P-type doped.
  • the doping concentration of the semiconductor substrate ranges from ⁇ 9 ions/cm 3 to ⁇ 15 ions/cm 3 .
  • the doping concentration of the first epitaxial layer ranges from ⁇ 14 ions/cm 3 to ⁇ 22 ions/cm 3
  • the thickness of the first epitaxial layer ranges from
  • the doping concentration of the second epitaxial layer ranges from ⁇ 14 ions/cm 3 to ⁇ 23 ions/cm 3
  • the thickness of the second epitaxial layer ranges from 1 micron to 6G (M glutinous rice.
  • the epitaxial growth temperature ranges from 1100 ° C to 1240 ° C o
  • the collector is a composite layer structure of Al/Ti/Ni/Ag; or a composite layer structure of Ti/Ni/Ag; or Al/V/Ni /Ag composite layer structure.
  • the first side of the semiconductor substrate is polished before the step of epitaxially growing the epitaxial layer.
  • a trench type IGBT which is formed by any of the methods described above.
  • the technical effect of the invention is that the epitaxial growth method forms a collector region on the back surface of the semiconductor substrate, thereby avoiding the process of multiple high-energy ion implantation in the conventional process, which is relatively low in cost and not easily restricted by high-energy ion implantation equipment.
  • the trench IGBT front side process is completed in a semiconductor substrate, and the quality of the semiconductor substrate is superior to that of the epitaxially grown semiconductor layer, and therefore, the device performance of the trench IGBT can be greatly improved (for example, a trench type)
  • the saturation characteristics of the IGBT The epitaxial semiconductor layer is mainly used to form the collector region, and its quality requirements are low, which also reduces the requirements and cost of the epitaxial process. Therefore, the use of the preparation method of the present invention is low in cost and the device performance of the trench IGBT formed is good.
  • Fig. 1 is a flow chart showing a method of fabricating a trench type IGBT according to an embodiment of the present invention.
  • FIGS. 2 to 7 are schematic diagrams showing structural changes when a trench type IGBT is fabricated according to the method flow shown in Fig. 1. detailed description
  • the terms “back”, “front”, “upper” and “lower” are defined relative to the y-coordinate direction defined in the drawing, relative to the IGBT device unit, emitter, gate
  • the direction of the opposite collector is defined as the positive direction of the y coordinate, which is simultaneously perpendicular to the surface of the substrate used to fabricate the IGBT.
  • these directional terms are relative concepts that are used in relation to the description and clarification, which may vary accordingly depending on the orientation in which the IGBT device unit is placed.
  • the direction on the channel of the cross section of the IGBT device unit is defined as the X coordinate direction, that is, the horizontal direction.
  • FIG. 1 is a flow chart showing a method of fabricating a trench type IGBT according to an embodiment of the present invention
  • Fig. 2 through Fig. 7 are schematic diagrams showing changes in structure when a trench type IGBT is fabricated according to the method shown in Fig. 1. An embodiment of the preparation method will be described in detail with reference to Figs.
  • an N-single crystal silicon substrate is provided.
  • the crystal orientation of the N-single-crystal silicon substrate 300 is preferably ⁇ 100>, and the doping concentration thereof is set within the range of ⁇ ⁇ ⁇ 9 ions/cm 3 to ⁇ ⁇ , 1 , for example, The doping concentration may be 6 ⁇ 10 14 ions/cm 3 .
  • Both sides of the N-single-crystal silicon substrate 300 are a front side 302 and a back side 301, which are used to complete the front side process and the back side process of the trench type IGBT, respectively.
  • step S120 an N+ epitaxial layer is epitaxially grown on the back surface of the N-single crystal silicon substrate.
  • an N+ epitaxial layer 310 is grown on the back surface 301 of the N-single-crystal silicon substrate 300 by an epitaxial process, and the N+ epitaxial layer 310 and the N-single-crystal silicon substrate 300 are doped with the same type. Heterogeneous, therefore, it is epitaxial growth of the same type (same conductivity type, that is, the same doping type), and the doping concentration of the N+ epitaxial layer 310 and the like are easily controlled with respect to epitaxial growth of the inversion type.
  • the doping concentration of the N+ epitaxial layer 310 is set in the range of ⁇ ⁇ ⁇ 14 ions/cm 3 to ⁇ ⁇ ⁇ 22 ions/cm 3 (for example, 5 ⁇ 10 18 ions/cm 3 ), and the thickness thereof is in the range of From 0.0001 micrometers to 100 micrometers (e.g., 5 micrometers); the epitaxial furnace growth in the process conditions when epitaxially growing the N+ epitaxial layer 310 ranges from 1100 °C to 1240 °C.
  • the N+ epitaxial layer 310 can ultimately be used to form a Buffer Layer of the trench IGBT.
  • a step of performing single-side polishing of the back surface of the N-single-crystal silicon substrate 300 is performed to accurately perform epitaxial growth.
  • step S130 a P+ epitaxial layer is epitaxially grown on the N+ epitaxial layer.
  • the epitaxial process is used to continue epitaxial growth on the N+ epitaxial layer 310 to form the P+ epitaxial layer 320a.
  • the doping concentration of the P+ epitaxial layer 320a is set in the range of ⁇ ⁇ ⁇ 14 ions/cm 3 to ⁇ ⁇ 23 ions/cm 3 (for example, 7 ⁇ 10 19 ions/cm 3 ), and the thickness thereof is in the range of 1 micrometer to 600 micrometers (for example, 20 micrometers); when the P+ epitaxial layer 320a is epitaxially grown, the specific process conditions are epitaxial furnace growth in a temperature range of 1100 ° C to 1240 ° C.
  • the quality of the epitaxial layer (e.g., the number of defects, etc.) has a relatively small effect on the performance of the trench IGBT, and most of the P+ epitaxial layer 320a is Thinning and removal are required in the subsequent steps. Therefore, the P+ epitaxial layer 320a grown by the epitaxial step has a lower quality requirement than the epitaxial layer of the second method in the background art, and is also advantageous in reducing cost.
  • step S140 a front side process is completed on the front side of the N-single crystal silicon substrate to prepare and form The gate and emitter of the IGBT.
  • an N-drag region of the trench IGBT is formed by the N-single-crystal silicon substrate 300, and a P+ body region 351 is formed on the front side of the N-single-crystal silicon substrate 300, at P+.
  • a trench is patterned in the body region 351 to form a trench, and a gate dielectric layer 353 is grown in the trench, and a gate 354 such as a polysilicon material is further formed in the trench; further on the P+ body region 351, the two sides of the trench are patterned.
  • Doping forms an N+ emitter region 352.
  • two N+ emitter regions 352 are commonly connected to an emitter 355, which is formed by a metallization process.
  • the trench passes through the P+ body region 351 to the N-drift region, and the gate 354 is formed by the trench, and therefore, is referred to as a trench IGBT to form a P+ from the front side of the N-monocrystalline silicon substrate.
  • the body region 351 to form the gate 354 and the emitter 355 are collectively referred to as a front side process, and the body of the trench type IGBT has been substantially formed by the front side process.
  • frontal process steps of the trench IGBT, or the structures specifically formed by the front side process are not limited by the illustrated embodiment of the present invention, and any of the prior art disclosed or disclosed may be used.
  • the front side process and the structure it forms can even use the improved front side process or the structure formed.
  • step S150 a thinning process is performed on the P+ epitaxial layer.
  • the back surface of the P+ epitaxial layer 320a may be thinned by a thinning process such as polishing to form the P+ collector region 320.
  • the doping concentration of the P+ collector region 320 is also set in the range of ⁇ 14 ions/cm 3 to ⁇ 23 ions/cm 3 (for example, 7 ⁇ 10 19 ions/cm 3 ), and the thickness thereof ranges from 1 ⁇ m to 100 ⁇ m. (for example, 5 microns). Therefore, most of the P+ epitaxial layer 320a is thinned and removed in this embodiment.
  • step S160 the back surface is metallized to form a collector.
  • the collector 330 is a composite layer structure of Al/Ti/Ni/Ag, and Al, Ti, Ni, Ag are arranged in order from top to bottom (not shown);
  • the collector 330 is a composite layer structure of Ti/Ni/Ag, and Ti, Ni, and Ag are arranged in order from top to bottom (not shown); in still another embodiment, the collector 330 is A1/.
  • a composite layer structure of V (vanadium) / Ni / Ag, Al, V, Ni, Ag are arranged in order from top to bottom (not shown).
  • FIG. 7 it is to be noted that the cell cells of the plurality of trench IGBTs collectively share one collector 330 in parallel, and the resistance is small.
  • the N-buffer layer and the collector region are formed by two epitaxial growth methods, thereby avoiding the process of multiple high-energy ion implantation in the conventional process, and the relative cost is low. It is not easy to be limited by high-energy ion implantation equipment; in particular, the trench IGBT front side process is completed in a semiconductor substrate exemplified by single crystal silicon, and the quality of the semiconductor substrate is superior to that of the epitaxially grown semiconductor layer, , can greatly improve the device performance of the trench IGBT (for example, the saturation characteristics of the trench IGBT); and, the epitaxial semiconductor layer is mainly used to form the collector region, the quality requirements are relatively low, and the epitaxial process is also reduced. Requirements and costs.
  • the N+ epitaxial layer 310 has a higher doping concentration with respect to the N-drift layer formed by the substrate, according to the Poisson equation, The electric field strength is rapidly terminated in the N+ epitaxial layer 310. It is to be understood that the preparation method of the present invention can also be applied to the preparation of trench type IGBTs of other embodiments, for example, non-field-off type IGBTs which do not include the N+ epitaxial layer 310.

Abstract

提供一种沟槽型绝缘栅双极型晶体管（IGBT）及其制备方法，属于IGBT技术领域，IGBT的制备方法包括步骤：（1）提供半导体衬底；（2）在半导体衬底的第一面上外延生长外延层；（3）在半导体衬底的第二面上制备形成沟槽型IGBT的栅极和发射极；（4）对外延层进行减薄以形成集电区；（5）在集电区上金属化以形成集电极。IGBT的制备方法成本低，制备形成的沟槽型IGBT的器件性能好。

Description

沟槽型绝缘栅双极型晶体管及其制备方法 本申请要求在 2011年 12月 07日提交中国专利局、 申请号为 201110402562.5、 发明名称为
"沟槽型绝缘栅双极型晶体管及其制备方法"的中国专利申请的优先权， 其全部内容通过引用 结合在本申请中。 技术领域
本发明属于绝缘栅双极型晶体管（ Insulated Gate Bipolar Transistor, IGBT ) 技术领域， 涉及沟槽型 IGBT的制备方法以及釆用该制备方法所制备形成的 IGBT, 尤其涉及正面工艺基本在半导体衬底的正面完成、 而背面工艺在半导 体衬底背面生长的外延层中完成的沟槽型 IGBT制备方法。 背景技术
IGBT是一种常见的功率型器件， 其是大电流开关主流器件之一， 广泛应 用于高压大电流情况下， 例如， 应用于工作电压在 1200V的情况下。
IGBT中， 按照栅极的结构类型， IGBT可以分为平面型 IGBT和沟槽型 IGBT, 在制备的过程中， 均包括正面工艺和背面工艺， 其中， 正面工艺主要用来完 成 IGBT的栅极 ( Ga te , G )和发射极（Emi t ter , E ) 的制备， 背面工艺主要用 来完成 IGBT的集电极（Col lector , C ) 的制备。
通常地， 现有的沟槽型 I GBT主要通过以下两种方法制备形成。
第一种是， 在单晶硅衬底上完成正面工艺， 然后对衬底背面减薄、 背面 多次离子注入以引出形成集电极； 这种方法不依赖于外延工艺， 但是依赖于 高能离子注入以及退火激活工艺过程， 高能离子注入的设备成本高、 工艺过 程实现成本也比较高； 并且， 离子注入并退火形成的集电极区的掺杂源的激 活率不高， 进而导致 IGBT的饱和特性不佳。
第二种是， 在单晶硅衬底上反型外延生长较厚的外延层， 并在该外延层 上完成正面工艺， 然后在其背面对硅衬底减薄并形成集电极； 这种方法釆用 外延工艺并且以外延层来主要制备 IGBT (緩冲层以上均由外延层来形成）， 外 延层比较厚并且对外延层的性能要求非常高（例如缺陷数目）， 常常因为外延 层的质量不够好而导致 IGBT性能变差 （例如， 过压承受能力和过电流承受能 力差）或者成品率低。
有鉴于此， 为提高沟槽型 IGBT的性能， 有必要针对沟槽型 IGBT提出一种 新的制备方法。 发明内容
本发明的目的之一在于， 提高沟槽型 IGBT的性能。
本发明的又一目的在于， 降低沟槽型 IGBT的制备成本。
为实现以上目的或者其它目的， 本发明提供以下技术方案。
按照本发明的一方面， 提供一种沟槽型 IGBT的制备方法， 其特征在于， 包括以下步骤：
提供半导体衬底；
在所述半导体衬底的第一面上外延生长外延层；
在所述半导体衬底的第二面上制备形成所述沟槽型 IGBT 的栅极和发射 极；
对所述外延层进行减薄以形成集电区； 以及
在所述集电区上金属化以形成集电极。
按照本发明一优选实施例的制备方法， 其中， 所述沟槽型 IGBT为沟槽型 场截止 IGBT; 并且
所述外延生长步骤中， 包括：
在所述半导体衬底的第一面上外延生长用于形成緩冲层的第一外延层； 以及
在所述第一外延层上外延生长用于形成集电区的第二外延层。
在之前所述实施例的制备方法中， 优选地， 在对所述外延层进行减薄的 步骤中， 对所述第二外延层进行减薄。 在之前所述实施例的制备方法中， 优选地， 所述半导体衬底为 N型掺杂， 所述第一外延层为 N型掺杂， 所述第二外延层为 P型掺杂。
在之前所述实施例的制备方法中， 优选地， 所述半导体衬底的掺杂浓度 范围为 ΙχΙΟ9离子 /cm3至 ΙχΙΟ15离子 /cm3。
在之前所述实施例的制备方法中， 优选地， 所述第一外延层的掺杂浓度 范围为 ΙχΙΟ14离子 /cm3至 ΙχΙΟ22离子 /cm3, 所述第一外延层的厚度范围为
0.0001 ϋ米至 io(M敖米；
在之前所述实施例的制备方法中， 优选地， 所述第二外延层的掺杂浓度 范围为 ΙχΙΟ14离子 /cm3至 ΙχΙΟ23离子 /cm3, 所述第二外延层的厚度范围为 1微 米至 6G(M敖米。
在之前所述实施例的制备方法中， 优选地， 所述外延生长的温度范围为 1100°C至 1240°Co
在之前所述实施例的制备方法中， 优选地， 所述集电极为 Al/Ti/Ni/Ag 的复合层结构； 或者为 Ti /Ni/Ag的复合层结构； 或者为 Al/V/Ni/Ag的复合 层结构。
在之前所述实施例的制备方法中， 优选地， 在外延生长外延层步骤之前， 对所述半导体衬底的第一面进行抛光。
按照本发明的又一方面， 提供一种沟槽型 IGBT, 其通过以上所述及的任 一种方法制备形成。
本发明的技术效果是， 釆用外延生长的办法在半导体衬底的背面形成集 电区， 避免了传统工艺中多次高能离子注入的过程， 相对成本低且不容易受 高能离子注入设备的限制； 并且， 沟槽型 IGBT正面工艺是在半导体衬底中完 成， 半导体衬底的质量优于外延生长的半导体层的质量， 因此， 能大大提高 沟槽型 IGBT的器件性能（例如， 沟槽型 IGBT的饱和特性）； 外延的半导体 层主要用来形成集电区， 其质量要求较低， 也降低了外延工艺的要求及成本。 因此，使用本发明的制备方法成本低、制备形成的沟槽型 IGBT的器件性能好。 附图说明
从结合附图的以下详细说明中， 将会使本发明的上述和其它目的及优点 更加完全清楚， 其中， 相同或相似的要素釆用相同的标号表示。
图 1是按照本发明一实施例的沟槽型 IGBT制备方法的流程示意图。
图 2至图 7是按照图 1所示方法流程制备沟槽型 IGBT时的结构变化示意图。 具体实施方式
下面介绍的是本发明的多个可能实施例中的一些， 旨在提供对本发明的 基本了解， 并不旨在确认本发明的关键或决定性的要素或限定所要保护的范 围。 容易理解， 根据本发明的技术方案， 在不变更本发明的实质精神下， 本 领域的一般技术人员可以提出可相互替换的其它实现方式。 因此， 以下具体 实施方式以及附图仅是对本发明的技术方案的示例性说明， 而不应当视为本 发明的全部或者视为对本发明技术方案的限定或限制。
在附图中， 为了清楚起见， 夸大了层和区域的厚度， 并且， 由于刻蚀引 起的圓润等形状特征未在附图中示意出。
本文中， "背面"、 "正面"、 "上" 和 "下" 等方位术语是相对于附图中的 定义的 y坐标方向来定义的， 相对于 IGBT器件单元来说， 发射极、栅极相对 集电极的方向被定义为 y坐标的正方向， y坐标同时垂直于用于制备该 IGBT 的衬底表面。 并且， 应当理解到， 这些方向性术语是相对的概念， 它们用于 相对于的描述和澄清，其可以根据 IGBT器件单元所放置的方位的变化而相应 地发生变化。另夕卜， IGBT器件单元的截面的沟道上的方向定义为 X坐标方向， 也即水平方向。
图 1所示为按照本发明一实施例的沟槽型 IGBT制备方法的流程示意图； 图 2至图 7所示为按照图 1所示方法流程制备沟槽型 IGBT时的结构变化示意 图。 结合图 1至图 7详细说明该制备方法实施例。
首先， 步骤 110, 提供 N-单晶硅衬底。 如图 2所示， N-单晶硅衬底 300 的晶向优选地为<100>, 其掺杂浓度在 Ι χ ΙΟ9离子 /cm3至 Ι χ ΙΟ1范围内设定，例如，其掺杂浓度可以为 6χ 1014离子 /cm3。 N-单晶硅衬底 300的两面为正面 302和背面 301 ,其分别用来完成沟槽型 IGBT 的正面工艺和背面工艺。
进一步， 步骤 S120 , 在 N-单晶硅衬底的背面外延生长 N+外延层。
如图 3所示， 釆用外延工艺， 在 N-单晶硅衬底 300的背面 301生长一层 N+外延层 310, N+外延层 310与 N-单晶硅衬底 300之间为同类型掺杂，因此， 其为同型 （相同导电类型、 即相同掺杂类型） 的外延生长， 相对于反型的外 延生长， N+外延层 310的掺杂浓度等容易得到控制。 较佳地， N+外延层 310 的掺杂浓度在 Ι χ ΙΟ14离子 /cm3至 Ι χ ΙΟ22离子 /cm3范围内设定（例如， 5χ 1018 离子 /cm3 ), 其厚度范围为 0.0001微米至 100微米（例如 5微米）； 外延生长 N+外延层 310时工艺条件中的外延炉生长的温度范围为 1100 °C至 1240 °C。
N+外延层 310最终可以用来形成沟槽型 IGBT的緩冲层（ Buffer Layer )。 优选地， 在该步骤 120中， 在外延生长之前， 包括对 N-单晶硅衬底 300的背 面进行单面抛光的步骤， 以准确进行外延生长。
进一步， 步骤 S130 , 在 N+外延层上外延生长 P+外延层。
如图 4所示， 釆用外延工艺， 继续在 N+外延层 310上反型生长形成 P+ 外延层 320a。较佳地， P+外延层 320a的掺杂浓度在 Ι χ ΙΟ14离子 /cm3至 Ι χ ΙΟ23 离子 /cm3范围内设定（例如， 7χ 1019离子 /cm3 ), 其厚度范围为 1微米至 600 微米（例如， 20微米）；外延生长 P+外延层 320a时，其具体工艺条件为在 1100 °C 至 1240 °C的温度范围内外延炉生长。
由于该 P+外延层 320a最终是用来形成集电极（ C ), 该外延层的质量（例 如缺陷数目等）对沟槽型 IGBT的性能影响相对较小， 并且， 大部分的 P+外 延层 320a在其后步骤中需要减薄去除， 因此， 对该外延步骤生长形成的 P+ 外延层 320a相对于背景技术中的第二种方法的外延层的质量要求也低， 也有 利于降低成本。
进一步， 步骤 S140 , 在 N-单晶硅衬底的正面完成正面工艺以制备形成 IGBT的栅极和发射极。
如图 5所示， 以 N-单晶硅衬底 300形成沟槽型 IGBT的 N-漂移 （ Drift ) 区，在 N-单晶硅衬底 300正面构图掺杂形成 P+体区 351 ,在 P+体区 351中构 图刻蚀形成沟槽， 并在沟槽内氧化生长栅介质层 353 , 在沟槽内进一步形成诸 如多晶硅材料的栅极 354; 进一步在 P+体区 351上、 沟槽的两旁构图掺杂形 成 N+发射区 352, 在该实例中， 两个 N+发射区 352共同连接于一个发射极 355, 发射极 355通过金属化工艺形成。 在该实例中， 沟槽穿过 P+体区 351 至 N-漂移区， 栅极 354是通过沟槽形成， 因此， 被称为沟槽型 IGBT从在 N- 单晶硅衬底的正面形成 P+体区 351至形成栅极 354和发射极 355 , 统称为正 面工艺， 通过正面工艺， 沟槽型 IGBT的主体已经基本形成。
需要理解的是， 沟槽型 IGBT的具体正面工艺步骤、或者正面工艺过程所 具体形成的结构均不受本发明图示实施例所限制， 其可以釆用现有技术中已 经公开或揭示的任何正面工艺及其形成的结构， 甚至可以釆用将来改进的正 面工艺或其所形成的结构。
进一步， 步骤 S150, 对 P+外延层实施减薄工艺。
如图 6所示，例如可以釆用抛光等减薄工艺对 P+外延层 320a的背面进行 减薄以形成 P+集电区 320。 P+集电区 320的掺杂浓度同样在 Ι χΙΟ14离子 /cm3 至 Ι χΙΟ23离子 /cm3范围内设定（例如， 7χ1019离子 /cm3 ), 其厚度范围为 1微 米至 100微米（例如， 5微米）。 因此， 大部分的 P+外延层 320a在该实施例 中被减薄去除。
进一步， 步骤 S160, 背面金属化以形成集电极。
如图 7所示， 在 P+集电区 320的表面上沉积金属层并金属化以形成集电 极 330。 在一优选实例中， 集电极 330为 Al/Ti/Ni/Ag的复合层结构， Al、 Ti、 Ni、 Ag 由上至下依次排布设置 （图中未示出）； 在又一优选实例中， 集电极 330为 Ti/Ni/Ag的复合层结构， Ti、 Ni、 Ag由上至下依次排布设置（图中未 示出）； 在还一实施例中， 集电极 330为 A1/V (钒） /Ni/Ag的复合层结构， Al、 V、 Ni、 Ag由上至下依次排布设置 （图中未示出）。 至此， 图 1所示实施例的制备方法过程基本结束，从而制备形成了如图 7 所示实施例的沟槽型 IGBT。在图 7所示中，需要说明的是，多个沟槽型 IGBT 的单元元胞共同地并联共用一个集电极 330, 电阻较小。
在图 7所示实施例的沟槽型 IGBT中， 釆用两次外延生长的办法形成 N- 緩冲层和集电区， 避免了传统工艺中多次高能离子注入的过程， 相对成本低 且不容易受高能离子注入设备的限制； 尤其是， 沟槽型 IGBT正面工艺是在以 单晶硅为例的半导体衬底中完成， 半导体衬底的质量优于外延生长的半导体 层的质量， 因此， 能大大提高沟槽型 IGBT的器件性能（例如， 沟槽型 IGBT 的饱和特性）； 并且， 外延的半导体层主要用来形成集电区， 其质量要求相对 较低， 也降低了外延工艺的要求及成本。
图 7所述实施例的沟槽型 IGBT, 沟槽型场截止（Field Stop ) IGBT, N+ 外延层 310相对于衬底形成的 N-漂移层的掺杂浓度更高， 按照泊松方程， 可 以使电场强度在该 N+外延层 310中迅速终止。 需要理解是， 本发明制备方法 还可以应用于其他实施例的沟槽型 IGBT的制备，例如，不包括 N+外延层 310 的非场截止型的 IGBT。
以上例子主要说明了本发明的沟槽型 IGBT 的制备方法以及使用该制备 方法所形成的 。 尽管只对其中一些本发明的实施方式进行了描述， 但是本领 域普通技术人员应当了解， 本发明可以在不偏离其主旨与范围内以许多其他 的形式实施。 因此， 所展示的例子与实施方式被视为示意性的而非限制性的， 在不脱离如所附各权利要求所定义的本发明精神及范围的情况下， 本发明可 能涵盖各种的修改与替换。

Claims

权 利 要 求
1、 一种沟槽型绝缘栅双极型晶体管的制备方法， 其特征在于， 包括以下 步骤：
提供半导体衬底；
在所述半导体衬底的第一面上外延生长外延层；
在所述半导体衬底的第二面上制备形成所述沟槽型绝缘栅双极型晶体管 的栅极和发射极；
对所述外延层进行减薄以形成集电区； 以及
在所述集电区上金属化以形成集电极。
2、 如权利要求 1所述的制备方法， 其特征在于， 所述沟槽型绝缘栅双极 型晶体管为沟槽型场截止绝缘栅双极型晶体管； 并且
所述外延生长步骤中， 包括：
在所述半导体衬底的第一面上外延生长用于形成緩冲层的第一外延层； 以及
在所述第一外延层上外延生长用于形成集电区的第二外延层。
3、 如权利要求 2所述的制备方法， 其特征在于， 在对所述外延层进行减 薄的步骤中， 对所述第二外延层进行减薄。
4、 如权利要求 2所述的制备方法， 其特征在于， 所述半导体衬底为 N型 掺杂， 所述第一外延层为 N型掺杂， 所述第二外延层为 P型掺杂。
5、 如权利要求 4所述的制备方法， 其特征在于， 所述半导体衬底的掺杂 浓度范围为 Ι χΙΟ9离子 /cm3至 Ι χΙΟ15离子 /cm3。
6、 如权利要求 4所述的制备方法， 其特征在于， 所述第一外延层的掺杂 浓度范围为 Ι χΙΟ14离子 /cm3至 Ι χΙΟ22离子 /cm3, 所述第一外延层的厚度范围 为 0.0001微米至 100微米；
7、 如权利要求 4所述的制备方法， 其特征在于， 所述第二外延层的掺杂 浓度范围为 Ι χΙΟ14离子 /cm3至 Ι χΙΟ23离子 /cm3, 所述第二外延层的厚度范围 为 1 米至 600 米。
8、 如权利要求 1所述的制备方法， 其特征在于， 所述外延生长的温度范 围为 1100 °C至 1240°C。
9、如权利要求 1所述的制备方法，其特征在于，所述集电极为 Al/Ti/Ni/Ag 的复合层结构； 或者为 Ti/Ni/Ag的复合层结构； 或者为 Al/V/Ni/Ag的复合层 结构。
10、 如权利要求 1 所述的制备方法， 其特征在于， 在外延生长外延层步 骤之前， 对所述半导体衬底的第一面进行抛光。
11、 一种按照如权利要求 1至 10中任一项所述方法制备形成的沟槽型绝 缘栅双极型晶体管。
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JP2010129697A (ja) * 2008-11-26 2010-06-10 Fuji Electric Systems Co Ltd 半導体装置
US20100193835A1 (en) * 2009-02-05 2010-08-05 Force-Mos Technology Corporation Trench insulated gate bipolar transistor (GBT) with improved emitter-base contacts and metal schemes

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