CN110265476A - 一种igbt芯片及其背面实现方法 - Google Patents
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Abstract
一种IGBT芯片及其背面实现方法。提供了一种用较低成本实现与高能氢注入IGBT的参数一致性,降低了设备依赖性的IGBT芯片及其背面实现方法。包括金属层、BPSG钝化层、POLY层、栅氧化层、N+区和Pbody区,还包括从上到下依次设置的N‑层、N缓冲层、N‑衬底和P+集电极,所述N‑层的厚度范围为4~150um,N缓冲层的厚度范围为5um~30um。本发明通过N‑单晶片二次外延,外延层一为N掺杂(即N缓冲层),外延层二为N‑掺杂,在IGBT正面工艺完成后,进行后续减薄时减薄截至在衬底N‑内,然后注入P+,实现IGBT背面结构。同时,外延N缓冲层浓度分布平直,再加上正面的热过程作用,会形成较小浓度梯度的NN+结,这有利于提高IGBT的动态雪崩能力。
Description
技术领域
本发明涉及半导体器件技术领域,尤其涉及一种IGBT芯片及其背面实现方法。
背景技术
功率半导体器件又称为电力电子器件,是电力电子装置实现电能转换,电路控制的核心器件。主要用途包括变频、整流、变压、功率放大和功率控制等,同时具有节能功效。功率半导体器件广泛应用与移动通讯、消费电子、新能源交通、轨道交通、工业控制以及发电与配电等电力电子领域,涵盖低、中、高各个功率层级。功率半导体种类众多,以IGBT为代表的新型电力电子器件,在能源、交通、工业和消费电子等领域有着不可替代的核心作用。
自从1988年第一代IGBT产品问世以来,目前已经进展到第六代产品,性能方面有显著的提升。目前IGBT发展主流是FS工艺(即FS-IGBT),而FS工艺中高能氢注入工艺在国外应用成熟,也是因为国外部分厂家起步较早,通常与低能核物理研究机构合作,工艺比较成熟,成本较低。国内没有这样的条件,只能购买国外价格较贵的设备来实现此工艺,由于价格昂贵,购买厂家较少。
发明内容
本发明针对以上问题,提供了一种用较低成本实现与高能氢注入IGBT的参数一致性,降低了设备依赖性的IGBT芯片及其背面实现方法。
本发明的技术方案为:包括金属层、BPSG钝化层、POLY层、栅氧化层、N+区和Pbody区,还包括从上到下依次设置的N-层、N缓冲层、N-衬底和P+集电极,所述N-层的厚度范围为4~150um,N缓冲层的厚度范围为5um~30um。
一种IGBT芯片的背面实现方法,包括以下步骤:
1)、在IGBT芯片的N-衬底上分别外延N缓冲层和N-层;
2)、进行IGBT芯片正面工艺;
3)、背面减薄:减薄截至在N-衬底内,减薄后进行去应力清洗,清洗后表面距离N缓冲层厚度0~20um;
4)、P+注入:进行P+注入并激活;
5)、背金:通过背面工艺生长背面金属电极。
步骤1)中,外延N-层的浓度范围为1E13~2E14,厚度范围为4~150um;N缓冲层的浓度范围为1E14~1E16,厚度范围为5um~30um。
步骤2)内的正面工艺为:
2.1)、光刻,刻蚀形成有源区,氧化形成栅氧,并淀积多晶硅;
2.2)、圆胞区光刻,干法刻蚀,形成圆胞区,硼离子注入并推结,形成Pbody;
2.3)、砷离子注入,退火激活,形成N+区;
2.4)BPSG淀积,引线孔光刻刻蚀,正面金属淀积,金属光刻刻蚀,形成正面电极。
本发明通过N-单晶片二次外延,外延层一为N掺杂(即N缓冲层), 外延层二为N-掺杂,在IGBT正面工艺完成后,进行后续减薄时减薄截至在衬底N-内,然后注入P+,实现IGBT背面结构。由于减薄在N-层内,N型掺杂总量因为减薄导致的偏差与高能氢注入的相同,因此,可实现与高能氢注入形成缓冲层的IGBT的参数(IGBT动静态参数特性,比如正向压降、开关时间、开关能量)相同。
同时,由于氢注入本身特点,射程末端剂量最高,因此氢注入形成的缓冲层NN+结浓度梯度较高,即具有明显的NN+结;而外延N缓冲层浓度分布平直,再加上正面的热过程作用,会形成较小浓度梯度的NN+结,这有利于提高IGBT的动态雪崩能力。
附图说明
图1是本发明的结构示意图,
图2是步骤1)的结构及浓度示意图,
图3是步骤3)的结构及浓度示意图,
图4是步骤4)的结构及浓度示意图;
图中1是N-衬底,2是N缓冲层,3是N-层,4是P+集电极,5是金属层,6是BPSG钝化层,7是POLY层,8是栅氧化层,9是N+区,10是Pbody区。
具体实施方式
本发明如图1-4所示,包括金属层5、BPSG钝化层6、POLY层7、栅氧化层8、N+区9和Pbody区10,还包括从上到下依次设置的N-层3、N缓冲层2、N-衬底1和P+集电极4,所述N-层的厚度范围为4~150um,N缓冲层的厚度范围为5um~30um。
一种IGBT芯片的背面实现方法,包括以下步骤:
1)、在N-衬底上外延N和N-,其中外延N-浓度范围为1E13~2E14,厚度取决于芯片耐压,范围为4~150um,N浓度范围为1E14~1E16,厚度范围为5um~30um,见图1,图1左边为结构,右边为浓度分布;
2)、进行IGBT正面工艺:
光刻,刻蚀形成有源区,氧化形成栅氧,并淀积多晶硅;
圆胞区光刻,干法刻蚀,形成圆胞区,硼离子注入并推结,形成Pbody;
砷离子注入,退火激活,形成N+区;
BPSG淀积,引线孔光刻刻蚀,正面金属淀积,金属光刻刻蚀,形成正面电极;
3)、背面减薄:在完成正面工艺后进行背面减薄,减薄截至在N-衬底内,减薄后进行去应力清洗,清洗后表面距离N缓冲层厚度0~20um(即大于0);见图2,图2左侧为结构图,右侧为浓度分布;应力清洗用于去除机械研磨造成的损伤层;
4)、P+注入:进行P+注入并激活;见图3,图3左侧为结构图,右侧为浓度分布;
5)、背金:按常规IGBT背金工艺生长背面金属电极。
本发明通过在N-衬底外延N和N-,在背面减薄时截至在衬底N-内,从而实现良好的IGBT参数一致性。
高能氢注入工艺是离子注入工艺,其注入的元素是氢离子,氢离子注入硅中在合适的退火温度下会形成N型掺杂, 目前,多用其形成功率器件的缓冲层,由于缓冲层截止电场的需求,需要一定的深度,通常在15-25um的范围,这需要1Mev以上的能量,所以通常称为高能氢注入工艺。
本案通过与高能氢注入结果进行比较,用较低成本实现了与高能氢注入IGBT相同的参数,降低了设备依赖性;同时,较小的NN+结浓度梯度具有比氢注入更好的动态雪崩能力。
对于本案所公开的内容,还有以下几点需要说明:
(1)、本案所公开的实施例附图只涉及到与本案所公开实施例所涉及到的结构,其他结构可参考通常设计;
(2)、在不冲突的情况下,本案所公开的实施例及实施例中的特征可以相互组合以得到新的实施例;
以上,仅为本案所公开的具体实施方式,但本公开的保护范围并不局限于此,本案所公开的保护范围应以权利要求的保护范围为准。
Claims (4)
1.一种IGBT芯片,包括金属层、BPSG钝化层、POLY层、栅氧化层、N+区和Pbody区,其特征在于,还包括从上到下依次设置的N-层、N缓冲层、N-衬底和P+集电极,所述N-层的厚度范围为4~150um,N缓冲层的厚度范围为5um~30um。
2.一种权利要求1所述的IGBT芯片的背面实现方法,其特征在于,包括以下步骤:
1)、在IGBT芯片的N-衬底上分别外延N缓冲层和N-层;
2)、进行IGBT芯片正面工艺;
3)、背面减薄:减薄截至在N-衬底内,减薄后进行去应力清洗,清洗后表面距离N缓冲层厚度0~20um;
4)、P+注入:进行P+注入并激活;
5)、背金:通过背面工艺生长背面金属电极。
3.根据权利要求2所述的一种IGBT芯片的背面实现方法,其特征在于,步骤1)中,外延N-层的浓度范围为1E13~2E14,厚度范围为4~150um;N缓冲层的浓度范围为1E14~1E16,厚度范围为5um~30um。
4.根据权利要求2所述的一种IGBT芯片的背面实现方法,其特征在于,步骤2)内的正面工艺为:
2.1)、光刻,刻蚀形成有源区,氧化形成栅氧,并淀积多晶硅;
2.2)、圆胞区光刻,干法刻蚀,形成圆胞区,硼离子注入并推结,形成Pbody;
2.3)、砷离子注入,退火激活,形成N+区;
2.4)、BPSG淀积,引线孔光刻刻蚀,正面金属淀积,金属光刻刻蚀,形成正面电极。
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JPH06112494A (ja) * | 1992-09-29 | 1994-04-22 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
CN103151251A (zh) * | 2011-12-07 | 2013-06-12 | 无锡华润华晶微电子有限公司 | 沟槽型绝缘栅双极型晶体管及其制备方法 |
CN104078354A (zh) * | 2013-03-26 | 2014-10-01 | 杭州士兰集成电路有限公司 | 功率半导体器件及其制造方法 |
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JPH06112494A (ja) * | 1992-09-29 | 1994-04-22 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
CN103151251A (zh) * | 2011-12-07 | 2013-06-12 | 无锡华润华晶微电子有限公司 | 沟槽型绝缘栅双极型晶体管及其制备方法 |
CN104078354A (zh) * | 2013-03-26 | 2014-10-01 | 杭州士兰集成电路有限公司 | 功率半导体器件及其制造方法 |
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