WO2015019797A1 - 高耐圧半導体装置およびその製造方法 - Google Patents
高耐圧半導体装置およびその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 244
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 239000010410 layer Substances 0.000 claims abstract description 303
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 239000002344 surface layer Substances 0.000 claims abstract description 23
- 230000008878 coupling Effects 0.000 claims abstract description 9
- 238000010168 coupling process Methods 0.000 claims abstract description 9
- 238000005859 coupling reaction Methods 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 claims description 54
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 43
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 30
- 238000005468 ion implantation Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 239000012535 impurity Substances 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 230000005684 electric field Effects 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 238000005259 measurement Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- -1 nitrogen ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Definitions
- the present invention relates to a power semiconductor device capable of controlling a high breakdown voltage and large current, and more particularly to a vertical high breakdown voltage semiconductor device using silicon carbide, which is one of wide band gap materials, as a semiconductor, and a method for manufacturing the same.
- a silicon single crystal has been used as a material of a power semiconductor element that controls a high breakdown voltage and a large current.
- power semiconductor elements There are several types of power semiconductor elements, and the current situation is that they are properly used according to the application.
- bipolar transistors and IGBTs insulated gate bipolar transistors
- the use limit is a frequency of several kHz for bipolar transistors and a frequency of about 20 kHz for IGBTs. .
- the power MOSFET can be used for high-speed switching up to a frequency of several MHz, although a large current cannot be obtained.
- IGBTs and power MOSFETs there is a strong demand for power devices having both high current and high speed in the market, and efforts have been made to improve IGBTs and power MOSFETs. At present, development has progressed to almost the limit of materials.
- FIG. 17 is a cross-sectional view showing a conventional MOSFET.
- An n ⁇ drift layer 2 is stacked on the n + type semiconductor substrate 1.
- a p base layer 3 is selectively formed on the surface layer of the n ⁇ drift layer 2.
- An n + source layer 4 is selectively formed on the surface layer of the p base layer 3, and a gate electrode is formed on the n ⁇ drift layer 2, the p base layer 3, and the n + source layer 4 via a gate insulating film 6. 7 is formed.
- MOSFETs (hereinafter referred to as super-junction MOSFETs) in which the drift layer is a parallel pn layer in which n-type regions and p-type regions with increased impurity concentration are alternately arranged are attracting attention. .
- FIG. 18 is a cross-sectional view of a conventional silicon superjunction MOSFET.
- FIG. 19 is a cross-sectional view of a silicon superjunction MOSFET formed by a conventional multistage epitaxial method.
- FIG. 20 is a cross-sectional view of a silicon super-junction MOSFET by a conventional trench filling method.
- Non-Patent Document 1 It is known that Fujihira published this theory in 1997 (see Non-Patent Document 1 below) and was commercialized as a CoolMOSFET by Deboy et al. In 1998 (see Non-Patent Document below). Reference 2). These are characterized in that the on-resistance can be remarkably improved without degrading the breakdown voltage characteristics between the source and drain by forming a p-layer in a columnar structure in the vertical direction (in the substrate depth direction) in the n ⁇ drift layer. Yes.
- SiC silicon carbide
- SiC is a low power on-chip as a next-generation power semiconductor element.
- SiC is a chemically very stable material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures.
- SiC has a maximum electric field strength that is one order of magnitude greater than that of silicon. Since SiC is likely to exceed the material limit of silicon, future growth is expected greatly in power semiconductor applications, particularly MOSFETs.
- the on-resistance is expected to be small, but a vertical SiC-MOSFET having a further low on-resistance while maintaining high withstand voltage characteristics can be expected.
- the cross-sectional structure of a general SiC-MOSFET is the same as that shown in FIG.
- a p base layer 3 is selectively formed on the surface layer of the n ⁇ drift layer 2.
- An n + source layer 4 selectively formed on the surface layer of the p base layer 3 is formed, and a gate insulating film 6 is interposed on the n ⁇ drift layer 2 and the p base layer 3 and the n + source layer 4.
- the gate electrode 7 is formed, and the drain electrode 8 is formed on the back surface of the semiconductor substrate 1.
- the SiC-MOSFET formed in this way is expected to be used as a switching device and as an element capable of high-speed switching with low on-resistance in power converters such as motor control inverters and uninterruptible power supplies (UPS). ing.
- the breakdown electric field strength is about 10 times as high as that of silicon and the on-resistance is sufficiently low.
- the breakdown electric field strength of the semiconductor is about 10 times higher. For this reason, the load of the electric field on the oxide film particularly when a high voltage is applied becomes larger than that of the silicon element.
- the oxide film may be destroyed due to the SiC that does not become a problem because the breakdown electric field strength of silicon is reached before a large electric field is applied to the oxide film.
- a large electric field strength is applied to the gate oxide film 6 of the SiC-MOSFET shown in FIG. 1, which may cause a serious problem in gate oxide film destruction and reliability. This is true not only for SiC-MOSFETs but also for SiC-IGBTs.
- Patent Document 1 there is a document that describes a need to pay attention to the electric field strength to the gate oxide film in the SiC-MOSFET (see Patent Document 1 above).
- an object of the present invention is to provide a high breakdown voltage semiconductor device having a low on-resistance, a large breakdown resistance, and a high-speed switching characteristic, and a manufacturing method thereof.
- a high breakdown voltage semiconductor device of the present invention includes a first conductivity type semiconductor substrate, and a first concentration formed on the first conductivity type semiconductor substrate and having a lower concentration than the first conductivity type semiconductor substrate.
- a second conductive type low concentration semiconductor layer having a lower concentration than the second conductive type high concentration semiconductor layer formed on the semiconductor layer and a surface layer of the second conductive type low concentration semiconductor layer are selectively formed.
- the first conductivity type source region and the first conductivity type semiconductor substrate are formed so as to penetrate the second conductivity type low concentration semiconductor layer and reach the first conductivity type semiconductor layer from the front surface of the first conductivity type semiconductor substrate.
- a part of the second conductivity type high concentration semiconductor layer Are coupled by a coupling portion in a region on the drain electrode side of the first conductivity type well region, and are formed so as to be in contact with a part of the second conductivity type high concentration semiconductor layer on the drain electrode side. It has a two-conductivity type high concentration region.
- the high withstand voltage semiconductor device of the present invention includes a first conductive semiconductor substrate, a first conductive semiconductor layer formed on the first conductive semiconductor substrate and having a lower concentration than the first conductive semiconductor substrate.
- the second conductivity type low concentration semiconductor layer selectively formed on the surface of the first conductivity type semiconductor layer, and the first conductivity type selectively formed on the surface layer of the second conductivity type low concentration semiconductor layer
- a source region and a first conductivity type well region formed so as to penetrate the second conductivity type low-concentration semiconductor layer from the front surface of the first conductivity type semiconductor substrate to reach the first conductivity type semiconductor layer
- a gate electrode layer provided on a surface exposed portion of the second conductivity type low concentration semiconductor layer sandwiched between the first conductivity type source region and the first conductivity type well region via a gate insulating film;
- the first conductivity type source region and the second conductivity type low concentration semiconductor layer In a vertical high voltage semiconductor device having a source electrode in contact with a drain electrode and a drain electrode provided on the back surface of the first conductive
- the source electrode is provided so as to be embedded in the trench.
- the high breakdown voltage semiconductor device may further include a trench that reaches the second conductivity type high concentration region from the front surface side through the second conductivity type low concentration semiconductor layer, and the source electrode includes the source electrode, It is provided so as to be embedded inside the trench.
- the material of the first conductivity type semiconductor substrate is silicon carbide.
- the crystallographic plane index of the first conductivity type semiconductor substrate is a plane parallel to (000-1) or a plane tilted within 10 degrees. .
- the crystallographic plane index of the first conductive type semiconductor substrate is a plane parallel to (0001) or a plane tilted within 10 degrees.
- the high breakdown voltage semiconductor device manufacturing method of the present invention includes a first step of epitaxially growing a first conductivity type semiconductor layer having a lower concentration than the first conductivity type semiconductor substrate on the first conductivity type semiconductor substrate, A second step of selectively forming a second conductivity type high concentration region in the surface layer of the first conductivity type semiconductor layer by ion implantation; and a surface layer of the first conductivity type semiconductor layer by ion implantation.
- the second conductivity type high concentration semiconductor layer is formed so that a part of the second conductivity type high concentration semiconductor layer is coupled in a region under the first conductivity type well region. It is characterized by that.
- a trench groove is formed from a surface of the first conductivity type semiconductor layer, and the second conductivity type high concentration region is formed on a bottom surface of the trench groove. Is formed by an ion implantation method.
- a method of manufacturing a high breakdown voltage semiconductor device comprising: epitaxially growing a first conductive semiconductor layer having a concentration lower than that of the first conductive semiconductor substrate on the first conductive semiconductor substrate; A step of selectively forming a second conductivity type high concentration region on the surface of the first conductivity type semiconductor layer by an ion implantation method; and on the first conductivity type semiconductor layer and the second conductivity type high concentration region, A step of selectively forming a second conductivity type low concentration semiconductor layer by an ion implantation method, a first conductivity type source region selectively on a surface layer of the second conductivity type low concentration semiconductor layer, and a front surface side; Forming a first conductivity type well region having a depth not penetrating through the second conductivity type low concentration semiconductor layer in the second conductivity type low concentration semiconductor layer by an ion implantation method.
- a method of manufacturing a high breakdown voltage semiconductor device comprising: epitaxially growing a first conductive semiconductor layer having a concentration lower than that of the first conductive semiconductor substrate on the first conductive semiconductor substrate; A step of selectively forming a second conductivity type low-concentration semiconductor layer on the surface of the first conductivity type semiconductor layer by an ion implantation method; Forming a first source region, and ion-implanting the first conductivity type well region from the front surface side into the second conductivity type low concentration semiconductor layer at a depth not penetrating the second conductivity type low concentration semiconductor layer Forming a trench groove reaching the first conductivity type semiconductor layer from the surface of the second conductivity type low concentration semiconductor layer, and forming the second conductivity type low concentration semiconductor layer on a bottom surface of the trench groove. 2nd so that it touches part of the lower part And having a step of forming by a conductivity type region ion implantation.
- the gate oxide film on the n type semiconductor well region (n counter layer) Therefore, even when a high voltage is applied between the source and the drain (a source is applied with 0 V and a + voltage is applied to the drain), a sufficient device breakdown voltage can be maintained. Even when the distance between the second conductivity type high-concentration semiconductor layers and between the second conductivity type low-concentration semiconductor layers is increased to reduce the on-resistance sufficiently, the gate oxide film on the first conductivity type well region is greatly increased. A sufficient device breakdown voltage can be maintained without applying an electric field.
- the electric field strength is relaxed, so that a large element breakdown tolerance can be exhibited.
- the depletion layer extending from the pn junction between the second conductivity type low concentration semiconductor layer and the second conductivity type high concentration semiconductor layer and the first conductivity type well region to the first conductivity type well region is the second conductivity type high concentration. This is because it tends to spread laterally along the semiconductor layer.
- the depletion layer is designed to spread easily, so the second conductive type high-concentration semiconductor layer And the distance between the second conductivity type low-concentration semiconductor layers can be widened to reduce the on-resistance while maintaining sufficient element breakdown voltage and element breakdown resistance.
- the second conductivity type low-concentration semiconductor layer of the present invention when the second conductivity type low-concentration semiconductor layer of the present invention is formed by the epitaxial growth method, it can be flattened so that there is almost no surface roughness, so that the mobility of the MOSFET portion on the surface becomes extremely large, and as a result, the on-resistance Can be further reduced.
- the crystallographic plane index of the first conductive type semiconductor substrate is a plane parallel to (000-1) or within 10 degrees, or the first conductive type semiconductor substrate.
- FIG. 1 is a sectional view of a SiC-MOSFET manufacturing process according to embodiment 1 of the present invention (part 1).
- FIG. 2 is a cross-sectional view of the SiC-MOSFET manufacturing process according to Example 1 of the present invention (No. 2).
- FIG. 3 is a sectional view of the SiC-MOSFET manufacturing process according to the first embodiment of the present invention (part 3).
- FIG. 4 is a sectional view of the SiC-MOSFET manufacturing process according to Example 1 of the present invention (No. 4).
- FIG. 5 is a sectional view of the SiC-MOSFET manufacturing process according to the first embodiment of the present invention (No. 5).
- FIG. 5 is a sectional view of the SiC-MOSFET manufacturing process according to the first embodiment of the present invention (No. 5).
- FIG. 6 is a sectional view of the SiC-MOSFET manufacturing process according to the example 1 of the present invention (part 6).
- FIG. 7 is a sectional view of the SiC-MOSFET manufacturing process according to Example 1 of the present invention (No. 7).
- FIG. 8A is a plan view showing the arrangement of p + layers and cells of the SiC-MOSFET according to Example 1 of the present invention.
- FIG. 8B is a plan view illustrating a comparison between the p + layer and the cell arrangement of the SiC-MOSFET according to the first example of the present invention and the conventional plan view.
- FIG. 9 is a chart showing measurement results of electrical characteristics of the SiC-MOSFETs of the respective examples.
- FIG. 10 is a table showing the breakdown voltage performance of the SiC-MOSFET according to Example 1 of the present invention.
- FIG. 11 is a table showing the measurement results of the load short-circuit withstand capability of the SiC-MOSFET according to Example 1 of the present invention.
- FIG. 12 is a table showing the evaluation results of the turn-off breakdown resistance of the SiC-MOSFET according to Example 1 of the present invention.
- FIG. 13 is a cross-sectional view of an SiC-MOSFET according to Example 2 of the present invention.
- FIG. 14 is a plan view showing the arrangement of p + layers and cells of the SiC-MOSFET according to Embodiment 9 of the present invention.
- FIG. 15 is a turn-off switching waveform of the SiC-MOSFET of each embodiment of the present invention.
- FIG. 16 is a turn-on switching waveform of the SiC-MOSFET according to each embodiment of the present invention.
- FIG. 17 is a cross-sectional view showing a conventional MOSFET.
- FIG. 18 is a cross-sectional view of a conventional silicon superjunction MOSFET.
- FIG. 19 is a cross-sectional view of a silicon superjunction MOSFET according to a conventional multistage epitaxial method.
- FIG. 20 is a cross-sectional view of a silicon super-junction MOSFET by a conventional trench filling method.
- FIG. 1 to 7 are cross-sectional views of an SiC-MOSFET manufacturing process according to the first embodiment of the present invention.
- (a) is a cross-sectional view of a portion where the p + layer 3 is not bonded
- (b) is a cross-sectional view of a portion where the p + layer 3 is bonded.
- the vertical planar gate MOSFET a silicon carbide is used as a semiconductor material, and a MOSFET having an element withstand voltage of 1200 V is shown.
- an n + type SiC semiconductor substrate 1 is prepared.
- a low resistance n + type SiC semiconductor substrate 1 containing about 2 ⁇ 10 19 cm ⁇ 3 of nitrogen as an impurity is used.
- An n ⁇ type SiC layer containing about 1.0 ⁇ 10 16 cm ⁇ 3 of nitrogen on a surface inclined by about 4 ° with respect to the crystallographic plane index (000-1) of the n + type SiC semiconductor substrate 1 2 is epitaxially grown by about 10 ⁇ m.
- a p + layer 31 having a width of 2 ⁇ m and a depth of 0.3 ⁇ m is selectively formed on the surface layer of the n ⁇ -type SiC layer 2 by an ion implantation method. Thereafter, the acceleration energy is decreased, and a p + layer 3 having a width of 13 ⁇ m and a depth of 0.5 ⁇ m is formed by ion implantation. In this case, aluminum was used as the ion. Further, the p + layer 31 is arranged at the center of the p + layer 3. The doses were set so that the impurity concentrations of the p + layer 31 and the p + layer 3 were 1.0 ⁇ 10 18 cm ⁇ 3 .
- a part of the p + layer 3 is coupled to each other by a coupling portion 13 (see FIGS. 8A and 8B) under the n-turnback layer 6 (drain electrode side) formed in a later step.
- the impurity at that time was aluminum, and the impurity concentration was set to 5.0 ⁇ 10 16 cm ⁇ 3 .
- nitrogen ions are 5.0 ⁇ 10 16 cm ⁇ 3 in depth and 1.5 ⁇ m in width as an n-repelling layer 6 formed by ion-implanting a part of the p base layer 4 into an n-type.
- pour so that it may become 2.0 micrometers.
- n + source layer 7 and p + contact layer 5 are selectively formed in p base layer 4. Thereafter, activation annealing is performed.
- the heat treatment temperature and time are 1800 ° C. and 2 minutes.
- a gate oxide film having a thickness of 100 nm is formed by thermal oxidation and annealed in the vicinity of 1000 ° C. in a hydrogen atmosphere.
- a polycrystalline silicon layer doped with phosphorus is formed and patterned as the gate electrode 8.
- a phosphor glass is formed to a thickness of 1.0 ⁇ m, and after the patterning, heat treatment is performed, and aluminum containing 1% silicon is formed on the surface to a thickness of 5 ⁇ m by sputtering.
- the source electrode 10 is formed to be in contact with the surfaces of the p + contact layer 5 and the n + source layer 7 in common.
- a nickel film was formed on the back surface of the element, and after heat treatment at 970 ° C., Ti / Ni / Au was sequentially formed as the back electrode (drain electrode) 11. Then, a protective film is added to the surface on the source electrode 10 side to complete the device.
- FIG. 8A is a plan view showing the arrangement of p + layers and cells of the SiC-MOSFET according to Example 1 of the present invention.
- FIG. 8B is a plan view illustrating a comparison between the p + layer and the cell arrangement of the SiC-MOSFET according to the first example of the present invention and the conventional plan view.
- the source electrode, the gate electrode, and the gate oxide film are not shown.
- the p + layer 3 and the p + layer 3 under the p base layer 4 are connected by the coupling portion 13.
- FIG. 8B shows the base pattern of the p + layer 3.
- p + layer 3 at hexagonal cell pattern may be other polygonal shapes such as square cell.
- the distance between the p + layers 3 that are not bonded to each other was 2 ⁇ m.
- n ⁇ type SiC layer 2 and n type semiconductor well region (n counter layer) 6 are greatly increased to reduce the on-resistance sufficiently, or between p + layer 3 and p
- the on-resistance is sufficiently lowered by increasing the distance between the base layers 4, even when a high voltage is applied between the source and the drain (the source is applied with 0V and the drain is applied with a + voltage), the n-type semiconductor well region (n A large electric field is not applied to the gate oxide film on the return layer 6 and a sufficient device breakdown voltage can be maintained.
- the electric field strength is alleviated, so that a large element breakdown tolerance can be exhibited. This is because the easily spread laterally depletion layer extending to the n-type semiconductor well region 6 from the pn junction between the p base layer 4 and p + layer 3 and the n-type semiconductor well region 6 along the p + layer 3 It is.
- the depletion layer is easy to spread, and therefore between the p + layers 3 and the p base layer 4
- the on-resistance can be reduced while the element breakdown voltage and the element breakdown tolerance are sufficiently maintained by increasing the distance between the two.
- the p base layer 4 of the present invention when the p base layer 4 of the present invention is formed by the epitaxial growth method, it can be made flat so that there is almost no surface roughness, so that the mobility of the MOSFET portion on the surface becomes extremely high, and as a result, the on-resistance is further reduced. be able to.
- FIG. 9 is a table showing the measurement results of the electrical characteristics of the SiC-MOSFET of each example (1200 V / 25 A element).
- the chip size of Example 1 is 3 mm square, the area of the active region is 5.27 mm 2 , and the rated current is 25A.
- An active region is a region through which current flows when in an on state.
- the device breakdown voltage and on-resistance at room temperature (RT), the on-resistance (RonA) is 3.2Emuomegacm 2 and shows a sufficiently low value, the initial element withstand voltage and 1450V, enough good characteristics as 1200V element Is shown.
- RT room temperature
- RonA on-resistance
- FIG. 10 is a table showing the breakdown voltage performance of the SiC-MOSFET according to Example 1 of the present invention.
- the vertical axis represents the element breakdown voltage (V), and the horizontal axis represents the width of the n-turnback layer 6, that is, the interval ( ⁇ m) between the p + layers 3.
- V element breakdown voltage
- ⁇ m the interval between the p + layers 3.
- Example 1 of the present invention achieves a high breakdown voltage characteristic of 1400 V or higher, which is a sufficient breakdown voltage characteristic for a 1200 V device.
- the on-resistance at this time was the same under both conditions.
- the distance between the p + layers 3 is set to 1.0 ⁇ m or less, and n ⁇ repulsion is performed. It has been found that the impurity concentration of the layer 6 must be reduced to one fifth.
- the on-resistance at that time was an extremely high value of 12.8 m ⁇ cm 2 . That is, the present invention can improve the on-resistance and the element breakdown voltage characteristics at the same time.
- Japanese Patent No. 3214274 discloses an example in which the element breakdown voltage is prevented from deteriorating by connecting adjacent p base layers.
- this method eliminates the surface accumulation layer of the connected portion by partially connecting the p base layers, and as a result, the MOSFET of the connected portion does not operate. As a result, the on-resistance increases.
- the present invention does not connect the p base layer 4, so connecting the p + layer 3, will be the surface accumulation layer remains, as a result, on-resistance is to be sufficiently low.
- an element in which the p base layer 4 is connected instead of the p + layer 3 was prototyped and the characteristics were evaluated. As a result, the on-resistance was 5.0 m ⁇ cm 2 and deteriorated by about 50% although the breakdown voltage was unchanged from 1440 V did.
- FIG. 11 is a chart showing the measurement results of the load short-circuit withstand capability of the SiC-MOSFET according to Example 1 of the present invention.
- the horizontal axis represents time
- the vertical axis represents current and voltage values
- the power supply voltage Vds 800 V
- Tj is 175 ° C.
- Ip 125A, whose maximum current is 5 times the element rating, was not broken even if it was made conductive, and even if it was 15 ⁇ sec.
- FIG. 12 is a table showing evaluation results of turn-off breakdown resistance of the SiC-MOSFET according to Example 1 of the present invention.
- the horizontal axis represents time, and the vertical axis represents current and voltage values.
- the source-drain voltage was clamped at 1650 V (Vdsclamp in FIG. 12), and it was confirmed that 100 A (four times the rated current) could be turned off at 150 ° C. without breaking. From this, it can be said that the element of the present invention realizes a low on-resistance, and has an extremely large load short-circuit resistance and turn-off resistance.
- the tolerances of various SiC-MOSFETs manufactured for comparison were evaluated, the element breakdown voltage and the turn-off tolerance were not sufficient, so both the load short-circuit tolerance and the turn-off tolerance were the elements of Example 1. The result was greatly inferior.
- n + -type SiC semiconductor substrate 1 has a crystallographic plane index that is similarly formed on a surface inclined at 0 °, 2 °, 8 °, and 10 ° with respect to (000-1). When the device was evaluated, the characteristics were almost unchanged and good.
- the crystallographic plane index of the n + type SiC semiconductor substrate 1 is a plane parallel to (000-1) or within 10 °, or the n + type SiC semiconductor substrate
- the interface state density between the gate oxide film and the semiconductor interface can be reduced, thereby further improving the mobility of the MOSFET portion. Can be made. As a result, the on-resistance can be made extremely small.
- FIG. 13 is a cross-sectional view of an SiC-MOSFET according to Example 2 of the present invention.
- a 1200 V, 25 A MOSFET was fabricated in the same manufacturing process as in Example 1 described above.
- the p + layer 31 is formed by digging a trench from the surface of the p base layer 4 until it penetrates the p + layer 3, and then ionizing aluminum into the n ⁇ type SiC layer 2 at the bottom of the trench. An injection was formed. Thereafter, the trench was formed so as to be filled with nickel metal electrode and aluminum.
- FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. Both the on-resistance and the load short-circuit withstand capability are the same as those in Example 1, indicating that they are good.
- Example 3 In Example 3, a 1200 V, 25 A MOSFET was manufactured by the same manufacturing process as in Example 1.
- a p base layer 4 instead of the p + layer 3, a p base layer 4 is selectively formed on the surface layer of the n ⁇ type SiC layer 2, and further on the p base layer 4 and the n ⁇ type SiC layer 2.
- a p base layer 4 is deposited.
- p base layer 4 is formed on the surface layer of n ⁇ type SiC layer 2 instead of p + layer 3.
- an n-turnback layer 6 is formed in the p base layer 4 at a depth that does not penetrate the p base layer 4.
- FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. Although the on-resistance is increased by about 10% with respect to Example 1, it can be seen that the normal SiC-MOSFET exhibits sufficiently good resistance characteristics.
- Example 4 In Example 4, a 1200 V, 25 A MOSFET was manufactured by the same manufacturing process as in Example 2. Also in the fourth embodiment, similarly to the third embodiment, a p base layer 4 is selectively formed on the surface layer of the n ⁇ type SiC layer 2 instead of the p + layer 3, and the p base layer 4 and the n ⁇ A p base layer 4 is deposited on the type SiC layer 2. Alternatively, p base layer 4 is formed on the surface layer of n ⁇ type SiC layer 2 instead of p + layer 3. Then, an n-turnback layer 6 is formed in the p base layer 4 at a depth that does not penetrate the p base layer 4.
- FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. Although the on-resistance is increased by about 10% with respect to Example 1, it can be seen that the normal SiC-MOSFET exhibits sufficiently good resistance characteristics.
- the crystallographic plane index of the n + -type SiC semiconductor substrate 1 was inclined by 0 °, 2 °, 8 °, and 10 ° with respect to (000-1) or (0001).
- a device was similarly formed on the surface, and the fabricated device was evaluated. As a result, it was found that there was almost no change in characteristics.
- Example 5 In Example 5, a p-channel MOSFET in which the conductivity type of the impurity was changed as compared with Examples 1 to 4 described above was manufactured, and its characteristics were evaluated.
- the fifth embodiment is obtained by inverting the p-type and the n-type of the first embodiment, and will be described with the same reference numerals as those of the first embodiment.
- a p + type SiC semiconductor substrate 1 is prepared.
- a low resistance p + type SiC semiconductor substrate 1 containing about 2 ⁇ 10 19 cm ⁇ 3 of aluminum as an impurity is used.
- Crystallographic plane index of the p + -type SiC semiconductor substrate 1 is p comprises about 1.0 ⁇ 10 16 cm -3 of aluminum on a plane inclined about 4 ° with respect to (0001) - type SiC layer 2
- Epitaxial growth is carried out by about 10 ⁇ m.
- An n + layer 31 having a width of 2 ⁇ m and a depth of 0.3 ⁇ m is formed on the surface layer of the p ⁇ -type SiC layer 2 by an ion implantation method. Thereafter, the acceleration energy is decreased, and an n + layer 3 having a width of 13 ⁇ m and a depth of 0.5 ⁇ m is formed by ion implantation. Phosphorus was used as the ion at that time.
- the n + layer 31 is arranged at the center of the n + layer 3.
- the doses were set so that the impurity concentrations of these n + layer 31 and n + layer 3 were 1.0 ⁇ 10 18 cm ⁇ 3 .
- the p Uchikaeshi layer coupling portion 13 a part of the n + layer 3 under 6 formed in a subsequent step (see FIGS. 8A, 8B) to be coupled to each other.
- a hexagonal cell pattern was used, but other polygonal shapes such as a quadrangular cell may be used.
- the distance between the n + layers 3 that are not bonded is 2 ⁇ m.
- the n base layer 4 is formed on the n + layer 3 and the p ⁇ type SiC layer 2 to a thickness of 0.5 ⁇ m by an epitaxial growth method.
- impurities of a nitrogen impurity concentration was set to be 5.0 ⁇ 10 16 cm -3.
- aluminum ions are 5.0 ⁇ 10 16 cm ⁇ 3 at a depth of 1.5 ⁇ m and a width of 2.0 ⁇ m as a p-type striking layer 6 formed by ion implantation of a part of the n base layer 4 to p-type.
- a p + source layer and an n + contact layer are selectively formed in the n base layer 4.
- activation annealing is performed.
- the heat treatment temperature and time are 1800 ° C. and 2 minutes.
- a gate oxide film having a thickness of 100 nm is formed by thermal oxidation and annealed in the vicinity of 1000 ° C. in a hydrogen atmosphere.
- phosphorous glass is formed as an interlayer insulating film 9 with a thickness of 1.0 ⁇ m, patterned and heat-treated.
- a source electrode 10 is formed by depositing aluminum containing 1% silicon on the surface with a thickness of 5 ⁇ m by sputtering.
- a nickel film was formed on the back surface of the device and heat-treated at 970 ° C., and then the back electrode 11 was formed by stacking Ti / Ni / Au.
- a protective film is added to the surface on the source electrode 10 side to complete the device.
- FIG. 9 shows the measurement results of the electrical characteristics of the p-channel SiC-MOSFET of Example 5 fabricated as described above.
- the chip size is 3 mm square, the area of the active region is 5.27 mm 2 , and the rated current is 25A.
- the on-resistance (RonA) is a sufficiently low value of 5.2 m ⁇ cm 2, and the initial device breakdown voltage is ⁇ 1430 V, which is sufficiently good for a 1200 V device.
- RonA the on-resistance
- the on-resistance showed an equivalent low value of 5.2 m ⁇ cm 2 , but 700 V between the source and drain.
- the gate oxide film was destroyed. From this, it can be seen that the semiconductor element of the present invention exhibits extremely low on-resistance while maintaining a sufficient element breakdown voltage.
- Example 6 In Example 6, a 1200 V, 25 A MOSFET was fabricated by the same manufacturing process as in Example 5. However, in the sixth embodiment, the n + layer 31 is formed by digging a trench from the surface of the n base layer 4 until it penetrates the n + layer 3 and ion-implanting nitrogen or phosphorus into the p ⁇ type SiC layer 2 at the bottom of the trench. Formed. Thereafter, the trench was formed so as to be filled with metal electrodes (nickel and aluminum). The cross-sectional structure diagram is the same as that in FIG. 13, and the impurity conductivity type is reversed. FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. Both the on-resistance and the load short-circuit withstand capability were almost the same as those of Example 5 and were found to be good.
- Example 7 In Example 7, a 1200 V, 25 A MOSFET was manufactured by the same manufacturing process as in Example 5. However, in Example 7, as in Example 3, the n + layer 3 is not formed, and the n base layer 4 is formed by ion implantation. Other processes and the cell structure are the same as those in the fifth embodiment.
- FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. The on-resistance is increased by about 15% with respect to Example 5, but it can be seen that the normal SiC-MOSFET exhibits sufficiently good resistance characteristics.
- Example 8 In Example 8, a 1200 V, 25 A MOSFET was manufactured by the same manufacturing process as in Example 6. Also in this eighth embodiment, as in the third embodiment, the n + layer 3 is not formed, and the n base layer 4 is formed by ion implantation. Other processes and the cell structure are the same as those in the sixth embodiment.
- FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. The on-resistance is increased by about 15% with respect to Example 5, but it can be seen that the normal SiC-MOSFET exhibits sufficiently good resistance characteristics.
- the crystallographic plane index of the p + type SiC semiconductor substrate 1 was inclined by 0 °, 2 °, 8 °, and 10 ° with respect to (000-1) or (0001).
- a device was similarly formed on the surface, and the fabricated device was evaluated. As a result, it was found that there was almost no change in characteristics.
- Example 9 Figure 14 is a plan view showing the arrangement of the p + layer and the cell of the SiC-MOSFET according to a ninth embodiment of the present invention.
- a 1200 V, 25 A MOSFET was manufactured by the same manufacturing process as in Examples 1 and 2.
- a stripe cell pattern is used. Therefore, the arrangement of the p + layer 3 is coupled to p + layer 3 between the structure shown in FIG. 14.
- Other steps are the same as those in Examples 1 and 2.
- FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. Although the on-resistance increases by about 10% with respect to Example 1, it is understood that the other characteristics hardly deteriorate and that the on-resistance characteristics and the high breakdown voltage characteristics are sufficiently low with respect to a normal SiC-MOSFET.
- Example 10 In Example 10, a 1200 V, 25 A MOSFET was manufactured by the same manufacturing process as in Examples 5 and 6. In Example 10, a stripe cell pattern was used for the design. For this reason, the n + layers 3 are arranged such that the n + layers 3 are coupled to each other by the same structure as that shown in FIG. Other steps are the same as those in Examples 5 and 6.
- FIG. 9 shows the result of evaluating the electrical characteristics of the manufactured element. Although the on-resistance is increased by about 20% compared to Examples 5 and 6, the other characteristics are hardly deteriorated and the on-resistance characteristics and the high withstand voltage characteristics are sufficiently low for a normal SiC-MOSFET. Recognize.
- FIG. 15 is a turn-off switching waveform of the SiC-MOSFET of each embodiment of the present invention
- FIG. 16 is a turn-on switching waveform of the SiC-MOSFET of each embodiment of the present invention.
- (a) is room temperature
- (b) is a temperature environment of 200 ° C.
- the horizontal axis is time
- the vertical axis is voltage and current.
- the present invention can also be applied to an IGBT using a semiconductor substrate having a conductivity type different from that of the MOSFET.
- the conductivity type of the n + -type SiC semiconductor substrate 1 should be p-type in Examples 1 to 4 and 9, and the conductivity type of the p + -type SiC semiconductor substrate 1 is n-type in Examples 5 to 8 and 10. You can do it.
- SiC is likely to exceed the material limit in silicon, future growth is expected greatly in power semiconductor applications, especially in MOSFETs.
- SiC is expected to have a particularly low on-resistance.
- the semiconductor itself and the gate oxide film can be prevented from being destroyed, and the reliability is high. It is possible to provide a vertical SiC-MOSFET, an IGBT structure and a simple manufacturing method thereof that can have a low on-resistance without deterioration.
- a MOSFET and an IGBT that have a low on-resistance, a large breakdown resistance, and a high-speed switching characteristic while maintaining a sufficient element breakdown voltage characteristic regardless of the crystal plane orientation of the substrate. It becomes possible to provide.
- the high voltage semiconductor device and the manufacturing method thereof according to the present invention are useful for power semiconductor devices such as power devices, and power semiconductor devices used for industrial motor control and engine control, for example. .
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Abstract
Description
以下に添付図面を参照して、この発明にかかる高耐圧半導体装置およびその製造方法の好適な実施の形態を詳細に説明する。本明細書および添付図面においては、nまたはpを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、nやpに付す+および-は、それぞれそれが付されていない層や領域よりも高不純物濃度および低不純物濃度であることを意味する。また、ミラー指数の表記において、"-"はその直後の指数につくバーを意味しており、指数の前に"-"を付けることで負の指数を表している。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。
以下、本発明の実施例1について、図面を参照して説明する。図1~図7は、本発明の実施例1にかかるSiC-MOSFET製造工程の断面図である。各図において、(a)は、p+層3が結合していない部分の断面図、(b)は、p+層3が結合している部分の断面図である。この実施例1では、縦型プレーナーゲートMOSFETとして、半導体材料として炭化ケイ素を用い、素子耐圧1200VのMOSFETを示した。
図13は、本発明の実施例2にかかるSiC-MOSFETの断面図である。上述した実施例1と同様の製造工程にて1200V、25AのMOSFETを作製した。ただし、本実施例2ではp+層31の形成法を、pベース層4表面からトレンチをp+層3を貫通するまで掘り、その後、トレンチの底面におけるn-型SiC層2にアルミニウムをイオン注入させて形成した。その後、トレンチは金属電極ニッケルならびにアルミニウムで埋め込むように形成した。作製した素子の電気特性評価結果を図9に示す。オン抵抗、負荷短絡耐量とも実施例1と同等の特性を示しており良好であることがわかる。
実施例3は、実施例1と同様の製造工程にて1200V、25AのMOSFETを作製した。本実施例3では、p+層3に代えて、n-型SiC層2の表面層にpベース層4を選択的に形成し、さらにこのpベース層4およびn-型SiC層2上にpベース層4を堆積する。または、p+層3に代えて、n-型SiC層2の表面層にpベース層4を形成する。そして、pベース層4に、pベース層4を貫通しない深さでn打ち返し層6を形成する。
実施例4は、実施例2と同様の製造工程にて1200V、25AのMOSFETを作製した。本実施例4においても実施例3同様に、p+層3に代えて、n-型SiC層2の表面層にpベース層4を選択的に形成し、さらにこのpベース層4およびn-型SiC層2上にpベース層4を堆積する。または、p+層3に代えて、n-型SiC層2の表面層にpベース層4を形成する。そして、pベース層4に、pベース層4を貫通しない深さでn打ち返し層6を形成する。
実施例5では、上記の実施例1~4に対し、不純物の導電型を変えたpチャネルMOSFETを作製しその特性を評価した。実施例5は、実施例1のp型とn型とを反転させたものであり、実施例1と同じ符号を付して説明する。まず、p+型SiC半導体基板1を用意する。ここでは、不純物としてアルミニウムを2×1019cm-3程度含む低抵抗のp+型SiC半導体基板1とした。前記p+型SiC半導体基板1の結晶学的面指数は(0001)に対して4°ほど傾いた面の上にアルミニウムを1.0×1016cm-3程度含むp-型SiC層2を10μm程度エピタキシャル成長させる。このp-型SiC層2の表面層に幅2μmで深さ0.3μmのn+層31をイオン注入法で形成する。その後加速エネルギーを減少させて、幅13μmで深さ0.5μmのn+層3をイオン注入法で形成する。その際のイオンはリンを用いた。またn+層31はn+層3の中心に配置するようにした。
実施例6は、実施例5と同様の製造工程にて1200V、25AのMOSFETを作製した。ただし本実施例6ではn+層31の形成法を、nベース層4表面からトレンチをn+層3を貫通するまで掘り、トレンチの底面におけるp-型SiC層2に窒素またはリンをイオン注入させて形成した。その後、トレンチは金属電極(ニッケルならびにアルミニウム)で埋め込むように形成した。断面構造図は図13と同じで、不純物の導電型が逆転した構造となる。作製した素子の電気特性評価結果を図9に示す。オン抵抗、負荷短絡耐量とも実施例5とほぼ同等の特性を示しており良好であることがわかった。
実施例7は、実施例5と同様の製造工程にて1200V、25AのMOSFETを作製した。ただし本実施例7においても、実施例3同様に、n+層3を形成せず、nベース層4をイオン注入法で形成する。その他の工程、セル構造は実施例5と同一である。作製した素子の電気特性評価結果を図9に示す。オン抵抗は実施例5に対し、15%ほど増加しているが通常のSiC-MOSFETに対しては十分良好な抵抗特性を示していることがわかる。
実施例8は、実施例6と同様の製造工程にて1200V、25AのMOSFETを作製した。この本実施例8においても、実施例3同様に、n+層3を形成せず、nベース層4をイオン注入法で形成する。その他の工程、セル構造は実施例6と同一である。作製した素子の電気特性評価結果を図9に示す。オン抵抗は実施例5に対し、15%ほど増加しているが通常のSiC-MOSFETに対しては十分良好な抵抗特性を示していることがわかる。
図14は、本発明の実施例9にかかるSiC-MOSFETのp+層とセルの配置を表す平面図である。実施例9は、実施例1、2と同様の製造工程にて1200V、25AのMOSFETを作製した。本実施例9ではストライプセルパターンで設計した。そのため、p+層3の配置は図14に示す構造でp+層3同士を結合させている。その他の工程は実施例1、2と同一である。作製した素子の電気特性評価結果を図9に示す。オン抵抗は実施例1に対し、10%ほど増加するものの、他の特性はほとんど劣化せず通常のSiC-MOSFETに対しては十分低いオン抵抗特性と高耐圧特性を示していることがわかる。
実施例10は、実施例5、6と同様の製造工程にて1200V、25AのMOSFETを作製した。本実施例10ではストライプセルパターンで設計した。そのため、n+層3の配置は、図14同様の構造によりn+層3同士を結合させている。その他の工程は実施例5,6と同一である。作製した素子の電気特性評価結果を図9に示す。オン抵抗は実施例5,6に対し、20%ほど増加するものの、他の特性はほとんど劣化せず通常のSiC-MOSFETに対しては十分低いオン抵抗特性と高耐圧特性を示していることがわかる。
2 第1導電型半導体層
3 第2導電型高濃度半導体層
4 第2導電型低濃度半導体層
5 第1導電型ソース領域
6 第1導電型ウェル領域
8 ゲート電極層
10 ソース電極
11 ドレイン電極
13 結合部
31 第2導電型領域
Claims (11)
- 第1導電型半導体基板と、
前記第1導電型半導体基板上に形成され、前記第1導電型半導体基板よりも低濃度な第1導電型半導体層と、
前記第1導電型半導体層の表面に選択的に形成された高濃度の第2導電型高濃度半導体層と、
前記第1導電型半導体層ならびに前記第2導電型高濃度半導体層の上に形成された前記第2導電型高濃度半導体層よりも低濃度の第2導電型低濃度半導体層と、
前記第2導電型低濃度半導体層の表面層に選択的に形成された第1導電型ソース領域と、
前記第1導電型半導体基板のおもて面から前記第2導電型低濃度半導体層を貫通して前記第1導電型半導体層に達するように形成された第1導電型ウェル領域と、
前記第1導電型ソース領域と前記第1導電型ウェル領域とに挟まれた前記第2導電型低濃度半導体層の表面露出部上にゲート絶縁膜を介して設けられたゲート電極層と、
前記第1導電型ソース領域と前記第2導電型低濃度半導体層とに接触するソース電極と、
前記第1導電型半導体基板の裏面に設けられたドレイン電極を有する縦型の高耐圧半導体装置において、
前記第2導電型高濃度半導体層の一部が前記第1導電型ウェル領域の前記ドレイン電極側の領域で結合部により結合されており、かつ前記第2導電型高濃度半導体層の前記ドレイン電極側の一部に接するように形成された第2導電型高濃度領域を有することを特徴とする高耐圧半導体装置。 - 第1導電型半導体基板と、
前記第1導電型半導体基板上に形成され、前記第1導電型半導体基板よりも低濃度な第1導電型半導体層と、
前記第1導電型半導体層の表面に選択的に形成された第2導電型低濃度半導体層と、
前記第2導電型低濃度半導体層の表面層に選択的に形成された第1導電型ソース領域と、
前記第1導電型半導体基板のおもて面から前記第2導電型低濃度半導体層を貫通して前記第1導電型半導体層に達するように形成された第1導電型ウェル領域と、
前記第1導電型ソース領域と前記第1導電型ウェル領域とに挟まれた前記第2導電型低濃度半導体層の表面露出部上にゲート絶縁膜を介して設けられたゲート電極層と、
前記第1導電型ソース領域と前記第2導電型低濃度半導体層とに接触するソース電極と、
前記第1導電型半導体基板の裏面に設けられたドレイン電極を有する縦型の高耐圧半導体装置において、
前記第2導電型低濃度半導体層の一部が前記第1導電型ウェル領域の前記ドレイン電極側の領域で結合部により結合されており、かつ前記第2導電型低濃度半導体層の前記ドレイン電極側の一部に接するように形成された第2導電型高濃度領域を有することを特徴とする高耐圧半導体装置。 - おもて面側から前記第2導電型低濃度半導体層および前記第2導電型高濃度半導体層を貫通して前記第2導電型高濃度領域に達するトレンチをさらに備え、
前記ソース電極は、前記トレンチの内部に埋め込まれるように設けられていることを特徴とする請求項1に記載の高耐圧半導体装置。 - おもて面側から前記第2導電型低濃度半導体層を貫通して前記第2導電型高濃度領域に達するトレンチをさらに備え、
前記ソース電極は、前記トレンチの内部に埋め込まれるように設けられていることを特徴とする請求項2に記載の高耐圧半導体装置。 - 前記第1導電型半導体基板の材料が炭化ケイ素であることを特徴とする請求項1に記載の高耐圧半導体装置。
- 前記第1導電型半導体基板の結晶学的面指数は(000-1)に対して平行な面もしくは10度以内に傾いた面であることを特徴とする請求項1に記載の高耐圧半導体装置。
- 前記第1導電型半導体基板の結晶学的面指数は(0001)に対して平行な面もしくは10度以内に傾いた面であることを特徴とする請求項1~5のいずれか一つに記載の高耐圧半導体装置。
- 第1導電型半導体基板上に、前記第1導電型半導体基板よりも低濃度な第1導電型半導体層をエピタキシャル成長させる第1の工程と、
イオン注入法により、前記第1導電型半導体層の表面層に第2導電型高濃度領域を選択的に形成する第2の工程と、
イオン注入法により、前記第1導電型半導体層の表面層に第2導電型高濃度半導体層よりも浅い深さで、かつ第2導電型高濃度半導体層に接するように前記第2導電型高濃度領域を形成する第3の工程と、
前記第1導電型半導体層ならびに前記第2導電型高濃度半導体層の上に、第2導電型低濃度半導体層をエピタキシャル成長法により形成する第4の工程と、
前記第2導電型低濃度半導体層の表面層に選択的に第1導電型ソース領域と、おもて面側から前記第2導電型低濃度半導体層を貫通して前記第1導電型半導体層に達する第1導電型ウェル領域とをイオン注入法により形成する第5の工程と、
を有し、
前記第3の工程では、前記第2導電型高濃度半導体層の一部が前記第1導電型ウェル領域の下の領域で結合されるように前記第2導電型高濃度半導体層を形成することを特徴とする高耐圧半導体装置の製造方法。 - 前記第2の工程では、前記第1導電型半導体層の表面からトレンチ溝を形成し、当該トレンチ溝の底面に前記第2導電型高濃度領域をイオン注入法により形成したことを特徴とする請求項8に記載の高耐圧半導体装置の製造方法。
- 第1導電型半導体基板上に、前記第1導電型半導体基板よりも低濃度な第1導電型半導体層をエピタキシャル成長で形成する工程と、
前記第1導電型半導体層の表面に、第2導電型高濃度領域をイオン注入法により選択的に形成する工程と、
前記第1導電型半導体層ならびに前記第2導電型高濃度領域の上に、第2導電型低濃度半導体層を選択的にイオン注入法により形成する工程と、
前記第2導電型低濃度半導体層の表面層に選択的に第1導電型ソース領域、およびおもて面側から前記第2導電型低濃度半導体層に当該第2導電型低濃度半導体層を貫通しない深さの第1導電型ウェル領域、をイオン注入法により形成する工程と、
を有することを特徴とする高耐圧半導体装置の製造方法。 - 第1導電型半導体基板上に、前記第1導電型半導体基板よりも低濃度な第1導電型半導体層をエピタキシャル成長で形成する工程と、
前記第1導電型半導体層の表面に、第2導電型低濃度半導体層をイオン注入法により選択的に形成する工程と、
前記第2導電型低濃度半導体層の表面層に選択的に第1導電型ソース領域を形成する工程と、
おもて面側から前記第2導電型低濃度半導体層に、当該第2導電型低濃度半導体層を貫通しない深さで第1導電型ウェル領域をイオン注入法により形成する工程と、
前記第2導電型低濃度半導体層の表面から前記第1導電型半導体層に達するトレンチ溝を形成し、当該トレンチ溝の底面に前記第2導電型低濃度半導体層の下部の一部に接するように第2導電型領域をイオン注入法により形成する工程と、
を有することを特徴とする高耐圧半導体装置の製造方法。
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JP2018082053A (ja) * | 2016-11-16 | 2018-05-24 | 富士電機株式会社 | 炭化珪素半導体素子および炭化珪素半導体素子の製造方法 |
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DE112014003637B4 (de) | 2023-07-27 |
JP6241958B2 (ja) | 2017-12-13 |
US20160155836A1 (en) | 2016-06-02 |
CN105474403B (zh) | 2018-10-23 |
CN105474403A (zh) | 2016-04-06 |
DE112014003637T5 (de) | 2016-04-14 |
JPWO2015019797A1 (ja) | 2017-03-02 |
US10263105B2 (en) | 2019-04-16 |
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